KR20160074775A - Gate shift register and flat panel display using the same - Google Patents

Abstract

The present invention relates to a gate shift register for facilitating a narrow bezel design by simplifying the circuit configuration of each of stages, and a flat panel display using the same. The gate shift register of the present invention includes the stages which forwardly output scan pulses in a forward shift mode, and reversely output the scan pulse in a backward shift mode. Each of the stages may include a scan direction control part which controls a scan direction by outputting a precharge voltage in response to a forward carry signal or a backward carry signal, a node control part which controls the voltage of a first and a second node in response to the precharge voltage and a reset signal, and an output part which outputs the scan pulse according to the voltage level of the first and the second node.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate shift register and a flat panel display using the gate shift register,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate shift register and a flat panel display using the same, and more particularly, to a gate shift register and a flat panel display using the gate shift register.

2. Description of the Related Art In recent years, products in which a gate drive circuit of a flat panel display device is constituted by a gate shift register capable of bi-directional shift operation are being released. The plurality of stages provided in the bidirectional gate shift register outputs scan pulses in the forward shift mode from the first stage to the last stage and outputs scan pulses in the reverse shift mode from the last stage to the first stage.

On the other hand, recent display devices are in the trend of narrow bezel. Accordingly, a GIP (Gate In Panel) type display device which can reduce the volume and weight of a display device by embedding a gate driving circuit in a display panel and reduce a manufacturing cost is emerging.

However, the conventional bidirectional gate shift register requires at least seven signal lines for driving each of a plurality of stages, at least sixteen thin film transistors constituting each stage are required, and it is difficult to reduce the design area there was.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gate shift register and a flat panel display using the gate shift register, which can simplify the narrow bezel design by simplifying the circuit configuration of each of a plurality of stages.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

According to another aspect of the present invention, there is provided a gate shift register and a flat panel display using the gate shift register. The gate shift register and the flat panel display device according to the present invention sequentially output scan pulses in a forward shift mode and inversely sequentially output the scan pulses in a backward shift mode, Wherein each of the plurality of stages includes a scan direction control unit for controlling a scan direction by outputting a precharge voltage in response to a forward carry signal or a backward carry signal and a scan direction control unit for controlling the scan direction in response to the precharge voltage and the reset signal, And an output unit for outputting the scan pulse according to a voltage level of the first and second nodes, wherein the node control unit includes a gate electrode connected to the first node, And a second electrode connected to the gate-off voltage supply line, A second transistor including a first electrode connected to the supply line of the reset signal and a first electrode and a second electrode connected to the second node, a gate electrode connected to the second node, A third transistor including a first electrode connected to the first node, a second transistor connected to the gate-off voltage supply line, a gate electrode connected to the gate-on voltage supply line, a first electrode connected to the first node, A fourth transistor including a second electrode connected to the output, a first capacitor disposed between the first electrode of the fourth transistor and the gate-off voltage supply line, and a second capacitor coupled between the second node and the gate- And a second capacitor disposed between the supply lines.

According to the solution of the above-mentioned problems, the present invention has the following effects.

The present invention simplifies the circuit configuration of each of a plurality of stages and reduces the number of wires, thereby facilitating narrow bezel design.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below, or may be apparent to those skilled in the art from the description and the description.

1 is a configuration diagram of a flat panel display device having a gate shift register according to the present invention.
2 is a configuration diagram of the first and second gate shift registers.
3A and 3B illustrate operations of the first and second gate shift registers according to the forward shift mode and the backward shift mode.
4 is a driving waveform diagram of the first and second gate shift registers shown in FIG.
5 is a configuration circuit diagram of any stage ST (LST or RST) shown in FIG.
FIGS. 6A to 6D are diagrams for explaining a stepwise method of driving the stage ST shown in FIG.
7 is a view for explaining the operation of each stage in response to an abnormal power-off signal.
8A and 8B are layouts in which the gate shift register of the present invention is compared with the conventional technique.

The meaning of the terms described herein should be understood as follows. The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms. It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one. The term "on" means not only when a configuration is formed directly on top of another configuration, but also when a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of a gate shift register and a flat panel display using the gate shift register according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a flat panel display device having a gate shift register according to the present invention. 2 is a configuration diagram of the first and second gate shift registers. 3A and 3B illustrate operations of the first and second gate shift registers according to the forward shift mode and the backward shift mode.

1, a flat panel display device according to the present invention includes a display panel 2, gate drivers 4a and 4b, a data driver 6, and a timing controller 8.

The display panel 2 includes a plurality of gate lines GL and a plurality of data lines DL intersecting with each other and a plurality of pixels P are provided at intersections of the display lines GL and DL. Each pixel P displays an image according to a video signal (data voltage) supplied from the data line DL in response to a scan pulse SCAN supplied from the gate line GL.

The gate drivers 4a and 4b are GIP (gate in panel) type gate drivers and are formed in a non-display area of the display panel 2. [ The gate drivers 4a and 4b may be provided on one side of the display panel 2 or on both sides of the display panel 2 to drive a plurality of gate lines GL.

Preferably, the gate drivers 4a and 4b are provided on both sides of the display panel 2, respectively. That is, the gate drivers 4a and 4b are built in a non-display area on one side of the display panel 2 and are provided with a first gate shift register (not shown) for supplying a scan pulse to the odd gate lines GL among the plurality of gate lines GL And a second gate shift register 40b for supplying scan pulses to the even-numbered gate lines GL among the plurality of gate lines GL. The present invention has the effect of facilitating the design of the narrow bezel by reducing the area of the non-display area.

The first and second gate shift registers 40a and 40b are disposed on both sides of the plurality of gate lines GL and connected to the plurality of gate lines GL as shown in FIG. The first and second gate shift registers 40a and 40b are configured to enable bi-directional shift operation. That is, the first and second gate shift registers 40a and 40b sequentially output scan pulses in the forward shift mode and inversely sequentially output the scan pulses in the backward shift mode.

Referring to FIG. 3A, in the forward shift mode, the second gate shift register 40b generates a scan signal in response to a Kth scan pulse applied to the gate line of the first gate shift register K (K is an odd number) Th scan pulse is applied to the (K + 1) th gate line in response to the (K + 1) th scan pulse, and the first gate shift register 40a applies the (K + .

Referring to FIG. 3B, in the backward shift mode, the first gate shift register 40a is responsive to a J th scan pulse applied to the J (j is an even) gate line by the second gate shift register 40b Th scan pulse is applied to the (J-1) th gate line, and the second gate shift register 40b applies the (J-2) th scan pulse in response to the J- Th gate line.

In the present invention, the gate shift register disposed on one side of the gate line GL outputs its own scan pulse in response to the scan pulse output from the gate shift register disposed on the other side, so that the number of the clock signal supply lines is halved Can be reduced. Therefore, the present invention can reduce the number of wirings connected to the gate shift register and simplify the design of the narrow bezel.

On the other hand, the first gate shift register 40a includes a plurality of left-side stages (LST) connected in a dependent manner. The plurality of left stages LST are selectively connected to a clock signal supply line to which the first and second clock signals CLK1 and CLK2 are supplied so that the scan pulse SCAN is sequentially applied to the odd gate lines GL Output. The second gate shift register 40b includes a plurality of right-side stages (RST) connected in a dependent manner. The plurality of right stages RST are selectively connected to a clock signal supply line to which the third and fourth clock signals CLK3 and CLK4 are supplied to sequentially supply the scan pulse SCAN to the even gate lines GL Output.

Each of the left stages LST includes first to fourth input terminals IN1 to IN4 and an output terminal OUT. The first input terminal IN1 is connected to one of the supply lines of the first and second clock signals CLK1 and CLK2 and the other is connected to the second input terminal IN2. A supply line of a forward carry signal is connected to the third input terminal IN3, and a supply line of a reverse carry signal is connected to the fourth input terminal IN4.

The forward carry signal may be a scan pulse applied to the (n-1) th gate line GL from the right stage RST. The backward carry signal may be a scan pulse applied to the (n + 1) th gate line GL from the right stage RST. However, in the forward shift mode, the forward start signal VST is applied to the third input terminal IN3 of the first left stage LST. In the reverse shift mode, a reverse start signal is applied to the fourth input terminal IN4 of the last left stage LST.

Each of the right stages RST includes first to fourth input terminals IN1 to IN4 and an output terminal OUT. One of the supply lines of the third and fourth clock signals CLK3 and CLK4 is connected to the first input terminal IN1 and the other is connected to the second input terminal IN2. A supply line of a forward carry signal is connected to the third input terminal IN3, and a supply line of a reverse carry signal is connected to the fourth input terminal IN4.

The forward carry signal may be a scan pulse applied to the (n-1) th gate line GL from the left stage LST. The backward carry signal may be a scan pulse applied to the (n + 1) th gate line GL from the left stage RST.

Meanwhile, the first to fourth clock signals CLK1 to CLK4 are sequentially delayed and output repeatedly. 4, the first to fourth clock signals CLK1 to CLK4 may include a first clock signal CLK1, a third clock signal CLK3, a second clock signal CLK2, And the fourth clock signal CLK4.

5 is a configuration circuit diagram of any stage ST (LST or RST) shown in FIG.

Referring to FIG. 5, the stage ST of the present invention includes a scan direction controller 100, a node controller 200, and an output unit 300. This stage ST includes 10 transistors and 2 capacitors. The present invention can reduce the circuit configuration of each stage and the number of signal lines connected to each stage, thereby simplifying the narrow bezel design.

The scan direction controller 100 controls the scan direction by outputting a precharge voltage in response to a forward carry signal or a reverse carry signal. To this end, the scan direction controller 100 includes first and second transistors T1 and T2.

The first transistor T1 includes a third input terminal IN3, that is, a gate electrode and a first electrode connected to a supply line of the forward carry signal, and a second electrode connected to the first node. The first transistor T1 supplies a precharge voltage to the first node Q in response to a forward carry signal in a forward shift mode.

The second transistor T2 has a fourth input terminal IN4, that is, a gate electrode and a first electrode connected to the supply line of the reverse carry signal, and a second electrode connected to the first node, Transistor. This second transistor T2 supplies the pre-charge voltage to the first node Q in response to the reverse carry signal in the reverse shift mode.

The node controller 200 controls the voltages of the first node Q and the second node QB in response to the precharge voltage and the reset signal provided from the scan direction controller 100. To this end, the node controller 200 includes first through sixth transistors T1 through T6 and first and second capacitors C1 and C2.

The third transistor T3 includes a gate electrode connected to the first node Q, a first electrode connected to the second node QB, and a second electrode connected to the gate-off voltage supply line . The third transistor T3 discharges the second node QB to the gate-off voltage VGL in a period in which the first node Q is charged.

The fourth transistor T4 includes a gate electrode and a first electrode connected to a second input terminal IN2, that is, a supply line of the reset signal, and a second electrode connected to the second node QB . The fourth transistor T4 supplies a reset signal to the second node QB. For reference, the reset signal may be any one selected from the first and second clock signals CLK1 and CLK2. Also, the reset signal may be a scan pulse output from the next stage.

The fifth transistor T5 includes a gate electrode connected to the second node QB, a first electrode connected to the first node Q, and a second electrode connected to the gate-off voltage supply line . The fifth transistor T5 discharges the first node Q to the gate-off voltage VGL in a period in which the second node QB is charged.

The sixth transistor T6 includes a gate electrode connected to a gate-on voltage supply line, a first electrode connected to the first node Q, and a second electrode connected to the output unit 300. [ The sixth transistor T6 supplies the precharge voltage charged in the first node Q to the boost node BST of the output unit 300. [ In particular, when the voltage of the boost node BST is higher than the gate-on voltage VGH during a period in which the clock signal is supplied to the first electrode of the pull-up transistor PU of the output unit 300, , So that the voltage charged in the boost node (BST) is prevented from being supplied to the first node (Q). This invention can prevent a plurality of transistors connected to the first node Q from being damaged.

The first capacitor C1 is disposed between the first electrode of the sixth transistor T1 and the gate-off voltage supply line. The first capacitor C1 maintains the voltage charged in the first node Q for a specific period of time.

The second capacitor (C2) is disposed between the second node (QB) and the gate-off voltage supply line. The second capacitor (C2) maintains the voltage charged in the second node (QB) for a specific period of time.

The node controller 200 may further include a residual image removing unit for removing a residual image that may be generated on the screen when the display apparatus is abnormally turned off. This residual image remover outputs the gate-on voltage VGH to the output terminal in response to an abnormal power-off signal APO provided from the outside when the display apparatus is abnormally turned off. To this end, the residual image removing unit includes seventh and eighth transistors T7 and T8.

The seventh transistor T7 is connected to a gate electrode and a first electrode connected to a supply line of an abnormal power-off signal, and to the output terminal OUT. The seventh transistor T7 outputs the abnormal power-off signal APO to the output terminal OUT in response to an abnormal power-off signal APO having a gate-on voltage VGH.

The eighth transistor T8 includes a gate electrode connected to a supply line of the abnormal power supply OFF signal, a first electrode connected to the second node (QB), and a second electrode connected to the gate-off voltage supply line . The eighth transistor T8 discharges the second node QB to the gate-off voltage VGL in response to the abnormal power-off signal APO.

The output unit 300 includes a pull-up transistor PU and a pull-down transistor PD.

The pull-up transistor PU includes a gate electrode connected to the boost node BST, a first electrode connected to a first input terminal IN1, i.e., a supply line of a clock signal, and a second electrode connected to the output terminal .

The pull-down transistor PD includes a gate electrode connected to the second node QB, a first electrode connected to the output terminal OUT, and a second electrode connected to the gate-off voltage supply line.

FIGS. 6A to 6D are diagrams for explaining a stepwise method of driving the stage ST shown in FIG. Hereinafter, the operation of each stage ST in the forward shift mode will be described with reference to Figs. 6A to 6D.

Referring to FIG. 6A, a forward carry signal is input through a third input terminal IN3 in a first period P1. Then, the forward carry signal is supplied to the first node (Q) through the first transistor (T1) as a precharge voltage. Thus, the third transistor T3 connected to the first node Q is turned on and the second node QB is discharged to the gate-off voltage VGL. Accordingly, the fifth transistor T5 and the pull-down transistor PD connected to the second node Q are turned off. On the other hand, the pre-charge voltage supplied to the first node Q is supplied to the boost node BST through the sixth transistor T6.

6B, a clock signal, for example, the second clock signal CLK2 is input to the gate-on voltage VGH through the first input terminal IN1 in the second period P2. Then, the voltage of the first node Q is bootstrapped by the parasitic capacitance of the pull-up transistor PU, and is raised to a level higher than the pre-charge voltage. As a result, the pull-up transistor PU is in a complete turn-on state, and the pull-up transistor PU supplies the second clock signal CLK2 as a scan pulse to the output terminal OUT. At this time, the sixth transistor T6 is turned off as the boost node BST rises to a level higher than the precharge voltage, so that the boosted voltage at the boost node BST is not supplied to the first node Q Do not.

6C, in the third period P3, the second clock signal CLK2 inputted through the first input terminal IN1 falls to the gate-off voltage VGL, The scan pulse supplied to the scan electrode Y is lowered to the gate-off voltage VGL. At this time, the voltage of the first node Q keeps the pre-charge voltage by the first capacitor C1.

Referring to FIG. 6D, a reset signal, for example, the first clock signal CLK1 is input to the gate-on voltage (VGH) state through the second input terminal IN2 in the fourth period P4. Then, a reset signal is applied to the second node QB via the fourth transistor T4 to charge the second node QB. Thus, the fifth transistor T5 connected to the second node QB is turned on so that the first node Q is discharged to the gate-off voltage VGL and the pull-up transistor PU is turned off. On the other hand, as the second node QB is charged, the pull-down transistor PD is turned on and the pull-down transistor PD supplies the gate-off voltage VGL to the output terminal OUT. The pull-down transistor PD is turned on until the forward carry signal is input to the third input terminal IN3 in the next frame period to supply the gate-off voltage VGL to the output terminal OUT. Thus, the operation of the stage ST is completed.

The operation of each stage ST in the backward shift mode is mostly the same as that of the forward shift mode except that the backward carry signal is inputted through the fourth input terminal IN4 in the first period P1.

Meanwhile, as described above, the stage ST of the present invention is provided with a residual image removing unit for removing a residual image that may be generated on the screen when the display apparatus is abnormally turned off, Respectively.

Referring to FIG. 7, when the display device is abnormally turned off, an abnormal power-off signal APO is generated from the outside and supplied to all the stages ST at the same time.

When the abnormal power-off signal APO is supplied, the seventh and eighth transistors T7 and T8 are turned on. Then, the seventh transistor T7 supplies an abnormal power-off signal APO of the gate-on voltage (VGH) state to the output terminal OUT. And the eighth transistor T8 discharges the second node QB to the gate-off voltage VGL to turn off the fifth transistor T5 and the pull-down transistor PD. The present invention eliminates the afterimage that can be generated temporarily by causing all the stages to output the gate-on voltage VGH irrespective of the current operation state of each of the stages when the display device is abnormally turned off.

8A and 8B are layouts in which the gate shift register of the present invention is compared with the conventional technique.

The bidirectional gate shift register of the prior art requires at least seven signal wires for driving each of the plurality of stages, and at least sixteen transistors are required to constitute each stage. Thus, the gate shift register according to the prior art is designed to have a width of 0.7 mm or more, as shown in FIG. 8A.

On the other hand, the gate shift register of the present invention has five signal lines for driving each of a plurality of stages (two clock signal supply lines, one abnormal power supply OFF signal supply line, two gate ON voltages and gate OFF voltage supply lines ), And 10 and 2 transistors and capacitors constituting each stage are required. Accordingly, the gate shift register according to the present invention can be designed to have a width of 0.4 mm as shown in FIG. 8B, and it is possible to reduce a width of at least 0.3 mm compared with the conventional technique.

As described above, the present invention simplifies the circuit configuration of each of a plurality of stages and reduces the number of wires, thereby facilitating narrow bezel design.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of. Therefore, the scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present invention.

40a: first gate shift register 40b: second gate shift register
LST: left stage RST: right stage

Claims (7)

A plurality of stages for sequentially outputting scan pulses in a forward shift mode and outputting the scan pulses in a reverse shift mode in a backward shift mode;
Wherein each of the plurality of stages includes a scan direction controller for controlling a scan direction by outputting a precharge voltage in response to a forward carry signal or a reverse carry signal and a scan direction controller for controlling a voltage of the first and second nodes in response to the precharge voltage and the reset signal And an output unit for outputting the scan pulse according to a voltage level of the first and second nodes;
The node control unit
A first transistor including a gate electrode connected to the first node, a first electrode connected to a second node, and a second electrode connected to a gate-off voltage supply line;
A second transistor including a gate electrode and a first electrode connected to a supply line of a reset signal, and a second electrode connected to the second node;
A third transistor including a gate electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to the gate-off voltage supply line;
A fourth transistor including a gate electrode connected to the gate-on voltage supply line, a first electrode connected to the first node, and a second electrode connected to the output unit;
A first capacitor disposed between the first electrode of the fourth transistor and the gate-off voltage supply line; And
And a second capacitor disposed between the second node and the gate-off voltage supply line. The method according to claim 1,
The scan direction control unit
A fifth transistor including a gate electrode and a first electrode connected to the supply line of the forward carry signal, and a second electrode connected to the first node; And
And a sixth transistor including a gate electrode and a first electrode connected to a supply line of the reverse carry signal and a second electrode connected to the first node. The method according to claim 1,
The output
A pull-up transistor including a gate electrode connected to a second electrode of the fourth transistor, a first electrode connected to a supply line of a clock signal, and a second electrode connected to the output terminal; And
A pull-down transistor including a gate electrode connected to the second node, a first electrode connected to the output terminal, and a second electrode connected to the gate-off voltage supply line. The method according to claim 1,
The node control unit
A seventh transistor including a gate electrode and a first electrode connected to a supply line of an abnormal power-off signal, and a second electrode connected to the output terminal; And
Further comprising an eighth transistor including a gate electrode connected to a supply line of the abnormal power supply OFF signal, a first electrode connected to the second node, and a second electrode connected to the gate OFF voltage supply line, Shift register. A display panel having a plurality of gate lines;
A first gate shift register which is embedded in a non-display area on one side of the display panel and supplies a scan pulse to odd-numbered gate lines among the plurality of gate lines; And
And a second gate shift register which is embedded in a non-display area on the other side of the display panel and supplies the scan pulse to even-numbered gate lines among the plurality of gate lines;
Wherein each of the first and second gate shift registers comprises the gate shift register according to any one of claims 1 to 4. 6. The method of claim 5,
In the forward shift mode,
The second gate shift register applies a (K + 1) -th scan pulse to the (K + 1) -th gate line in response to a K-th scan pulse applied to the K-th gate line by the first gate shift register ,
And the first gate shift register applies a (K + 2) th scan pulse to the (K + 2) th gate line in response to the (K + 1) th scan pulse. 6. The method of claim 5,
In the reverse shift mode,
The first gate shift register applies a (J-1) th scan pulse to the (J-1) th gate line in response to a Jth scan pulse applied to the second gate line by the second gate shift register J ,
And the second gate shift register applies a (J-2) th scan pulse to the (J-2) th gate line in response to the (J-1) th scan pulse.

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