KR102278812B1 - Gate shift register and flat panel display using the same - Google Patents

Abstract

The present invention relates to a gate shift register capable of facilitating narrow bezel design by simplifying the circuit configuration of each of a plurality of stages, and a flat panel display device using the same. The gate shift register of the present invention sequentially transmits scan pulses in forward shift mode. and a plurality of stages for outputting the scan pulses in reverse sequential order in reverse shift mode, wherein each of the plurality of stages controls the scan direction by outputting a precharge voltage in response to a forward carry signal or a reverse carry signal. a scan direction controller, a node controller for controlling voltages of first and second nodes in response to the pre-charge voltage and a reset signal, and an output unit for outputting the scan pulses according to voltage levels of the first and second nodes may include

Description

GATE SHIFT REGISTER AND FLAT PANEL DISPLAY USING THE SAME

The present invention relates to a gate shift resistor and a flat panel display using the same, and more particularly, to a gate shift resistor capable of easily designing a narrow bezel and a flat panel display using the same.

Recently, products in which a gate driving circuit of a flat panel display device is configured with a gate shift resistor capable of bidirectional shift operation have been released. A plurality of stages provided in the bidirectional gate shift register outputs scan pulses from the first stage to the last stage in the forward shift mode, and outputs scan pulses from the last stage to the first stage in the reverse shift mode.

Meanwhile, a recent display device has a narrow bezel trend. Accordingly, a gate in panel (GIP) type display device capable of reducing the volume and weight of the display device and reducing manufacturing cost by embedding the gate driving circuit in the display panel has emerged.

However, the conventional bidirectional gate shift register requires at least 7 signal wires for driving each of a plurality of stages, and at least 16 thin film transistors constituting each stage, making it difficult to reduce the design area. there was.

The present invention has been devised to solve the above problems, and it is a technical task to provide a gate shift register capable of facilitating a narrow bezel design by simplifying a circuit configuration of each of a plurality of stages, and a flat panel display using the same.

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those skilled in the art from such description and description.

A gate shift register and a flat panel display using the same according to the present invention for achieving the above technical problem are a plurality of stages that sequentially output scan pulses in a forward shift mode and reversely output the scan pulses in a reverse shift mode wherein each of the plurality of stages includes a scan direction controller configured to control a scan direction by outputting a precharge voltage in response to a forward carry signal or a reverse carry signal, and first and second stages in response to the precharge voltage and reset signal. a node control unit for controlling a voltage of a node; and an output unit for outputting the scan pulses according to voltage levels of the first and second nodes, wherein the node control unit includes a gate electrode connected to the first node and a second node a first transistor comprising a first electrode connected to and a second electrode connected to a gate-off voltage supply line, a gate electrode and a first electrode connected to a supply line of a reset signal, and a second electrode connected to the second node A second transistor comprising a second electrode, a gate electrode coupled to the second node, a first electrode coupled to the first node, a third transistor comprising a second electrode coupled to a gate-off voltage supply line, gate on A fourth transistor including a gate electrode connected to a voltage supply line, a first electrode connected to the first node, and a second electrode connected to the output unit, a first electrode of the fourth transistor and the gate-off voltage supply a first capacitor disposed between the lines, and a second capacitor disposed between the second node and the gate-off voltage supply line.

According to the means for solving the above problems, the present invention has the following effects.

According to the present invention, the narrow bezel design can be facilitated by simplifying the circuit configuration of each of a plurality of stages and reducing the number of wirings.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those of ordinary skill in the art from such description and description.

1 is a block diagram of a flat panel display having a gate shift register according to the present invention.
2 is a configuration diagram of first and second gate shift registers.
3A and 3B are diagrams for explaining the operations of the first and second gate shift registers according to the forward shift mode and the reverse shift mode.
FIG. 4 is a driving waveform diagram of the first and second gate shift registers shown in FIG. 2 .
FIG. 5 is a configuration circuit diagram of an arbitrary stage (ST: LST or RST) shown in FIG. 2 .
6A to 6D are diagrams for explaining a method of driving the stage ST shown in FIG. 5 in stages.
7 is a view for explaining the operation of each stage according to an abnormal power-off signal.
8A and 8B are layouts comparing the gate shift register of the prior art and the present invention.

The meaning of the terms described herein should be understood as follows. The singular expression is to be understood as including the plural expression unless the context clearly defines otherwise, and the terms "first", "second", etc. are used to distinguish one element from another, The scope of rights should not be limited by these terms. It should be understood that terms such as “comprise” or “have” do not preclude the possibility of addition or existence of one or more other features or numbers, steps, operations, components, parts, or combinations thereof. The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It means a combination of all items that can be presented from more than one. The term "on" is meant to include not only cases in which a component is formed directly on top of another component, but also a case in which a third component is interposed between these components.

Hereinafter, a preferred example of a gate shift register according to the present invention and a flat panel display using the same will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a flat panel display having a gate shift register according to the present invention. 2 is a configuration diagram of first and second gate shift registers. 3A and 3B are diagrams for explaining the operations of the first and second gate shift registers according to the forward shift mode and the reverse shift mode.

Referring to FIG. 1 , a flat panel display device according to the present invention includes a display panel 2 , gate drivers 4a and 4b , a data driver 6 , and a timing controller 8 .

The display panel 2 includes a plurality of gate lines GL and a plurality of data lines DL that intersect each other, and a plurality of pixels P are provided in the intersection regions of the GL and DL. Each pixel P displays an image according to an image signal (data voltage) supplied from the data line DL in response to the scan pulse SCAN supplied from the gate line GL.

The gate drivers 4a and 4b are gate in panel (GIP) type gate drivers and are formed in a non-display area of the display panel 2 . The gate drivers 4a and 4b may be provided on one side of the display panel 2 or respectively provided on both sides of the display panel 2 to drive the plurality of gate lines GL.

Preferably, the gate drivers 4a and 4b are provided on both sides of the display panel 2 , respectively. That is, the gate drivers 4a and 4b are built in the non-display area of one side of the display panel 2 and supply scan pulses to the odd-numbered gate lines GL among the plurality of gate lines GL. It may be configured to include a 40a and a second gate shift register 40b that supplies a scan pulse to an even-numbered gate line GL among the plurality of gate lines GL. The present invention has the effect of facilitating narrow bezel design by reducing the area of the non-display area.

As shown in FIG. 2 , the first and second gate shift resistors 40a and 40b are respectively disposed on both sides of the plurality of gate lines GL and are connected to the plurality of gate lines GL. The first and second gate shift registers 40a and 40b are configured to enable a bidirectional shift operation. That is, the first and second gate shift registers 40a and 40b sequentially output scan pulses in the forward shift mode and reversely output the scan pulses in the reverse shift mode.

Referring to FIG. 3A , in the forward shift mode, the second gate shift register 40b responds to a K-th scan pulse applied by the first gate shift register to a K (K is an odd number)-th gate line, The +1th scan pulse is applied to the K+1th gate line, and the first gate shift register 40a applies the K+2th scan pulse to the K+2th gate line in response to the K+1th scan pulse. accredit to

Referring to FIG. 3B , in the reverse shift mode, the first gate shift register 40a responds to the J-th scan pulse applied by the second gate shift register 40b to the J (J is an even number)-th gate line. Thus, the J-1 th scan pulse is applied to the J-1 th gate line, and the second gate shift register 40b responds to the J-1 th scan pulse to apply the J-2 th scan pulse to J-2 is applied to the second gate line.

According to the present invention, the number of clock signal supply lines is halved by outputting its own scan pulse in response to a scan pulse output from the gate shift register disposed on the other side of the gate shift register disposed on one side of the gate line GL. can be reduced Therefore, according to the present invention, the number of wirings connected to the gate shift resistor can be reduced and narrow bezel design is facilitated.

Meanwhile, the first gate shift register 40a includes a plurality of subordinately connected left stages LST. The plurality of left stages LST are selectively connected to clock signal supply lines to which first and second clock signals CLK1 and CLK2 are supplied, and sequentially apply scan pulses SCAN to odd-numbered gate lines GL. print out The second gate shift register 40b includes a plurality of cascadingly connected right stages RST. The plurality of right stages RST are selectively connected to a clock signal supply line to which the third and fourth clock signals CLK3 and CLK4 are supplied, and sequentially apply the scan pulse SCAN to the even-numbered gate line GL. print out

Each of the left stages LST includes first to fourth input terminals IN1 to IN4 and an output terminal OUT. A selected one of the supply lines of the first and second clock signals CLK1 and CLK2 is connected to the first input terminal IN1 , and the other one is connected to the second input terminal IN2 . A supply line of a forward carry signal is connected to the third input terminal IN3 , and a supply line of a reverse carry signal is connected to the fourth input terminal IN4 .

The forward carry signal may be a scan pulse applied to the n−1 th gate line GL from the right stage RST. The reverse carry signal may be a scan pulse applied to the n+1-th gate line GL from the right stage RST. However, in the forward shift mode, the forward start signal VST is applied to the third input terminal IN3 of the first left stage LST. In the reverse shift mode, a reverse start signal is applied to the fourth input terminal IN4 of the last left stage LST.

Each of the right stages RST includes first to fourth input terminals IN1 to IN4 and an output terminal OUT. A selected one of the supply lines of the third and fourth clock signals CLK3 and CLK4 is connected to the first input terminal IN1 , and the other one is connected to the second input terminal IN2 . A supply line of a forward carry signal is connected to the third input terminal IN3 , and a supply line of a reverse carry signal is connected to the fourth input terminal IN4 .

The forward carry signal may be a scan pulse applied from the left stage LST to the n-1 th gate line GL. The reverse carry signal may be a scan pulse applied to the n+1-th gate line GL from the left stage RST.

Meanwhile, the first to fourth clock signals CLK1 to CLK4 are sequentially delayed and repeatedly output. As shown in FIG. 4 , the first to fourth clock signals CLK1 to CLK4 according to the embodiment include a first clock signal CLK1 , a third clock signal CLK3 , a second clock signal CLK2 , The fourth clock signal CLK4 is output in the order.

FIG. 5 is a configuration circuit diagram of an arbitrary stage (ST: LST or RST) shown in FIG. 2 .

Referring to FIG. 5 , the stage ST of the present invention includes a scan direction control unit 100 , a node control unit 200 , and an output unit 300 . This stage ST is configured to include 10 transistors and 2 capacitors. The present invention can facilitate narrow bezel design by reducing the circuit configuration of each stage and the number of signal lines connected to each stage compared to the prior art.

The scan direction control unit 100 serves to control the scan direction by outputting a pre-charge voltage in response to a forward carry signal or a reverse carry signal. To this end, the scan direction control unit 100 includes first and second transistors T1 and T2.

The first transistor T1 includes a third input terminal IN3, that is, a gate electrode and a first electrode connected to a supply line of the forward carry signal, and a second electrode connected to the first node. In the forward shift mode, the first transistor T1 supplies a precharge voltage to the first node Q in response to a forward carry signal.

The second transistor T2 includes a fourth input terminal IN4, that is, a gate electrode and a first electrode connected to a supply line of the reverse carry signal, and a second electrode connected to the first node. including transistors. In the reverse shift mode, the second transistor T2 supplies a pre-charge voltage to the first node Q in response to the reverse carry signal.

The node control unit 200 controls the voltages of the first node Q and the second node QB in response to the pre-charge voltage and the reset signal provided from the scan direction control unit 100 . To this end, the node controller 200 includes first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

The third transistor T3 includes a gate electrode connected to the first node Q, a first electrode connected to the second node QB, and a second electrode connected to a gate-off voltage supply line. . The third transistor T3 discharges the second node QB to the gate-off voltage VGL while the first node Q is charged.

The fourth transistor T4 includes a second input terminal IN2, that is, a gate electrode and a first electrode connected to the supply line of the reset signal, and a second electrode connected to the second node QB. . The fourth transistor T4 supplies a reset signal to the second node QB. For reference, the reset signal may be any one selected from the first and second clock signals CLK1 and CLK2. Also, the reset signal may be a scan pulse output from the next stage.

The fifth transistor T5 includes a gate electrode connected to the second node QB, a first electrode connected to the first node Q, and a second electrode connected to the gate-off voltage supply line. . The fifth transistor T5 discharges the first node Q to the gate-off voltage VGL while the second node QB is charged.

The sixth transistor T6 includes a gate electrode connected to a gate-on voltage supply line, a first electrode connected to the first node Q, and a second electrode connected to the output unit 300 . The sixth transistor T6 supplies the pre-charge voltage charged in the first node Q to the boost node BST of the output unit 300 . In particular, when the voltage of the boost node BST becomes higher than the gate-on voltage VGH during the period in which the clock signal is supplied to the first electrode of the pull-up transistor PU of the output unit 300 , the sixth transistor T6 is , is turned off to prevent the voltage charged to the boost node BST from being supplied to the first node Q. The present invention can prevent a plurality of transistors connected to the first node Q from being damaged.

The first capacitor C1 is disposed between the first electrode of the sixth transistor T1 and the gate-off voltage supply line. The first capacitor C1 maintains the voltage charged in the first node Q for a specific period.

The second capacitor C2 is disposed between the second node QB and the gate-off voltage supply line. The second capacitor C2 maintains the voltage charged in the second node QB for a specific period.

Meanwhile, the node controller 200 may further include an afterimage removal unit that removes an afterimage that may be generated on the screen when the display device is abnormally powered off. When the display device is abnormally powered off, the afterimage removal unit outputs the gate-on voltage VGH to the output terminal in response to the abnormal power-off signal APO provided from the outside. To this end, the afterimage removal unit includes seventh and eighth transistors T7 and T8.

The seventh transistor T7 has a gate electrode and a first electrode connected to a supply line of an abnormal power-off signal, and is connected to the output terminal OUT. The seventh transistor T7 outputs the abnormal power-off signal APO to the output terminal OUT in response to the abnormal power-off signal APO in the gate-on voltage VGH state.

The eighth transistor T8 includes a gate electrode connected to the supply line of the abnormal power-off signal, a first electrode connected to the second node QB, and a second electrode connected to the gate-off voltage supply line. include The eighth transistor T8 discharges the second node QB to the gate-off voltage VGL in response to the abnormal power-off signal APO.

The output unit 300 includes a pull-up transistor PU and a pull-down transistor PD.

The pull-up transistor PU has a gate electrode connected to the boost node BST, a first input terminal IN1, that is, a first electrode connected to a supply line of a clock signal, and a second electrode connected to an output terminal. include

The pull-down transistor PD includes a gate electrode connected to the second node QB, a first electrode connected to the output terminal OUT, and a second electrode connected to the gate-off voltage supply line.

6A to 6D are diagrams for explaining the driving method of the stage ST shown in FIG. 5 in stages. Hereinafter, an operation of each stage ST in the forward shift mode will be described with reference to FIGS. 6A to 6D .

First, referring to FIG. 6A , a forward carry signal is input through the third input terminal IN3 in the first period P1 . Then, the forward carry signal is supplied to the first node Q as a pre-charge voltage through the first transistor T1. Accordingly, the third transistor T3 connected to the first node Q is turned on, and the second node QB is discharged to the gate-off voltage VGL. Accordingly, the fifth transistor T5 and the pull-down transistor PD connected to the second node Q are turned off. Meanwhile, the pre-charge voltage supplied to the first node Q is supplied to the boost node BST through the sixth transistor T6.

Subsequently, referring to FIG. 6B , in the second period P2 , a clock signal, for example, the second clock signal CLK2 is input to the gate-on voltage VGH through the first input terminal IN1 . Then, the voltage of the first node Q is bootstrapped by the parasitic capacitance of the pull-up transistor PU and rises to a level higher than the pre-charge voltage. Accordingly, the pull-up transistor PU is completely turned on, and the pull-up transistor PU supplies the second clock signal CLK2 as a scan pulse to the output terminal OUT. At this time, the sixth transistor T6 is turned off as the boost node BST rises to a level higher than the pre-charge voltage, and thus the voltage raised from the boost node BST is not supplied to the first node Q. does not

Subsequently, referring to FIG. 6C , in the third period P3 , the second clock signal CLK2 input through the first input terminal IN1 drops to the gate-off voltage VGL, and thus the output terminal OUT The scan pulse supplied to the voltage falls to the gate-off voltage VGL. At this time, the voltage of the first node Q continues to maintain the pre-charge voltage by the first capacitor C1.

Subsequently, referring to FIG. 6D , in the fourth period P4 , a reset signal, for example, the first clock signal CLK1 , is input to the gate-on voltage VGH through the second input terminal IN2 . Then, a reset signal is applied to the second node QB through the fourth transistor T4 to charge the second node QB. Accordingly, the fifth transistor T5 connected to the second node QB is turned on, the first node Q is discharged to the gate-off voltage VGL, and the pull-up transistor PU is turned off. Meanwhile, as the second node QB is charged, the pull-down transistor PD is turned on, and the pull-down transistor PD supplies the gate-off voltage VGL to the output terminal OUT. The pull-down transistor PD is turned on until the forward carry signal is input to the third input terminal IN3 in the next frame period to supply the gate-off voltage VGL to the output terminal OUT. Accordingly, the operation of the corresponding stage ST is completed.

Meanwhile, in the reverse shift mode, the operation of each stage ST is mostly the same as in the forward shift mode, except that the reverse carry signal is input through the fourth input terminal IN4 in the first period P1 .

On the other hand, as described above, the stage ST of the present invention is provided with an afterimage removal unit that removes an afterimage that may be generated on the screen when the display device is abnormally powered off. same as

Referring to FIG. 7 , when the display device is abnormally powered off, an abnormal power off signal APO is generated from the outside and is simultaneously supplied to all stages ST.

When the abnormal power-off signal APO is supplied, the seventh and eighth transistors T7 and T8 are turned on. Then, the seventh transistor T7 supplies the abnormal power-off signal APO of the gate-on voltage VGH state to the output terminal OUT. And the eighth transistor T8 turns off the fifth transistor T5 and the pull-down transistor PD by discharging the second node QB to the gate-off voltage VGL. The present invention removes an afterimage that may be temporarily generated by allowing all stages to output the gate-on voltage VGH regardless of the current operating state of each stage when the power of the display device is abnormally turned off.

8A and 8B are layouts comparing the gate shift register of the prior art and the present invention.

The bidirectional gate shift register of the prior art requires at least 7 signal lines for driving each of the plurality of stages, and at least 16 transistors constituting each stage. Therefore, the gate shift resistor according to the prior art is designed to have a width of 0.7 mm or more, as shown in FIG. 8A.

On the other hand, the gate shift register of the present invention has 5 signal wirings for driving each of the plurality of stages (2 clock signal supply lines, 1 abnormal power-off signal supply line, and 2 gate-on voltage and gate-off voltage supply lines) ), and 10 and 2 transistors and capacitors constituting each stage are required, respectively. Therefore, it can be seen that the gate shift resistor according to the present invention can be designed to have a width of 0.4 mm as shown in FIG. 8B, and can be reduced by at least 0.3 mm compared to the prior art.

As described above, the present invention has the effect that the narrow bezel design can be facilitated by simplifying the circuit configuration of each of a plurality of stages and reducing the number of wirings.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible within the scope of the present invention. It will be clear to those who have the knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

40a: first gate shift register 40b: second gate shift register
LST: left stage RST: right stage

Claims (7)

a plurality of stages for sequentially outputting scan pulses in a forward shift mode and outputting the scan pulses in reverse order in a reverse shift mode;
Each of the plurality of stages includes a scan direction control unit for controlling a scan direction by outputting a precharge voltage in response to a forward carry signal or a reverse carry signal, and voltages of the first and second nodes in response to the precharge voltage and the reset signal. a node controller to control, and an output unit for outputting the scan pulses according to voltage levels of the first and second nodes;
The node controller
a first transistor comprising a gate electrode connected to the first node, a first electrode connected to a second node, and a second electrode connected to a gate-off voltage supply line;
a second transistor comprising a gate electrode and a first electrode connected to a supply line of a reset signal, and a second electrode connected to the second node;
a third transistor including a gate electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to a gate-off voltage supply line;
a fourth transistor including a gate electrode connected to a gate-on voltage supply line, a first electrode connected to the first node, and a second electrode connected to the output unit;
a first capacitor disposed between the first electrode of the fourth transistor and the gate-off voltage supply line; and
and a second capacitor disposed between the second node and the gate-off voltage supply line. The method of claim 1,
The scan direction control unit
a fifth transistor comprising a gate electrode and a first electrode connected to a supply line of the forward carry signal, and a second electrode connected to the first node; and
and a sixth transistor comprising a gate electrode and a first electrode coupled to the supply line of the reverse carry signal, and a second electrode coupled to the first node. The method of claim 1,
the output unit
a pull-up transistor comprising a gate electrode connected to a second electrode of the fourth transistor, a first electrode connected to a supply line of a clock signal, and a second electrode connected to an output terminal; and
and a pull-down transistor comprising a gate electrode coupled to the second node, a first electrode coupled to the output terminal, and a second electrode coupled to the gate off voltage supply line. 4. The method of claim 3,
The node controller
a seventh transistor including a gate electrode and a first electrode connected to a supply line of an abnormal power-off signal, and a second electrode connected to the output terminal; and
and an eighth transistor comprising a gate electrode connected to the supply line of the abnormal power-off signal, a first electrode connected to the second node, and a second electrode connected to the gate-off voltage supply line. shift register. a display panel having a plurality of gate lines;
a first gate shift register embedded in a non-display area of one side of the display panel to supply a scan pulse to an odd-numbered gate line among the plurality of gate lines; and
a second gate shift register embedded in a non-display area of the other side of the display panel to supply the scan pulse to an even-numbered gate line among the plurality of gate lines;
5. A flat panel display device, wherein each of the first and second gate shift registers is constituted by the gate shift register according to any one of claims 1 to 4. 6. The method of claim 5,
In the forward shift mode,
The second gate shift register applies a K+1-th scan pulse to the K+1-th gate line in response to the K-th scan pulse applied by the first gate shift register to the K (K is an odd number)-th gate line, ,
and the first gate shift register applies a K+2 th scan pulse to a K+2 th gate line in response to the K+1 th scan pulse. 6. The method of claim 5,
In the reverse shift mode,
The first gate shift register applies a J-1 th scan pulse to the J-1 th gate line in response to the J th scan pulse applied to the J (J is an even number) th gate line by the second gate shift register, ,
and the second gate shift register applies a J-2 th scan pulse to a J-2 th gate line in response to the J-1 th scan pulse.

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