CN112951146B

CN112951146B - Shift register, driving method, scanning driving circuit, display panel and device

Info

Publication number: CN112951146B
Application number: CN202110448731.2A
Authority: CN
Inventors: 李东华; 魏晓丽; 伍黄尧
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2021-04-25
Filing date: 2021-04-25
Publication date: 2024-03-15
Anticipated expiration: 2041-04-25
Also published as: CN112951146A

Abstract

The embodiment of the invention discloses a shift register, a driving method, a scanning driving circuit, a display panel and a device, wherein the shift register comprises a first node control module, a second node control module, an output module, a node mutual control module and a pull-down module; the first node control module is respectively and electrically connected with the scanning control end and the signal input end, and is also electrically connected with the output module and the first node; the second node control module is respectively and electrically connected with the first reference signal end, the first clock signal end and the scanning control end, and is also electrically connected with the output module and the second node; the output module is also respectively and electrically connected with the second clock signal end, the second reference signal end and the scanning signal output end; the node mutual control module is electrically connected with the first node, the second node and the second reference signal end respectively; the pull-down module is electrically connected with the pull-down control end, the pull-down signal end and the second node respectively. The technical scheme of the embodiment of the invention can improve the driving capability of the shift register and ensure normal display.

Description

Shift register, driving method, scanning driving circuit, display panel and device

Technical Field

The embodiment of the invention relates to a display technology, in particular to a shift register, a driving method, a scanning driving circuit, a display panel and a device.

Background

With the continuous development of display technology, the application of display panels is also becoming more and more widespread, for example, the display panels are applied to products such as mobile phones, computers, tablet computers, electronic books, information inquiry machines, and the like, and in addition, the display panels can be applied to instrument displays (for example, vehicle-mounted displays), control panels of smart home, and the like.

The conventional display panel scans pixels of each row line by a scanning circuit, thereby displaying a picture. The scanning circuit comprises a plurality of cascaded shift registers, and the shift registers realize the progressive scanning function through the circuit structures of a plurality of thin film transistors and capacitors. However, during the scan driving process, the on state of the thin film transistor may be abnormal due to an excessively high or low temperature, or due to aging of the device, etc., which affects the output signal of the shift register, resulting in abnormal display.

Disclosure of Invention

The embodiment of the invention provides a shift register, a driving method, a scanning driving circuit, a display panel and a device, which are used for improving the driving capability of the shift register and ensuring normal display.

In a first aspect, an embodiment of the present invention provides a shift register, including: the system comprises a first node control module, a second node control module, an output module, a node mutual control module, a pull-down module, a scanning control end, a signal input end, a first clock signal end, a second clock signal end, a first reference signal end, a second reference signal end, a scanning signal output end, a pull-down control end and a pull-down signal end;

the first node control module is respectively and electrically connected with the scanning control end and the signal input end; the first node control module is also electrically connected with the output module and is connected with the first node; in the charging stage, the first node control module is used for charging the first node under the control of a scanning control signal of the scanning control end and an input signal of the signal input end;

the second node control module is electrically connected with the first reference signal end, the first clock signal end and the scanning control end respectively; the second node control module is also electrically connected with the output module and is connected with a second node; in the reset stage, the second node control module is used for transmitting a first reference potential of the first reference signal end to the second node under the control of the scanning control signal and a first clock signal of the first clock signal end;

The output module is also respectively and electrically connected with the second clock signal end, the second reference signal end and the scanning signal output end; in the charging stage, the output module is used for outputting a second clock signal of the second clock signal end to the scanning signal output end under the control of the potential of the first node; in the reset stage, the output module is used for outputting a second reference signal of the second reference signal end to the scanning signal output end under the control of the potential of the second node;

the node mutual control module is electrically connected with the first node, the second node and the second reference signal end respectively; in the charging stage, the node mutual control module is used for controlling the second reference potential of the second reference signal end to be transmitted to the second node according to the potential of the first node; in the resetting stage, the node mutual control module is used for controlling the second reference potential of the second reference signal end to be transmitted to the first node according to the potential of the second node;

the pull-down module is electrically connected with the pull-down control end, the pull-down signal end and the second node respectively; in the charging stage, the pull-down module is used for transmitting a non-enabling level of the pull-down signal to the second node under the control of the pull-down control signal.

In a second aspect, an embodiment of the present invention further provides a driving method of a shift register, which is performed by using the shift register provided in the previous aspect, where the driving method includes:

In the charging stage, the scanning control end provides the enabling level of the scanning control signal, the signal input end provides the enabling level of the input signal, and the first node control module is controlled to charge the first node; the node mutual control module controls the second reference potential to be transmitted to the second node according to the potential of the first node; the pull-down control terminal provides an enabling level of a pull-down control signal, the pull-down signal terminal provides a non-enabling level of the pull-down signal, and the pull-down module is controlled to pull down the potential of the second node; the output module outputs a second clock signal of the second clock signal end to the scanning signal output end under the control of the potential of the first node;

in the signal output stage, the second clock signal end provides the enabling level of the second clock signal, and the output module outputs the enabling level of the second clock signal under the control of the potential of the first node;

in a reset stage, the scanning control end provides an enabling level of a scanning control signal, the first clock signal end provides an enabling level of a first clock signal, and the second node control module is controlled to transmit a first reference potential of the first reference signal end to the second node; the node mutual control module controls the second reference potential of the second reference signal end to be transmitted to the first node according to the potential of the second node; the output module outputs a second reference signal of the second reference signal end to the scanning signal output end under the control of the potential of the second node.

In a third aspect, an embodiment of the present invention further provides a scan driving circuit, including: a plurality of shift registers provided in the first aspect; a plurality of shift registers are arranged in cascade.

In a fourth aspect, an embodiment of the present invention further provides a display panel, including: the third aspect provides the scan driving circuit.

In a fifth aspect, an embodiment of the present invention further provides a display apparatus, including: the display panel provided in the fourth aspect.

According to the shift register provided by the embodiment of the invention, the pull-down module is additionally arranged, and the pull-down module transmits the non-enabling level of the pull-down signal to the second node under the control of the pull-down control signal in the charging stage, so that the node mutual control module and the pull-down module can be utilized to perform double control on the potential of the second node, the potential of the second node is ensured to be the non-enabling level in the charging stage, the second reference potential is further ensured not to be transmitted to the first node, the influence of the second reference potential on the potential of the first node caused by transistor leakage is avoided, the influence on the output signal of the scanning signal output end is further avoided, the driving capability of the shift register is improved, and normal display is ensured.

Drawings

FIG. 1 is a schematic diagram of a shift register according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating another embodiment of a shift register according to the present invention;

FIG. 5 is a timing diagram illustrating another embodiment of a shift register according to the present invention;

FIG. 6 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another embodiment of a shift register according to the present invention;

FIG. 8 is a timing diagram of driving a shift register during forward scanning according to an embodiment of the present invention;

FIG. 9 is a schematic diagram showing a specific structure of another shift register according to an embodiment of the present invention;

FIG. 10 is a schematic flow chart of a driving method of a shift register according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention, referring to fig. 1, the shift register includes: the first node control module 10, the second node control module 20, the output module 30, the node mutual control module 40, the pull-DOWN module 50, the scan control terminal (e.g., the forward scan control terminal U2D), the signal input terminal (e.g., the forward scan signal input terminal INF), the first clock signal terminal (e.g., the first forward scan clock signal terminal RSTF), the second clock signal terminal OUT, the first reference signal terminal VGH, the second reference signal terminal VGL, the scan signal output terminal GOUT, the pull-DOWN control terminal DC, and the pull-DOWN signal terminal DOWN.

The first node control module 10 is electrically connected with a scan control terminal (e.g. U2D) and a signal input terminal (e.g. INF), respectively; the first node control module 10 is further electrically connected to the first node N1 with the output module 30; in the charging phase, the first node control module 10 is configured to charge the first node N1 under the control of the scan control signal at the scan control terminal and the input signal at the signal input terminal. The second node control module 20 is electrically connected to the first reference signal terminal VGH, the first clock signal terminal (e.g. RSTF), and the scan control terminal (e.g. U2D), respectively; the second node control module 20 is further electrically connected to the second node N2 with the output module 30; in the reset phase, the second node control module 20 is configured to transmit the first reference potential of the first reference signal terminal VGH to the second node N2 under the control of the scan control signal and the first clock signal of the first clock signal terminal. The output module 30 is further electrically connected to the second clock signal terminal OUT, the second reference signal terminal VGL, and the scan signal output terminal GOUT, respectively; in the charging phase, the output module 30 is configured to output the second clock signal of the second clock signal terminal OUT to the scan signal output terminal GOUT under the control of the potential of the first node N1; in the reset phase, the output module 30 is configured to output the second reference signal of the second reference signal terminal VGL to the scan signal output terminal GOUT under the control of the potential of the second node N2. The node mutual control module 40 is electrically connected with the first node N1, the second node N2 and the second reference signal terminal VGL respectively; in the charging stage, the node inter-control module 40 is configured to control the second reference potential of the second reference signal terminal VGL to be transmitted to the second node N2 according to the potential of the first node N1; in the reset phase, the node mutual control module 40 is configured to control the second reference potential of the second reference signal terminal VGL to be transmitted to the first node N1 according to the potential of the second node N2. The pull-DOWN module 50 is electrically connected with the pull-DOWN control terminal DC, the pull-DOWN signal terminal DOWN, and the second node N2, respectively; during the charging phase, the pull-down module 50 is configured to transmit the disable level of the pull-down signal to the second node N2 under the control of the pull-down control signal.

Specifically, in the charging stage, the scan control terminal (e.g. U2D) provides the enable level of the scan control signal, the signal input terminal (e.g. INF) provides the enable level of the input signal, so as to control the first node control module 10 to charge the first node N1, so that the potential of the first node N1 is in the state of the enable level, and thus, the node inter-control module 40 can control the second reference potential of the second reference signal terminal VGL to be transmitted to the second node N2 according to the potential of the first node N1, and the potential of the second node N2 is in the state of the non-enable level, so that the second reference potential is not transmitted to the scan signal output terminal GOUT; the output module 30 can output the second clock signal of the second clock signal terminal OUT to the scan signal output terminal GOUT under the control of the potential of the first node N1, and can provide the enable level of the scan signal to the corresponding gate line when the second clock signal terminal OUT provides the enable level. In addition, the embodiment of the invention further adds the pull-DOWN module 50, in the charging stage, the pull-DOWN control terminal DC provides the enable level of the pull-DOWN control signal, and the pull-DOWN signal terminal DOWN provides the disable level of the pull-DOWN signal, so that the pull-DOWN module 50 can be controlled to pull DOWN the potential of the second node N2, so that the node mutual control module 40 and the pull-DOWN module 50 can be utilized to perform dual control on the potential of the second node N2, the potential of the second node N2 is ensured to be the disable level in the charging stage, further, the second reference potential in the charging stage is ensured not to be transmitted to the first node N1, the influence of the second reference potential on the potential of the first node N1 caused by transistor leakage is avoided, the influence on the output signal of the scanning signal output terminal GOUT is further avoided, the driving capability of the shift register is improved, and normal display is ensured.

In the reset phase, the scan control terminal (e.g. U2D) provides the enable level of the scan control signal, the first clock signal terminal (e.g. RSTF) provides the enable level of the first clock signal, the second node control module 20 is controlled to transmit the first reference potential of the first reference signal terminal VGH to the second node N2 so as to enable the potential of the second node N2 to be in the enable level state, so the node inter-control module 40 can control the second reference potential of the second reference signal terminal VGL to be transmitted to the first node N1 according to the potential of the second node N2, the potential of the first node N1 is in the non-enable level state, so that the second clock signal of the second clock signal terminal OUT is not transmitted to the scan signal output terminal GOUT, and the output module 30 can output the second reference signal of the second reference signal terminal VGL to the scan signal output terminal GOUT under the control of the potential of the second node N2 to realize the reset.

The thin film transistor in the shift register may be, for example, an N-type transistor, where the enable level of the output signal of each signal terminal is high and the disable level is low.

Fig. 2 is a schematic diagram of a specific structure of a shift register according to an embodiment of the present invention, referring to fig. 2, optionally, the scan control terminal includes a forward scan control terminal U2D, the signal input terminal includes a forward scan signal input terminal INF, and the first clock signal terminal includes a first forward scan clock signal terminal RSTF; the first node control module 10 includes a first transistor M1, a gate of the first transistor M1 is electrically connected to the forward scan signal input terminal INF, a first pole of the first transistor M1 is electrically connected to the forward scan control terminal U2D, and a second pole of the first transistor M1 is electrically connected to the first node N1; the pull-DOWN module 50 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the pull-DOWN control terminal DC, a first pole of the third transistor M3 is electrically connected to the pull-DOWN signal terminal DOWN, and a second pole of the third transistor M3 is electrically connected to the second node N2; the second node control module 20 includes a fifth transistor M5 and a seventh transistor M7, wherein the gate of the fifth transistor M5 is electrically connected to the forward scan control terminal U2D, the first pole of the fifth transistor M5 is electrically connected to the first forward scan clock signal terminal RSTF, the second pole of the fifth transistor M5 is electrically connected to the gate of the seventh transistor M7, the first pole of the seventh transistor M7 is electrically connected to the first reference signal terminal VGH, and the second pole of the seventh transistor M7 is electrically connected to the second node N2; the node mutual control module 40 includes an eighth transistor M8 and a ninth transistor M9, wherein a gate of the eighth transistor M8 is electrically connected to the second node N2, a first pole of the eighth transistor M8 is electrically connected to the second reference signal terminal VGL, a second pole of the eighth transistor M8 is electrically connected to the first node N1, a gate of the ninth transistor M9 is electrically connected to the first node N1, a first pole of the ninth transistor M9 is electrically connected to the second reference signal terminal VGL, and a second pole of the ninth transistor M9 is electrically connected to the second node N2; the output module 30 includes a tenth transistor M10, an eleventh transistor M11, a first capacitor C1, and a second capacitor C2; the gate of the tenth transistor M10 and the first end of the first capacitor C1 are electrically connected to the first node N1; a first pole of the tenth transistor M10 is electrically connected to the second clock signal terminal OUT; the second terminal of the tenth transistor M10 and the second terminal of the first capacitor C1 are electrically connected to the scanning signal output terminal GOUT; the gate of the eleventh transistor M11 and the first end of the second capacitor C2 are electrically connected to the second node N2; the first pole of the eleventh transistor M11 and the second end of the second capacitor C2 are electrically connected to the second reference signal terminal VGL; the second pole of the eleventh transistor M11 is electrically connected to the scanning signal output terminal GOUT; wherein the eighth transistor M8 is the same as the eleventh transistor M11 in channel type; the ninth transistor M9 is the same as the tenth transistor M10 in channel type.

Fig. 2 illustrates an example in which the thin film transistors in the shift register are all N-type transistors, and the structure is not limited. Fig. 3 is a driving timing chart of a shift register according to an embodiment of the present invention, and with reference to fig. 2 and 3, the shift register has the following working procedures:

in the charging stage T1, the forward scan signal input terminal INF inputs a high level, the first transistor M1 is turned on, and the forward scan control terminal U2D inputs a high level to charge the first node N1 and pull it up to a high level. Since the first node N1 is at a high level, the tenth transistor M10 is turned on, and the second clock signal of the second clock signal terminal OUT is transmitted to the scan signal output terminal GOUT (the second clock signal of the charging stage may be at a non-enable level). Meanwhile, since the first node N1 is at a high level, the ninth transistor M9 is turned on, so that the second reference potential of the second reference signal terminal VGL is transmitted to the second node N2, the potential of the second node N2 is reduced, and the eighth transistor M8 and the eleventh transistor M11 are turned off, the second reference potential is not transmitted to the scanning signal output terminal GOUT and the first node N1, and furthermore, since the pull-DOWN control terminal DC inputs a high level, the third transistor M3 is turned on, the pull-DOWN signal terminal DOWN inputs a low level to pull DOWN the potential of the second node N2, thereby further ensuring that the potential of the second node N2 is at a low level, ensuring that the second reference potential of the second reference signal terminal VGL is not transmitted to the first node N1, avoiding the situation that the tenth transistor M10 cannot be turned on due to the fact that the second reference potential pulls DOWN the potential of the first node N1 due to the leakage current of the eighth transistor M8, ensuring that the potential of the first node N1 satisfies the conduction condition of the tenth transistor M10, and improving the shift register.

In the signal output stage T2, since the first capacitor C1 stores the potential of the first node N1, the potential of the first node N1 is maintained at a high level, the tenth transistor M10 is in a conductive state, and in this stage, the second clock signal terminal OUT inputs a high level (enable level) so that the scan signal output terminal GOUT outputs a high level, and the shift register supplies a scan signal to a corresponding gate line.

In the reset stage T3, the positive scan control terminal U2D inputs a high level, the fifth transistor M5 is turned on, and the first positive scan clock signal terminal RSTF inputs a high level, so that the seventh transistor M7 is turned on, the first reference potential of the first reference signal terminal VGH is transmitted to the second node N2, and the potential of the second node N2 is pulled up. Since the second node N2 is at a high level, the eighth transistor M8 and the eleventh transistor M11 are turned on, the second reference signal of the second reference signal terminal VGL is transmitted to the first node N1, the potential of the first node N1 is pulled down, so that the tenth transistor M10 is turned off, the second clock signal of the second clock signal terminal OUT is not transmitted to the scan signal output terminal GOUT, and since the eleventh transistor M11 is turned on, the second reference signal of the second reference signal terminal VGL is transmitted to the scan signal output terminal GOUT, and the shift register resets the signal on the gate line.

As shown in fig. 3, the forward scanning signal input end INF is consistent with the signal output by the pull-DOWN control end DC, so in other embodiments, the forward scanning signal input end INF may be optionally multiplexed into the pull-DOWN control end DC, and in addition, the second reference signal end VGL may be multiplexed into the pull-DOWN signal end DOWN, so as to avoid increasing pins required by the driving chip and ensure the practicability of the existing driving chip.

Fig. 4 is a schematic diagram showing a driving timing diagram of another shift register according to an embodiment of the present invention, referring to fig. 4, optionally, a scan control terminal (e.g., a forward scan control terminal U2D) provides an enable level of a scan control signal in a charging stage T1 and a reset stage T3, and provides a scan control signal disable level in an intermittent stage T4; the signal input terminal (such as the forward scan signal input terminal INF) provides an enable level of the input signal in the charging phase T1 and provides a disable level of the input signal in the intermittent phase T4 and the reset phase T3; in the intermittent stage T4, the first node control module 10 is configured to be in an unbiased state under the control of the scan control signal and the input signal.

Specifically, the scan control terminals of the shift registers of the scan driving circuit are typically connected to the same scan control line, and the scan control line is used to transmit the enable level of the scan control signal to the scan control terminals of the shift registers in the charging stage and the reset stage of each shift register.

As shown in fig. 2, after the first node N1 of the shift register is charged, the first node control module 10 is in a negative bias state until the first node N1 of the shift register is charged next time. Taking the first node control module including the first transistor M1 as an example, in the period from the end of the charging period to the beginning of the next charging period, if the gate potential Vg of the first transistor M1 is low, and the source potential Vs of the first transistor M1 is high, the first transistor M1 will be in a negative bias state for a long period of time because Vg is less than Vs, and the performance of the first transistor M1 may be affected by the long period of time in the negative bias state, so that the threshold value of the first transistor M1 shifts, and the first transistor M1 cannot be controlled to meet the conduction condition that Vgs is greater than Vth in an accurate period of time when entering the charging period again, so that the first node control module 10 is turned on abnormally or even cannot be turned on in the charging period. Referring to fig. 2 and 4 in combination, the present embodiment sets the scan control terminal to provide the non-enable level of the scan control signal in the intermittent stage, so that the first node control module 10 is in the non-bias state in the intermittent stage, thereby avoiding the adverse effect caused by the long-term negative bias, and further enabling the shift register to output an accurate scan signal. Still taking the first node control module as an example, the first transistor M1 is included, and in the intermittent stage T4, the gate potential of the first transistor M1 is at a low level, and the source potential of the first transistor M1 is at a low level, so that the first node control module is in an unbiased state.

For example, as shown in fig. 4, the intermittent phase T4 may be located after the reset phase T3. In this way, in the whole scanning process, after the charging phase is finished, the first node control module 10 of any shift register is in a negative bias state and a non-bias state alternately until the next charging phase starts, so that the situation that the subsequent charging phase cannot be conducted normally due to long-term negative bias can be avoided.

With continued reference to fig. 4, further alternatively, the second clock signal terminal OUT is configured to provide a non-enable level of the second clock signal in the charging phase T1, the reset phase T3 and the intermittent phase T4, and provide an enable level of the second clock signal in the signal output phase T2; the scan control terminal (e.g., the forward scan control terminal U2D) is further configured to provide an enable level of the scan control signal in the signal output stage T2; the signal input terminal (e.g. the forward scan signal input terminal INF) is further configured to provide a disable level of the input signal during the signal output phase T2; the signal output stage T2 is located between the charging stage T1 and the reset stage T3.

In the charging phase T1, the first node control module 10 charges the first node N1, and after the charging phase is finished, the first node N1 is kept in the state of the enabling level for a period of time, so that the first node N1 has a relatively stable potential; at this time, the signal output stage T2 may be entered, and the second clock signal terminal OUT provides the enabling level of the second clock signal, and is output by the output module 30, so as to ensure that the enabling level of the scanning signal output by the output module 30 to the scanning signal output terminal GOUT is more stable. In addition, in the signal output stage T2, the scan control terminal (e.g., the forward scan control terminal U2D) provides the enable level of the scan control signal, so that the potentials at the two ends of the first node control module 10 are balanced, avoiding the first node control module 10 (e.g., the first transistor M1) from leaking to affect the potential of the first node N1, and ensuring the driving capability of the shift register.

In the driving sequence shown in fig. 4, the position of the intermittent stage in the driving period of the shift register is only schematic and not limited. Fig. 5 is a driving timing diagram of another shift register according to an embodiment of the present invention, and referring to fig. 5, optional intermittent phases include a first intermittent phase T41, a second intermittent phase T42, and a third intermittent phase T43; the first intermittent stage T41 is positioned between the charging stage T1 and the signal output stage T2; the second intermittent stage T42 is positioned between the signal output stage T2 and the reset stage T3; the third intermittent stage T43 is located after the reset stage T3 or the third intermittent stage T43 is located before the charging stage T1.

Fig. 5 illustrates an example in which the third intermittent stage T43 is located after the reset stage T3. As shown in fig. 5, in the driving period of the shift register, the positive scan control terminal U2D provides the non-enable level in the first intermittent stage T41, the second intermittent stage T42 and the third intermittent stage T43, so that the duration of the negative bias of the first node control module 10 can be further shortened, and the first node control module 10 is alternately in the negative bias state (such as the signal output stage T2 and the reset stage T3) for a shorter time and the non-bias state (such as the intermittent stages T41, T42 and T43) for a shorter time, so as to ensure that the first node control module 10 in the shift register can be normally turned on in the subsequent charging stage.

In summary, on the basis of setting the pull-down module 50 to pull down the potential of the second node N2, so as to ensure that the potential of the first node N1 is not affected by the second reference potential of the second reference signal terminal VGL, the output signal of the scan control terminal may be set to be a pulse signal, so that the first node control module 10 may be normally turned on in the charging stage, thereby ensuring the charging capability of the first node N1, further improving the driving capability of the shift register, and ensuring normal display.

It should be noted that, in the above embodiment, only the scan control terminal includes the forward scan control terminal U2D, the signal input terminal includes the forward scan signal input terminal INF, and the first clock signal terminal includes the first forward scan clock signal terminal RSTF as an example, so that the forward scan (from the first row to the nth row in turn, N is a positive integer greater than 1) can be implemented for the pixels of the display area, which is not limited. In other embodiments, referring to the schematic structural diagram of another shift register provided in the embodiment of the present invention shown in fig. 6, optionally, the scan control end includes a forward scan control end U2D and a reverse scan control end D2U; the signal input end comprises a forward scanning signal input end INF and a reverse scanning signal input end INB; the first clock signal terminal includes a first forward scan clock signal terminal RSTF and a first reverse scan clock signal terminal RSTB.

The forward scanning control end U2D is used for providing an enabling level of a forward scanning control signal in a charging stage and a resetting stage of forward scanning; the reverse scanning control end D2U is used for providing the enabling level of a reverse scanning control signal in the charging stage and the resetting stage of the reverse scanning; the forward scan signal input end INF is used for providing an enabling level of a forward input signal in a charging stage of forward scanning; the inverse scan signal input terminal INB is used for providing an enable level of an inverse input signal in a charging phase of inverse scan; the first forward scanning clock signal terminal RSTF is used for providing the enabling level of the first forward scanning clock signal in the reset phase of forward scanning; the first inverse scan clock signal terminal RSTB is used for providing an enable level of the first inverse scan clock signal in a reset phase of the inverse scan. In addition, the forward scan control terminal U2D may be further configured to provide an enable level of the forward scan control signal during a signal output phase of the forward scan, and the reverse scan control terminal D2U may be further configured to provide an enable level of the reverse scan control signal during a signal output phase of the reverse scan.

So configured, the display area can be scanned forward or backward (scanning from the nth row to the 1 st row in turn, N being a positive integer greater than 1) as needed. Specifically, during forward scanning, signals required by corresponding modules are provided through a forward scanning control terminal U2D, a forward scanning signal input terminal INF and a first forward scanning clock signal terminal RSTF; in the reverse scanning process, signals required by the corresponding modules are provided through the reverse scanning control terminal D2U, the reverse scanning signal input terminal INB and the first reverse scanning clock signal terminal RSTB.

Further, with continued reference to FIG. 6, the pull-down signal terminals may optionally include a forward pull-down signal terminal and a reverse pull-down signal terminal; the pull-down control end comprises a forward pull-down control end and a reverse pull-down control end; the forward scanning signal input end INF is multiplexed into a forward pull-down control end, and the reverse scanning signal input end INB is multiplexed into a reverse pull-down control end; the forward scanning control end U2D is multiplexed into a reverse pull-down signal end, and the reverse scanning control end D2U is multiplexed into a forward pull-down signal end; during the charging phase of the forward scan, the pull-down module 50 is configured to transmit the disable level of the forward pull-down signal terminal (i.e. D2U) to the second node N2 under the control of the forward pull-down control signal of the forward pull-down control terminal (i.e. INF); during the charging phase of the reverse scan, the pull-down module 50 is configured to transmit the disable level of the reverse pull-down signal terminal (i.e. U2D) to the second node N2 under the control of the reverse pull-down control signal of the reverse pull-down control terminal (i.e. INB).

Specifically, during the charging phase of the forward scan, the enable level provided by the forward scan signal input terminal INF controls the first node control module 10 to be turned on, so that the forward scan signal input terminal INF can be multiplexed into the forward pull-down control terminal to control the pull-down module 50 to be turned on during the charging phase, so that the non-enable level of the forward pull-down signal terminal is transmitted to the second node N2, and the potential of the second node N2 is at the non-enable level. In addition, in the forward scanning phase, a signal opposite to the forward scanning control terminal U2D may be provided by the reverse scanning control terminal D2U, for example, in the charging phase of the forward scanning, the reverse scanning control terminal D2U provides a disable level, so that the reverse scanning control terminal D2U may be multiplexed into the forward pull-down signal terminal. Similarly, the reverse scan signal input terminal INB may be multiplexed as a reverse pull-down control terminal, and the forward scan control terminal U2D may be multiplexed as a reverse pull-down signal terminal. Therefore, the pins required by the driving chip can be prevented from being increased, and the practicability of the existing driving chip is ensured.

Accordingly, fig. 7 is a schematic diagram of a specific structure of another shift register according to an embodiment of the present invention, referring to fig. 7, optionally, the first node control module 10 includes a first transistor M1 and a second transistor M2; the pull-down module 50 includes a third transistor M3 and a fourth transistor M4; the gate of the first transistor M1 and the gate of the third transistor M3 are electrically connected to the forward scan signal input terminal INF; the grid electrode of the second transistor M2 and the grid electrode of the fourth transistor M4 are electrically connected with the reverse scanning signal input end INB; the first pole of the first transistor M1 and the first pole of the fourth transistor M4 are electrically connected to the forward scan control terminal U2D; the first electrode of the second transistor M2 and the first electrode of the third transistor M3 are electrically connected with the reverse scanning control end D2U; the second pole of the first transistor M1 and the second pole of the second transistor M2 are both electrically connected to the first node N1; the second pole of the third transistor M3 and the second pole of the fourth transistor M4 are both electrically connected to the second node N2; the channel type of the first transistor M1 is the same as that of the third transistor M3, and the channel type of the second transistor M2 is the same as that of the fourth transistor M4.

With continued reference to fig. 7, the second node control module 20 may optionally include a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7; the grid electrode of the fifth transistor M5 is electrically connected with the forward scanning control end U2D, and the first electrode of the fifth transistor M5 is electrically connected with the first forward scanning clock signal end RSTF; the gate of the sixth transistor M6 is electrically connected to the inverse scan control terminal D2U, and the first pole of the sixth transistor M6 is electrically connected to the first inverse scan clock signal terminal RSTB; the second pole of the fifth transistor M5 and the second pole of the sixth transistor M6 are both electrically connected to the gate of the seventh transistor M7; the first pole of the seventh transistor M7 is electrically connected to the first reference signal terminal VGH, and the second pole of the seventh transistor M7 is electrically connected to the second node N2.

Fig. 7 illustrates an example in which the thin film transistors in the shift register are all N-type transistors. Fig. 8 is a driving timing chart of the shift register during forward scanning according to the embodiment of the present invention, and with reference to fig. 7 and 8, the shift register works as follows:

in the charging period T1, the forward scan signal input terminal INF inputs a high level, and the first transistor M1 and the third transistor M3 are turned on, so that the high level input by the forward scan control terminal U2D charges the first node N1 through the first transistor M1, thereby raising the potential of the first node N1, and the low level input by the reverse scan control terminal D2U is transmitted to the second node N2 through the third transistor M3, thereby lowering the potential of the second node N2. Further, since the potential of the first node N1 increases, the ninth transistor M9 and the tenth transistor M10 are turned on, and thus, the second clock signal of the second clock signal terminal OUT is transmitted to the scan signal output terminal GOUT through the tenth transistor M10, and at this time, the second clock signal may be, for example, low level; the low level input by the second reference signal terminal VGL is transmitted to the second node N2 through the ninth transistor M9, and the potential of the second node N2 is also lowered, so that the potential of the second node N2 is controlled in a dual manner through the node mutual control module 40 and the pull-down module 50, the potential of the second node N2 is ensured to be low in the charging stage, and therefore the second reference signal of the second reference signal terminal VGL is ensured not to affect the potential of the first node N1, and further the driving capability of the shift register is ensured.

In the first intermittent stage T41, the forward scan signal input terminal INF inputs a low level, and the forward scan control terminal U2D inputs a low level, so that the first transistor M1 is in an unbiased state.

In the signal output stage T2, the potential of the first node N1 is at a high level, so that the tenth transistor M10 is turned on, the high level signal input from the second clock signal terminal OUT is transmitted to the scan signal output terminal GOUT through the tenth transistor M10, and the shift register supplies the scan signal to the corresponding gate line. At this stage, since the forward scan signal input terminal INF is at a low level and the forward scan control terminal U2D is at a high level, the first transistor M1 is in a negative bias state.

In the second intermittent stage T42, the forward scan signal input terminal INF inputs a low level, and the forward scan control terminal U2D inputs a low level, so that the first transistor M1 is in an unbiased state.

In the reset stage T3, the positive scan control terminal U2D inputs a high level, the fifth transistor M5 is turned on, and the first positive scan clock signal terminal RSTF inputs a high level, so that the seventh transistor M7 is turned on, the high level input by the first reference signal terminal VGH is transmitted to the second node N2, and the potential of the second node N2 is pulled up. Since the second node N2 is at a high level, the eighth transistor M8 and the eleventh transistor M11 are turned on, the low level of the second reference signal terminal VGL is transmitted to the first node N1, the potential of the first node N1 is pulled down, the tenth transistor M10 is turned off, the second clock signal of the second clock signal terminal OUT is not transmitted to the scan signal output terminal GOUT, and since the eleventh transistor M11 is turned on, the low level signal of the second reference signal terminal VGL is transmitted to the scan signal output terminal GOUT, and the signal on the gate line is reset. At this stage, since the forward scan signal input terminal INF is at a low level and the forward scan control terminal U2D is at a high level, the first transistor M1 is in a negative bias state.

In the third intermittent stage T43, the forward scan signal input terminal INF inputs a low level, and the forward scan control terminal U2D inputs a low level, so that the first transistor M1 is in an unbiased state.

Therefore, after the charging stage T1 is finished, the first transistor M1 is alternately in the non-biased state and the negative biased state, and in the working process of the lower shift register, the first transistor M1 of the shift register is also alternately in the non-biased state and the negative biased state until the shift register enters the next charging stage, so that the situation that the first transistor M1 is in the negative biased state for a long time to cause abnormal conduction can be avoided, the charging capability of the first node N1 is ensured, and the driving capability of the shift register is further ensured.

On the basis of any one of the above embodiments, fig. 9 is a schematic diagram of a specific structure of another shift register provided in the embodiment of the present invention, referring to fig. 9, optionally, the first node includes a first node N1a and a first second node N1b; the first node control module 10 is electrically connected with the first node N1a, and the output module 30 is electrically connected with the first node B N1b; the shift register further includes a voltage stabilizing protection module 60; the voltage stabilizing protection module 60 is electrically connected with the first reference signal end VGH, the first node a N1a and the first node b N1b respectively; the voltage stabilizing protection module 60 is configured to maintain the potential of the first node N1a to be less than or equal to a preset voltage value under the control of the first reference signal terminal VGH and the first node N1 b.

Since the output module 30 is electrically connected to the scan signal output terminal GOUT, and the scan signal output terminal GOUT is electrically connected to the gate line in the display area, if the potential of the scan signal output terminal GOUT suddenly increases due to static electricity or other reasons, the potential is conducted to the first node through the first capacitor, and further flows back to the driving chip through the first node control module 10, so that the driving chip is damaged. In the embodiment of the invention, the voltage stabilizing protection module 60 is arranged between the first node N1a and the first node N1b, so that the voltage stabilizing protection module 60 is electrically connected with the first reference signal end VGH, and when the potential of the first node N1b suddenly rises due to static electricity and the like, the voltage stabilizing protection module 60 can be controlled to be closed, so that the potential of the first node N1a is smaller than or equal to a preset voltage value, and the high potential is prevented from flowing back to the driving chip. In addition, when the potential of the scan signal output terminal GOUT is not abnormal, the voltage stabilizing protection module 60 can be continuously turned on under the control of the first reference signal terminal VGH, so that the normal operation of the shift register is not affected.

For example, referring to fig. 9, the voltage stabilizing protection module 60 includes a twelfth transistor M12, the gate of the twelfth transistor M12 is electrically connected to the first reference signal terminal VGH, the source of the twelfth transistor M12 is electrically connected to the first node b 1b, and the drain of the twelfth transistor M12 is electrically connected to the first node a 1 a.

With continued reference to fig. 9, the shift register may optionally further include a first node potential adjustment module 70, a second node potential adjustment module 80, and a start control terminal GAS; the starting control end GAS is used for providing an enabling level of a starting control signal in a starting stage; the first node potential adjusting module 70 is electrically connected with the start control terminal GAS, the first reference signal terminal VGH and the scanning signal output terminal GOUT, respectively; in the start-up phase, the first node potential adjustment module 70 is configured to transmit a first reference potential to the scan signal output terminal GOUT under the control of a start-up control signal; the second node potential adjusting module 80 is electrically connected with the start control terminal GAS, the second reference signal terminal VGL and the second node N2, respectively; in the start-up phase, the second node potential adjustment module 80 is configured to transmit the second reference potential to the second node N2 under the control of the start-up control signal; wherein the start-up phase is located before the charge phase and the reset phase.

Specifically, in the start-up phase, the scan signal output terminals GOUT of all shift registers are required to output high level signals at the same time. To achieve the objective, the first node potential adjusting module 70 and the second node potential adjusting module 80 are provided, the first node potential adjusting module 70 is electrically connected to the start control terminal GAS, the first reference signal terminal VGH and the scan signal output terminal GOUT, the second node potential adjusting module 80 is electrically connected to the start control terminal GAS, the second reference signal terminal VGL and the second node N2, respectively, so that the start control terminal GAS provides the enable level of the start control signal during the start phase, the first node potential adjusting module 70 and the second node potential adjusting module 80 are turned on, the first reference potential is transmitted to the scan signal output terminal GOUT, the high level signal is simultaneously output to all gate lines, the second reference potential is transmitted to the second node N2, the potential of the second node N2 is pulled down, the eleventh transistor M11 is turned off, and the second reference potential is not transmitted to the scan signal output terminal GOUT.

For example, referring to fig. 9, the first node potential adjusting module 70 includes a thirteenth transistor M13, the second node potential adjusting module 80 includes a fourteenth transistor M14, the gate of the thirteenth transistor M13 and the gate of the fourteenth transistor M14 are electrically connected to the start control terminal GAS, the first pole of the thirteenth transistor M13 is electrically connected to the first reference signal terminal VGH, the second pole of the thirteenth transistor M13 is electrically connected to the scan signal output terminal GOUT, the first pole of the fourteenth transistor M14 is electrically connected to the second reference signal terminal VGL, and the second pole of the thirteenth transistor M13 is electrically connected to the second node N2.

Based on the same inventive concept, an embodiment of the present invention further provides a method for driving a shift register, which is performed by using the shift register provided in any one of the embodiments, and fig. 10 is a schematic flow chart of a method for driving a shift register provided in the embodiment of the present invention, and referring to fig. 10, the method for driving a shift register includes:

s101, in a charging stage, a scanning control end provides an enabling level of a scanning control signal, a signal input end provides an enabling level of an input signal, and a first node control module is controlled to charge a first node; the node mutual control module controls the second reference potential to be transmitted to the second node according to the potential of the first node; the pull-down control terminal provides an enabling level of a pull-down control signal, the pull-down signal terminal provides a non-enabling level of the pull-down signal, and the pull-down module is controlled to pull down the potential of the second node; the output module outputs a second clock signal of the second clock signal end to the scanning signal output end under the control of the potential of the first node.

S102, in a signal output stage, the second clock signal end provides an enabling level of the second clock signal, and the output module outputs the enabling level of the second clock signal under the control of the potential of the first node.

S103, in a reset stage, the scanning control end provides an enabling level of a scanning control signal, the first clock signal end provides an enabling level of a first clock signal, and the second node control module is controlled to transmit a first reference potential of the first reference signal end to a second node; the node mutual control module controls the second reference potential of the second reference signal end to be transmitted to the first node according to the potential of the second node; the output module outputs a second reference signal of the second reference signal end to the scanning signal output end under the control of the potential of the second node.

According to the driving method of the shift register, in the charging stage, the node mutual control module is used for controlling the second reference potential to be transmitted to the second node according to the potential of the first node, meanwhile, the pull-down control end is used for providing the enabling level of the pull-down control signal, the pull-down signal end is used for providing the non-enabling level of the pull-down signal, and the pull-down module is controlled to pull down the potential of the second node, so that the node mutual control module and the pull-down module can be used for carrying out double control on the potential of the second node, the potential of the second node is ensured to be the non-enabling level in the charging stage, the second reference potential is further ensured not to be transmitted to the first node, the influence of the second reference potential on the potential of the first node caused by transistor leakage is avoided, the influence on the output signal of the scanning signal output end is further avoided, the driving capability of the shift register is improved, and normal display is ensured.

On the basis of the above embodiment, the driving method may further include: in the intermittent stage, the scan control terminal provides a disable level of the scan control signal, the signal input terminal provides a disable level of the input signal, and the first node control module is controlled to be in a non-bias state. Thus, the adverse effect caused by the fact that the first node control module is in negative bias for a long time can be avoided.

For example, the intermittent phases may include a first intermittent phase, a second intermittent phase, and a third intermittent phase; the first intermittent stage is positioned between the charging stage and the signal output stage; the second intermittent stage is positioned between the signal output stage and the reset stage; the third intermittent stage is located after the reset stage or the third intermittent stage is located before the charging stage.

Based on the same inventive concept, the embodiments of the present invention also provide a scan driving circuit, and the scan driving circuit 100 includes a plurality of shift registers (ASGs) provided in any of the above embodiments; a plurality of shift registers are arranged in cascade. The scan driving circuit provided by the embodiment of the present invention also has the beneficial effects of the shift register in the foregoing embodiment, and the same points can be understood with reference to the explanation of the shift register, and are not described in detail below.

Fig. 11 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention, and illustrates a 4-stage shift register, which is respectively a first-stage shift register ASG1, a second-stage shift register ASG2, a third-stage shift register ASG3, and a fourth-stage shift register ASG4, where the four-stage shift registers are arranged in cascade.

Specifically, referring to fig. 11, the forward scan signal input end INF of the first stage shift register ASG1 is electrically connected to the forward start signal input end STVF of the scan driving circuit, and the scan signal output end GOUT i of the i stage shift register is electrically connected to the forward scan signal input end INF of the i+1th stage shift register, where i is a positive integer, so that forward scanning can be implemented. The reverse scan signal input terminal INB of the shift register (for example, ASG 4) of the last stage is electrically connected to the reverse start signal input terminal STVB of the scan driving circuit, and the scan signal output terminal GOUT (i+1) of the i+1th stage shift register is electrically connected to the reverse scan signal input terminal INB of the i-th stage shift register, i being a positive integer, so that the reverse scan can be realized.

The internal operation of each stage of shift register can be understood by referring to the above description, and is not repeated here. On the basis, taking forward scanning as an example, the shift register ASG1 of the first stage is triggered by a signal input by the forward starting signal input end STVF to start working; when the scan signal output end of the i-th shift register outputs a scan signal, the forward scan signal input end INF of the i+1-th shift register is triggered to start working.

Optionally, referring to fig. 11, when applied to the display panel, the display panel is provided with 4 clock signal lines, namely CKV1, CKV2, CKV3, and CKV4, and is further provided with a first reference signal line VGH, a second reference signal line VGL, a forward scan control line U2D, and a reverse scan control line D2U. Taking four cascaded shift registers of a scan driving circuit as an example, the forward scan control ends U2D of the shift registers of each stage are electrically connected with the forward scan control line U2D (the forward scan control line and the forward scan control end adopt the same mark); the forward scan control line U2D is configured to provide a forward scan control signal to the forward scan control terminal U2D. The reverse scanning control end D2U of each stage of shift register is electrically connected with the reverse scanning control line D2U (the reverse scanning control line and the reverse scanning control end adopt the same mark); the reverse scan control line D2U is configured to provide a reverse scan control signal to the reverse scan control terminal D2U. The first reference signal ends VGH of the shift registers of each stage are electrically connected with the first reference signal lines VGH (the first reference signal lines and the first reference signal ends are marked in the same way); the second reference signal terminals VGL of the shift registers of each stage are electrically connected to the second reference signal lines VGL (the second reference signal lines and the second reference signal terminals are labeled the same). The first forward scanning clock signal end RSTF of the first stage shift register is electrically connected with CKV3, the first reverse scanning clock signal end RSTB is electrically connected with CKV1, and the second clock signal end OUT is electrically connected with CKV 2. The first forward scanning clock signal end RSTF of the second stage shift register is electrically connected with CKV4, the first reverse scanning clock signal end RSTB is electrically connected with CKV2, and the second clock signal end OUT is electrically connected with CKV 3. The first forward scanning clock signal end RSTF of the third stage shift register is electrically connected with CKV1, the first reverse scanning clock signal end RSTB is electrically connected with CKV3, and the second clock signal end OUT is electrically connected with CKV 4. The first forward scanning clock signal end RSTF of the fourth stage shift register is electrically connected to CKV2, the first reverse scanning clock signal end RSTB is electrically connected to CKV4, and the second clock signal end OUT is electrically connected to CKV 1. The signals input by the same clock signal terminals of the two mutually cascaded shift registers differ by one clock pulse.

Based on the same inventive concept, the embodiment of the present invention further provides a display panel, and fig. 12 is a schematic structural diagram of the display panel provided by the embodiment of the present invention, and referring to fig. 12, the display panel 200 includes the scan driving circuit 100 provided by the above embodiment. Specifically, as shown in fig. 12, the display panel 200 includes a display area AA and a non-display area NA at least partially surrounding the display area AA, wherein the non-display area NA is provided with a scan driving circuit 100, the display area NA is provided with a pixel circuit 201, a gate line 202, a data line 203, and the like, and a stage shift register ASG in the scan driving circuit 100 may be electrically connected to at least one gate line 202.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 13 is a schematic structural diagram of the display device provided in the embodiment of the present invention, where the display device 300 includes the display panel 200 described above. The display device 300 provided in the embodiment of the present invention may be a mobile phone as shown in fig. 13, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the invention.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A shift register, comprising: the system comprises a first node control module, a second node control module, an output module, a node mutual control module, a pull-down module, a scanning control end, a signal input end, a first clock signal end, a second clock signal end, a first reference signal end, a second reference signal end, a scanning signal output end, a pull-down control end and a pull-down signal end;

the first node control module is respectively and electrically connected with the scanning control end and the signal input end; the first node control module is also electrically connected with the output module and is connected with a first node; in the charging stage, the first node control module is configured to charge the first node under control of a scan control signal of the scan control terminal and an input signal of the signal input terminal;

The second node control module is respectively and electrically connected with the first reference signal end, the first clock signal end and the scanning control end; the second node control module is also electrically connected with the output module and is connected with a second node; in a reset stage, the second node control module is configured to transmit a first reference potential of the first reference signal terminal to the second node under control of the scan control signal and a first clock signal of the first clock signal terminal;

the output module is also respectively and electrically connected with the second clock signal end, the second reference signal end and the scanning signal output end; the output module is used for outputting a second clock signal of the second clock signal end to the scanning signal output end under the control of the potential of the first node in the charging stage; in the reset stage, the output module is configured to output a second reference signal of the second reference signal terminal to the scan signal output terminal under control of the potential of the second node;

the node mutual control module is electrically connected with the first node, the second node and the second reference signal end respectively; in the charging stage, the node mutual control module is used for controlling the second reference potential of the second reference signal end to be transmitted to the second node according to the potential of the first node; in the reset stage, the node mutual control module is used for controlling the second reference potential of the second reference signal end to be transmitted to the first node according to the potential of the second node;

The pull-down module is electrically connected with the pull-down control end, the pull-down signal end and the second node respectively; the pull-down module is used for transmitting a non-enabling level of the pull-down signal to the second node under the control of the pull-down control signal in the charging stage.

2. The shift register of claim 1, wherein the scan control terminal provides an enable level of the scan control signal in the charging phase and the reset phase, and provides a scan control signal disable level in an intermittent phase;

the signal input terminal provides an enable level of an input signal in the charging phase and provides a disable level of the input signal in the intermittent phase and the reset phase;

in the intermittent stage, the first node control module is configured to be in an unbiased state under control of the scan control signal and the input signal.

3. The shift register of claim 2, wherein the second clock signal terminal is configured to provide a disable level of the second clock signal in the charging phase, the reset phase, and the intermittent phase, and to provide an enable level of the second clock signal in a signal output phase;

The scanning control end is also used for providing the enabling level of the scanning control signal in the signal output stage;

the signal input is also used for providing a non-enabling level of the input signal in the signal output stage;

wherein the signal output stage is located between the charging stage and the reset stage.

4. A shift register as claimed in claim 3, in which the rest phases comprise a first rest phase, a second rest phase and a third rest phase; the first intermittent stage is located between the charging stage and the signal output stage; the second intermittent stage is positioned between the signal output stage and the reset stage; the third intermittent stage is located after the reset stage or the third intermittent stage is located before the charging stage.

5. The shift register of claim 1, wherein the scan control terminal comprises a forward scan control terminal and a reverse scan control terminal; the signal input end comprises a forward scanning signal input end and a reverse scanning signal input end; the first clock signal end comprises a first forward scanning clock signal end and a first backward scanning clock signal end;

The forward scanning control end is used for providing the enabling level of a forward scanning control signal in the charging stage and the resetting stage of forward scanning; the reverse scanning control end is used for providing the enabling level of a reverse scanning control signal in the charging stage and the resetting stage of the reverse scanning;

the positive scanning signal input end is used for providing an enabling level of a positive input signal in a charging stage of the positive scanning; the inverted scan signal input is for providing an enable level of an inverted input signal during a charging phase of the inverted scan.

6. The shift register of claim 5, wherein said pull-down signal terminals comprise a forward pull-down signal terminal and a reverse pull-down signal terminal; the pull-down control end comprises a forward pull-down control end and a reverse pull-down control end;

the pull-down module is used for transmitting a non-enabling level of a forward pull-down signal of the forward pull-down signal end to the second node under the control of a forward pull-down control signal of the forward pull-down control end in a charging stage of the forward scanning; in the charging stage of the reverse scan, the pull-down module is configured to transmit a disable level of a reverse pull-down signal of the reverse pull-down signal terminal to the second node under control of a reverse pull-down control signal of the reverse pull-down control terminal;

The forward scanning signal input end is multiplexed to be the forward pull-down control end, and the reverse scanning signal input end is multiplexed to be the reverse pull-down control end; the forward scanning control end is multiplexed into the reverse pull-down signal end, and the reverse scanning control end is multiplexed into the forward pull-down signal end.

7. The shift register of claim 6, wherein the first node control module comprises a first transistor and a second transistor; the pull-down module comprises a third transistor and a fourth transistor;

the grid electrode of the first transistor and the grid electrode of the third transistor are electrically connected with the forward scanning signal input end; the grid electrode of the second transistor and the grid electrode of the fourth transistor are electrically connected with the reverse scanning signal input end; the first electrode of the first transistor and the first electrode of the fourth transistor are electrically connected with the forward scanning control end; the first electrode of the second transistor and the first electrode of the third transistor are electrically connected with the reverse scanning control end; a second pole of the first transistor and a second pole of the second transistor are both electrically connected with the first node; a second pole of the third transistor and a second pole of the fourth transistor are electrically connected with the second node;

Wherein a channel type of the first transistor is the same as a channel type of the third transistor, and a channel type of the second transistor is the same as a channel type of the fourth transistor.

8. The shift register of claim 5, wherein the second node control module comprises a fifth transistor, a sixth transistor, and a seventh transistor;

the grid electrode of the fifth transistor is electrically connected with the forward scanning control end, and the first electrode of the fifth transistor is electrically connected with the first forward scanning clock signal end; the grid electrode of the sixth transistor is electrically connected with the reverse scanning control end, and the first electrode of the sixth transistor is electrically connected with the first reverse scanning clock signal end; a second pole of the fifth transistor and a second pole of the sixth transistor are electrically connected with a gate of the seventh transistor;

the first pole of the seventh transistor is electrically connected to the first reference signal terminal, and the second pole of the seventh transistor is electrically connected to the second node.

9. The shift register of claim 1, wherein the node inter-control module comprises an eighth transistor and a ninth transistor;

The grid electrode of the eighth transistor is electrically connected with the second node, the first electrode of the eighth transistor is electrically connected with the second reference signal end, and the second electrode of the eighth transistor is electrically connected with the first node;

the grid electrode of the ninth transistor is electrically connected with the first node, the first electrode of the ninth transistor is electrically connected with the second reference signal end, and the second electrode of the ninth transistor is electrically connected with the second node.

10. The shift register of claim 9, wherein the output module comprises a tenth transistor, an eleventh transistor, a first capacitance, and a second capacitance;

the grid electrode of the tenth transistor and the first end of the first capacitor are electrically connected with the first node; a first pole of the tenth transistor is electrically connected with the second clock signal terminal; the second pole of the tenth transistor and the second end of the first capacitor are electrically connected with the scanning signal output end;

the grid electrode of the eleventh transistor and the first end of the second capacitor are electrically connected with the second node; the first pole of the eleventh transistor and the second end of the second capacitor are electrically connected with the second reference signal end; a second pole of the eleventh transistor is electrically connected with the scanning signal output end;

Wherein the eighth transistor is the same as the eleventh transistor in channel type; the ninth transistor is the same as the tenth transistor in channel type.

11. The shift register of any one of claims 1-10, wherein the first node comprises a first a node and a first b node; the first node control module is electrically connected with the first node, and the output module is electrically connected with the first node B;

the shift register also comprises a voltage stabilizing protection module; the voltage stabilizing protection module is respectively and electrically connected with the first reference signal end, the first node and the first second node; the voltage stabilizing protection module is used for maintaining the potential of the first node to be smaller than or equal to a preset voltage value under the control of the first reference signal end and the first node.

12. The shift register according to any one of claims 1 to 10, further comprising: the system comprises a first node potential adjusting module, a second node potential adjusting module and a starting control end;

the starting control end is used for providing an enabling level of a starting control signal in a starting stage;

the first node potential regulating module is respectively and electrically connected with the starting control end, the first reference signal end and the scanning signal output end; in the starting stage, the first node potential adjusting module is used for transmitting the first reference potential to the scanning signal output end under the control of the starting control signal;

The second node potential regulating module is respectively and electrically connected with the starting control end, the second reference signal end and the second node; the second node potential adjustment module is used for transmitting the second reference potential to the second node under the control of the starting control signal in the starting stage;

wherein the start-up phase is located before the charging phase and the reset phase.

13. A shift register driving method performed by using the shift register according to any one of claims 1 to 12, comprising:

in a charging stage, the scanning control end provides an enabling level of a scanning control signal, the signal input end provides an enabling level of an input signal, and the first node control module is controlled to charge the first node; the node mutual control module controls the second reference potential to be transmitted to the second node according to the potential of the first node; the pull-down control terminal provides an enabling level of a pull-down control signal, the pull-down signal terminal provides a non-enabling level of the pull-down signal, and the pull-down module is controlled to pull down the potential of the second node; the output module outputs a second clock signal of the second clock signal end to the scanning signal output end under the control of the potential of the first node;

In a signal output stage, the second clock signal end provides an enabling level of the second clock signal, and the output module outputs the enabling level of the second clock signal under the control of the potential of the first node;

in a reset stage, the scan control terminal provides an enable level of a scan control signal, the first clock signal terminal provides an enable level of a first clock signal, and the second node control module is controlled to transmit a first reference potential of the first reference signal terminal to the second node; the node mutual control module controls the second reference potential of the second reference signal end to be transmitted to the first node according to the potential of the second node; the output module outputs the second reference signal of the second reference signal end to the scanning signal output end under the control of the potential of the second node.

14. The driving method according to claim 13, characterized by further comprising:

in the intermittent stage, the scanning control end provides a non-enabling level of a scanning control signal, the signal input end provides a non-enabling level of an input signal, and the first node control module is controlled to be in a non-bias state.

15. A scan driving circuit, comprising: a plurality of shift registers according to any one of claims 1 to 12; a plurality of shift registers are arranged in cascade.

16. A display panel, comprising: the scan driving circuit of claim 15.

17. A display device, comprising: the display panel of claim 16.