CN105761663A

CN105761663A - Shift register unit, gate drive circuit and display device

Info

Publication number: CN105761663A
Application number: CN201610341470.3A
Authority: CN
Inventors: 金慧俊; 朱雪婧
Original assignee: Tianma Microelectronics Co Ltd; Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Tianma Microelectronics Co Ltd; Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2016-05-19
Filing date: 2016-05-19
Publication date: 2016-07-13
Anticipated expiration: 2036-05-19
Also published as: CN105761663B

Abstract

The invention provides a shift register unit, a gate drive circuit and a display device. The shift register unit comprises a first shift register unit body and a second shift register unit body which are similar to each other in structure, the first shift register unit body and the second shift register unit body control each other, and therefore scanning in the first order and scanning in the second order can be better achieved; besides, in the first shift register unit body, pull-down of a first node and pull-down of a first output end are double pull-downs, and in the second shift register unit body, pull-down of a fourth node and pull down of a second output end are double pull-downs, so that the waveform of a gate scanning signal output by the shift register unit is more stable; the display effect of the display device can be further improved through the shift register unit.

Description

Shift register cell, gate driver circuit and display device

Technical field

It relates to Display Technique field, it is specifically related to a kind of shift register cell, applies the gate driver circuit of this shift register cell and apply the display device of this gate driver circuit.

Background technology

Development along with optical technology Yu semiconductor technology, liquid crystal indicator (LiquidCrystalDisplay, and organic LED display device (OrganicLightEmittingDiode LCD), etc. OLED) panel display apparatus owing to having that body is more frivolous, cost and energy consumption is lower, response speed faster, excitation and brightness is more excellent and contrast more high, be widely used in each electronic product.

In above-mentioned display device, realize display mainly through picture element matrix.Typically, each row pixel is both coupled to the scanning grid line of correspondence.In display device work process, by gate driver circuit, the signals such as the clock signal of input are converted to through modules such as shift register cells the gated sweep signal controlling pixel on/off, gated sweep signal is sequentially applied to the scanning grid line of each row pixel of display device again, each row pixel is carried out gating.

But, shift register cell of the prior art and gate driver circuit still suffer from the part that haves much room for improvement.

It should be noted that in information disclosed in above-mentioned background section only for strengthening the understanding of background of this disclosure, therefore can include not constituting the information to prior art known to persons of ordinary skill in the art.

Summary of the invention

The purpose of the disclosure is in that to provide a kind of shift register cell, applies the gate driver circuit of this shift register cell and apply the display device of this gate driver circuit, for overcoming the one or more problems caused due to restriction and the defect of correlation technique at least to a certain extent.

Other characteristics of the disclosure and advantage will be apparent from by detailed description below, or partially by the practice of the disclosure and acquistion.

First aspect according to the disclosure, it is provided that a kind of shift register cell, including:

First input module, be used for responding one first input signal provides primary nodal point by one first sequential scan signal, and one second sequential scan signal is provided to described primary nodal point by response one first reset signal；

First output module, one first clock signal is provided to the first outfan by the signal for responding described primary nodal point；

First drop-down module, a pulldown signal is provided to described primary nodal point and described first outfan by the signal for responding a secondary nodal point；

Second drop-down module, described pulldown signal is provided to described secondary nodal point and one the 3rd node by the signal for responding described primary nodal point；

3rd drop-down module, described pulldown signal is provided to described secondary nodal point and the 3rd node by the signal for responding a fourth node；

4th drop-down module, described pulldown signal is provided to described primary nodal point and described first outfan by the signal for responding one the 5th node；

First charging module, one first charging signals is provided to described secondary nodal point by the signal for responding described 3rd node；

Second input module, be used for responding one second input signal provides described fourth node by described first sequential scan signal, and described second sequential scan signal is provided to described fourth node by response one second reset signal；

Second output module, a second clock signal is provided to the second outfan by the signal for responding described fourth node；

5th drop-down module, described pulldown signal is provided to described fourth node and described second outfan by the signal for responding described 5th node；

6th drop-down module, described pulldown signal is provided to described 5th node and one the 6th node by the signal for responding described fourth node；

7th drop-down module, described pulldown signal is provided to described 5th node and the 6th node by the signal for responding described primary nodal point；

8th drop-down module, described pulldown signal is provided to described fourth node and described second outfan by the signal for responding described secondary nodal point；

Second charging module, one second charging signals is provided to described 5th node by the signal for responding described 6th node, and described second charging signals is complementary with described first charging signals.

In a kind of exemplary embodiment of the disclosure, described shift register cell also includes:

9th drop-down module, being used for responding one the 3rd clock signal provides described pulldown signal to described first outfan；Described 3rd clock signal and described first clock signal complement；

Tenth drop-down module, being used for responding one the 4th clock signal provides described pulldown signal to described second outfan；Described 4th clock signal is complementary with described second clock signal.

In a kind of exemplary embodiment of the disclosure, wherein:

Described first input module includes:

The first transistor, the control termination of described the first transistor receives described first input signal, and the first termination of described the first transistor receives described first sequential scan signal, and the second end of described the first transistor is connected with described primary nodal point；

Transistor seconds, the control termination of described transistor seconds receives described first reset signal, and the first termination of described transistor seconds receives described second sequential scan signal, and the second end of described transistor seconds is connected with described primary nodal point；

Described second input module includes:

15th transistor, the control termination of described 15th transistor receives described second input signal, and the first termination of described 15th transistor receives described first sequential scan signal, and the second end of described 15th transistor is connected with described fourth node；

16th transistor, the control termination of described 16th transistor receives described second reset signal, and the first termination of described 16th transistor receives described second sequential scan signal, and the second end of described 16th transistor is connected with described fourth node.

In a kind of exemplary embodiment of the disclosure, wherein:

Described first output module includes:

Third transistor, the control end of described third transistor is connected with described primary nodal point, and the first termination of described third transistor receives described first clock signal, and the second end of described third transistor is connected with described first outfan；

First electric capacity, is connected between described primary nodal point and described first outfan；

Described second output module includes:

17th transistor, the control end of described 17th transistor is connected with described fourth node, and the first termination of described 17th transistor receives described second clock signal, and the second end of described 17th transistor is connected with described second outfan；

Second electric capacity, is connected between described fourth node and described second outfan.

In a kind of exemplary embodiment of the disclosure, wherein:

Described first drop-down module includes:

4th transistor, the control end of described 4th transistor is connected with described secondary nodal point, and the first termination of described 4th transistor receives described pulldown signal, and the second end of described 4th transistor is connected with described primary nodal point；

5th transistor, the control end of described 5th transistor is connected with described secondary nodal point, and the first termination of described 5th transistor receives described pulldown signal, and the second end of described 5th transistor is connected with described first outfan；

Described 5th drop-down module includes:

18th transistor, the control end of described 18th transistor is connected with described 5th node, and the first termination of described 18th transistor receives described pulldown signal, and the second end of described 18th transistor is connected with described fourth node；

19th transistor, the control end of described 19th transistor is connected with described 5th node, and the first termination of described 19th transistor receives described pulldown signal, and the second end of described 19th transistor is connected with described second outfan.

In a kind of exemplary embodiment of the disclosure, wherein:

Described second drop-down module includes:

6th transistor, the control end of described 6th transistor is connected with described primary nodal point, and the first termination of described 6th transistor receives described pulldown signal, and the second end of described 6th transistor is connected with described secondary nodal point；

7th transistor, the control end of described 7th transistor is connected with described primary nodal point, and the first termination of described 7th transistor receives described pulldown signal, and the second end of described 7th transistor is connected with described 3rd node；

Described 6th drop-down module includes:

20th transistor, the control end of described 20th transistor is connected with described fourth node, and the first termination of described 20th transistor receives described pulldown signal, and the second end of described 20th transistor is connected with described 5th node；

21st transistor, the control end of described 21st transistor is connected with described fourth node, and the first termination of described 21st transistor receives described pulldown signal, and the second end of described 21st transistor is connected with described 6th node.

In a kind of exemplary embodiment of the disclosure, wherein:

Described 3rd drop-down module includes:

8th transistor, the control end of described 8th transistor is connected with described fourth node, and the first termination of described 8th transistor receives described pulldown signal, and the second end of described 8th transistor is connected with described secondary nodal point；

9th transistor, the control end of described 9th transistor is connected with described fourth node, and the first termination of described 9th transistor receives described pulldown signal, and the second end of described 9th transistor is connected with described 3rd node；

Described 7th drop-down module includes:

20th two-transistor, the control end of described 20th two-transistor is connected with described primary nodal point, and the first termination of described 20th two-transistor receives described pulldown signal, and the second end of described 20th two-transistor is connected with described 5th node；

23rd transistor, the control end of described 23rd transistor is connected with described primary nodal point, and the first termination of described 23rd transistor receives described pulldown signal, and the second end of described 23rd transistor is connected with described 6th node.

In a kind of exemplary embodiment of the disclosure, wherein:

Described 4th drop-down module includes:

Tenth transistor, the control end of described tenth transistor is connected with described 5th node, and the first termination of described tenth transistor receives described pulldown signal, and the second end of described tenth transistor is connected with described primary nodal point；

11st transistor, the control end of described 11st transistor is connected with described 5th node, and the first termination of described 11st transistor receives described pulldown signal, and the second end of described 11st transistor is connected with described first outfan；

Described 8th drop-down module includes:

24th transistor, the control end of described 24th transistor is connected with described secondary nodal point, and the first termination of described 24th transistor receives described pulldown signal, and the second end of described 24th transistor is connected with described fourth node；

25th transistor, the control end of described 25th transistor is connected with described secondary nodal point, and the first termination of described 25th transistor receives described pulldown signal, and the second end of described 25th transistor is connected with described second outfan.

In a kind of exemplary embodiment of the disclosure, wherein:

Described first charging module includes:

Tenth two-transistor, the control end of described tenth two-transistor is connected with described 3rd node, and the first termination of described tenth two-transistor receives described first charging signals, and the second end of described tenth two-transistor is connected with described secondary nodal point；

13rd transistor, the control end of described 13rd transistor and the first termination receive described first charging signals, and the second end of described 13rd transistor is connected with described 3rd node；

Described second charging module includes:

26th transistor, the control end of described 26th transistor is connected with described 6th node, and the first termination of described 26th transistor receives described second charging signals, and the second end of described 26th transistor is connected with described 5th node；

27th transistor, the control end of described 27th transistor and the first termination receive described second charging signals, and the second end of described 27th transistor is connected with described 6th node.

In a kind of exemplary embodiment of the disclosure, wherein:

Described 9th drop-down module includes:

14th transistor, the control termination of described 14th transistor receives described 3rd clock signal, and the first termination of described 14th transistor receives described pulldown signal, and the second end of described 14th transistor is connected with described first outfan；

Described tenth drop-down module includes:

28th transistor, the control termination of described 28th transistor receives described 4th clock signal, and the first termination of described 28th transistor receives described pulldown signal, and the second end of described 28th transistor is connected with described second outfan.

In a kind of exemplary embodiment of the disclosure, described first sequential scan signal controls described shift register cell along the first sequential scan, described second sequential scan signal controls described shift register cell along the second sequential scan, and described first order is in opposite direction with described second order.

In a kind of exemplary embodiment of the disclosure, described first clock signal is overlapping with described second clock signal section；Described 3rd clock signal is overlapping with described 4th clock signal portion.

In a kind of exemplary embodiment of the disclosure, described transistor is N-type channel transistor or is P-type channel transistor.

In a kind of exemplary embodiment of the disclosure, described transistor is amorphous silicon transistor, low-temperature polycrystalline silicon transistor or oxide semi conductor transistor.

Second aspect according to the disclosure, it is provided that a kind of gate driver circuit, including any one shift register cell above-mentioned.

In a kind of exemplary embodiment of the disclosure, described gate driver circuit includes the N number of described shift register cell of cascade；Wherein:

First input signal described in m+1 level shift register cell is the signal of the first outfan output described in m level shift register cell；

Second input signal described in m+1 level shift register cell is the signal of the second outfan output described in m level shift register cell；

First reset signal described in m level shift register cell is the signal of the first outfan output described in m+1 level shift register cell；

Second reset signal described in m level shift register cell is the signal of the second outfan output described in m+1 level shift register cell；Wherein, 0 < m < N.

First input signal described in m+1 level shift register cell is the signal of the second outfan output described in m-1 level shift register cell；

Second input signal described in m+1 level shift register cell is the signal of the first outfan output described in m level shift register cell；

Second reset signal described in m-1 level shift register cell is the signal of the first outfan output described in m+1 level shift register cell；

First reset signal described in m level shift register cell is the signal of the second outfan output described in m+1 level shift register cell；Wherein, 1 < m < N.

The third aspect according to the disclosure, it is provided that a kind of display device, including any one gate driver circuit above-mentioned.

In the shift register cell that the example embodiment of the disclosure provides, first shift register cell similar including structure and the second shift register cell, and the first shift register cell and the second shift register cell control mutually, therefore can better realize the first sequential scan and the second sequential scan.In addition, in the first shift register cell, primary nodal point and the first outfan drop-down is double; two drop-down, in the second shift register cell, be double; two drop-down for fourth node and the second outfan drop-down, therefore the waveform of the gated sweep signal of shift register cell output is more stable.And then the shift register cell provided by the example embodiment of the disclosure can further promote the display effect of display device.

Accompanying drawing explanation

Its exemplary embodiment being described in detail by referring to accompanying drawing, the above-mentioned and further feature of the disclosure and advantage will be apparent from.

Fig. 1 is the structural representation of a kind of shift register cell in example embodiment of the present invention；

Fig. 2 is the structural representation of another kind of shift register cell in example embodiment of the present invention；

Fig. 3 A is driver' s timing and the signal waveform schematic diagram of shift register cell in Fig. 2；

Fig. 3 B is the waveform diagram of the first charging signals and the second charging signals in shift register cell in Fig. 2；

Fig. 4 is that in example embodiment of the present invention, the one of gate driver circuit realizes structural representation；

Fig. 5 is that in example embodiment of the present invention, the another kind of gate driver circuit realizes structural representation.

Detailed description of the invention

It is described more fully with exemplary embodiment referring now to accompanying drawing.But, exemplary embodiment can be implemented in a variety of forms, and is not understood as limited to embodiment set forth herein；On the contrary, it is provided that these embodiments make the disclosure will fully and completely, and the design of exemplary embodiment is conveyed to those skilled in the art all sidedly.In the drawings, in order to clearly, exaggerate, deform or simplify geomery.Accompanying drawing labelling identical in the drawings represents same or similar structure, thus will omit their detailed description.

Additionally, described feature, structure or step can be combined in one or more embodiment in any suitable manner.In the following description, it is provided that many details are thus providing fully understanding of embodiment of this disclosure.It will be appreciated, however, by one skilled in the art that one or more without in described specific detail of the technical scheme of the disclosure can be put into practice, or other method, step, structure etc. can be adopted.

This example embodiment provide firstly a kind of shift register cell.This shift register cell includes the first shift register cell and the second shift register cell, and the first shift register cell and the second shift register cell have similar structure.As shown in fig. 1, the first shift register cell includes the first input module M1, the first output module M2, the first drop-down module M3, the second drop-down module M4, the 3rd drop-down module M5, the 4th drop-down module M6 and the first charging module M7；Second shift register cell includes the second input module M8, the second output module M9, the 5th drop-down module M10, the 6th drop-down module M11, the 7th drop-down module M12, the 8th drop-down module M13 and the second charging module M14.Wherein:

First input module M1 may be used for response one first input signal SET1 and turns on, thus providing primary nodal point P1 by one first sequential scan signal FW, and respond one first reset signal RESET1 and turn on, thus one second sequential scan signal BW is provided to described primary nodal point P1.First output module M2 may be used for responding the signal of described primary nodal point P1 and turning on, thus providing one first clock signal CK1 to the first outfan GOUT1.First drop-down module M3 may be used for the signal of response one secondary nodal point P2 and turns on, thus providing a pulldown signal VGL to described primary nodal point P1 and described first outfan GOUT1.Second drop-down module M4 may be used for responding the signal of described primary nodal point P1 and turning on, thus providing described pulldown signal VGL to described secondary nodal point P2 and one the 3rd node P3.3rd drop-down module M5 may be used for the signal of response one fourth node P4 and turns on, thus providing described pulldown signal VGL to described secondary nodal point P2 and the 3rd node P3.4th drop-down module M6 may be used for the signal of response one the 5th node P5 and turns on, thus providing described pulldown signal VGL to described primary nodal point P1 and described first outfan GOUT1.First charging module M7 may be used for responding the signal of described 3rd node P3 and turning on, thus providing one first charging signals V1 to described secondary nodal point P2.

Second input module M8 may be used for response one second input signal SET2 and turns on, thus providing described fourth node P4 by described first sequential scan signal FW, and respond one second reset signal RESET2 and turn on, thus described second sequential scan signal BW is provided to described fourth node P4.Second output module M9 may be used for responding the signal of described fourth node P4 and turning on, thus providing a second clock signal CK2 to the second outfan GOUT2.5th drop-down module M10 may be used for responding the signal of described 5th node P5 and turning on, thus providing described pulldown signal VGL to described fourth node P4 and described second outfan GOUT2.6th drop-down module M11 may be used for responding the signal of described fourth node P4 and turning on, thus providing described pulldown signal VGL to described 5th node P5 and one the 6th node P6.7th drop-down module M12 may be used for responding the signal of described primary nodal point P1 and turning on, thus providing described pulldown signal VGL to described 5th node P5 and the 6th node P6.8th drop-down module M13 may be used for responding the signal of described secondary nodal point P2 and turning on, thus providing described pulldown signal VGL to described fourth node P4 and described second outfan GOUT2.Second charging module M14 may be used for responding the signal of described 6th node P6 and turning on, thus providing one second charging signals V2 to described 5th node P5；In this example embodiment, described second charging signals V2 is complementary with described first charging signals V1, and when namely the second charging signals V2 is positioned at high level, the first charging signals V1 is positioned at low level；When second charging signals V2 is positioned at low level, the first charging signals V1 is positioned at high level.

In the shift register cell that this example embodiment provides, first shift register cell similar including structure and the second shift register cell, and the first shift register cell and the second shift register cell control mutually, therefore can better realize the first sequential scan and the second sequential scan.In addition, in the first shift register cell, primary nodal point P1 and the first outfan GOUT1 drop-down is double; two drop-down, in the second shift register cell, be double; two drop-down for fourth node P4 and the second outfan GOUT2 drop-down, therefore the waveform of the gated sweep signal of shift register cell output is more stable.And then the display effect of display device can be further promoted by the shift register cell in this example embodiment.

Shown in Fig. 1, in order to promote the stability of the waveform of the gated sweep signal of output further, in this example embodiment, described first shift register cell can also include the 9th drop-down module M15, and described second shift register cell can include the tenth drop-down module M16.Wherein: the 9th drop-down module M15 may be used for response one the 3rd clock signal CK3 and turns on, thus described pulldown signal VGL is provided to described first outfan GOUT1；Described 3rd clock signal CK3 is complementary with described first clock signal CK1, for instance, described 3rd clock signal CK3 is the inversion signal etc. of described first clock signal CK1.Tenth drop-down module M16 may be used for response one the 4th clock signal CK4 and turns on, thus providing described pulldown signal VGL to described second outfan GOUT2；Described 4th clock signal CK4 and described second clock signal CK2 is complementary, for instance, described 4th clock signal CK4 is the inversion signal etc. of described second clock signal CK2.

Below, mainly consisted of example by transistor with above-mentioned each module the shift register cell in this example embodiment is further detailed.In this example embodiment, each described transistor all includes the first end, the second end and controls end, for instance, the first end, the second end and the control source electrode of end respectively transistor, drain electrode and grid；Or, the first end, the second end and the control drain electrode of end respectively transistor, source electrode and grid.Described transistor can be N-type channel transistor or be P-type channel transistor, will can be N-type channel transistor for described transistor and illustrate in this exemplary embodiment.Described transistor can be amorphous silicon transistor, low-temperature polycrystalline silicon transistor, oxide semi conductor transistor or other kinds of transistor, and this does not do in this exemplary embodiment particular determination.

Incorporated by reference to Fig. 1 and with reference to shown in Fig. 2, in this example embodiment, described first input module M1 can include the first transistor T1 and transistor seconds T2.Wherein: the control termination of described the first transistor T1 is received first termination of described first input signal SET1, described the first transistor T1 and received described first sequential scan signal FW, and second end of described the first transistor T1 is connected with described primary nodal point P1.The control termination of transistor seconds T2, described transistor seconds T2 is received first termination of described first reset signal RESET1, described transistor seconds T2 and is received described second sequential scan signal BW, and second end of described transistor seconds T2 is connected with described primary nodal point P1.

Similar with the first input module M1, described second input module M8 can include the 15th transistor T15 and the 16th transistor T16.Wherein: the control termination of described 15th transistor T15 is received first termination of described second input signal SET2, described 15th transistor T15 and received described first sequential scan signal FW, and second end of described 15th transistor T15 is connected with described fourth node P4.The control termination of described 16th transistor T16 is received first termination of described second reset signal RESET2, described 16th transistor T16 and is received described second sequential scan signal BW, and second end of described 16th transistor T16 is connected with described fourth node P4.

Shown in Fig. 2, in this exemplary embodiment, described first output module M2 can include third transistor T3 and the first electric capacity C1.Wherein: the control end of described third transistor T3 is connected with described primary nodal point P1, second end of first termination receipts described first clock signal CK1, the described third transistor T3 of described third transistor T3 is connected with described first outfan GOUT1.Described first electric capacity C1 is connected between described primary nodal point P1 and described first outfan GOUT1.

Similar with the first output module M2, described second output module M9 can include the 17th transistor T17 and the second electric capacity C2.Wherein: the control end of described 17th transistor T17 is connected with described fourth node P4, first termination of described 17th transistor T17 receives described second clock signal CK2, and second end of described 17th transistor T17 is connected with described second outfan GOUT2.Described second electric capacity C2 is connected between described fourth node P4 and described second outfan GOUT2.

Shown in Fig. 2, in this exemplary embodiment, described first drop-down module M3 can include the 4th transistor T4 and the 5th transistor T5.Wherein: the control end of described 4th transistor T4 is connected with described secondary nodal point P2, first termination of described 4th transistor T4 receives described pulldown signal VGL, and second end of described 4th transistor T4 is connected with described primary nodal point P1.The control end of described 5th transistor T5 is connected with described secondary nodal point P2, and first termination of described 5th transistor T5 receives described pulldown signal VGL, and second end of described 5th transistor T5 is connected with described first outfan GOUT1.

Similar with the first drop-down module M3, described 5th drop-down module M10 can include the 18th transistor T18 and the 19th transistor T19.Wherein: the control end of described 18th transistor T18 is connected with described 5th node P5, first termination of described 18th transistor T18 receives described pulldown signal VGL, and second end of described 18th transistor T18 is connected with described fourth node P4.The control end of described 19th transistor T19 is connected with described 5th node P5, and first termination of described 19th transistor T19 receives described pulldown signal VGL, and second end of described 19th transistor T19 is connected with described second outfan GOUT2.

Continuing with in conjunction with Fig. 1 and with reference to shown in Fig. 2, in this exemplary embodiment, described second drop-down module M4 can include the 6th transistor T6 and the 7th transistor T7.Wherein: the control end of described 6th transistor T6 is connected with described primary nodal point P1, first termination of described 6th transistor T6 receives described pulldown signal VGL, and second end of described 6th transistor T6 is connected with described secondary nodal point P2.The control end of described 7th transistor T7 is connected with described primary nodal point P1, and first termination of described 7th transistor T7 receives described pulldown signal VGL, and second end of described 7th transistor T7 is connected with described 3rd node P3.

Similar with the second drop-down module M4, described 6th drop-down module M11 can include the 20th transistor T20 and the 21st transistor T21.Wherein: the control end of described 20th transistor T20 is connected with described fourth node P4, first termination of described 20th transistor T20 receives described pulldown signal VGL, and second end of described 20th transistor T20 is connected with described 5th node P5.The control end of described 21st transistor T21 is connected with described fourth node P4, and first termination of described 21st transistor T21 receives described pulldown signal VGL, and second end of described 21st transistor T21 is connected with described 6th node P6.

Continuing with in conjunction with Fig. 1 and with reference to shown in Fig. 2, in this exemplary embodiment, described 3rd drop-down module M5 can include the 8th transistor T8 and the 9th transistor T9.Wherein: the control end of described 8th transistor T8 is connected with described fourth node P4, first termination of described 8th transistor T8 receives described pulldown signal VGL, and second end of described 8th transistor T8 is connected with described secondary nodal point P2.The control end of described 9th transistor T9 is connected with described fourth node P4, and first termination of described 9th transistor T9 receives described pulldown signal VGL, and second end of described 9th transistor T9 is connected with described 3rd node P3.

Similar with the 3rd drop-down module M5, described 7th drop-down module M12 can include the 20th two-transistor T22 and the 23rd transistor T23.Wherein: the control end of described 20th two-transistor T22 is connected with described primary nodal point P1, first termination of described 20th two-transistor T22 receives described pulldown signal VGL, and second end of described 20th two-transistor T22 is connected with described 5th node P5.The control end of described 23rd transistor T23 is connected with described primary nodal point P1, and first termination of described 23rd transistor T23 receives described pulldown signal VGL, and second end of described 23rd transistor T23 is connected with described 6th node P6.

Continuing with in conjunction with Fig. 1 and with reference to shown in Fig. 2, in this exemplary embodiment, described 4th drop-down module M6 can include the tenth transistor T10 and the 11st transistor T11.Wherein: the control end of described tenth transistor T10 is connected with described 5th node P5, first termination of described tenth transistor T10 receives described pulldown signal VGL, and second end of described tenth transistor T10 is connected with described primary nodal point P1.The control end of described 11st transistor T11 is connected with described 5th node P5, and first termination of described 11st transistor T11 receives described pulldown signal VGL, and second end of described 11st transistor T11 is connected with described first outfan GOUT1.

Similar with the 4th drop-down module M6, described 8th drop-down module M13 can include the 24th transistor T24 and the 25th transistor T25.Wherein: the control end of described 24th transistor T24 is connected with described secondary nodal point P2, first termination of described 24th transistor T24 receives described pulldown signal VGL, and second end of described 24th transistor T24 is connected with described fourth node P4.The control end of described 25th transistor T25 is connected with described secondary nodal point P2, and first termination of described 25th transistor T25 receives described pulldown signal VGL, and second end of described 25th transistor T25 is connected with described second outfan GOUT2.

Continuing with in conjunction with Fig. 1 and with reference to shown in Fig. 2, in this exemplary embodiment, described first charging module M7 can include the tenth two-transistor T12 and the 13rd transistor T13.Wherein: the control end of described tenth two-transistor T12 is connected with described 3rd node P3, first termination of described tenth two-transistor T12 receives described first charging signals V1, and second end of described tenth two-transistor T12 is connected with described secondary nodal point P2.The control end of described 13rd transistor T13 and the first termination receive described first charging signals V1, and second end of described 13rd transistor T13 is connected with described 3rd node P3.

Similar with the first charging module M7, described second charging module M14 can include the 26th transistor T26 and the 27th transistor T27.Wherein: the control end of described 26th transistor T26 is connected with described 6th node P6, first termination of described 26th transistor T26 receives described second charging signals V2, and second end of described 26th transistor T26 is connected with described 5th node P5.The control end of described 27th transistor T27 and the first termination receive described second charging signals V2, and second end of described 27th transistor T27 is connected with described 6th node P6.

Continuing with in conjunction with Fig. 1 and with reference to shown in Fig. 2, in this exemplary embodiment, described 9th drop-down module M15 can include the 14th transistor T14.Wherein: the control termination of described 14th transistor T14 is received first termination of described 3rd clock signal CK3, described 14th transistor T14 and received described pulldown signal VGL, and second end of described 14th transistor T14 is connected with described first outfan GOUT1.

Similar with the 9th drop-down module M15, described tenth drop-down module M16 can include the 28th transistor T28.Wherein: the control termination of described 28th transistor T28 receives described 4th clock signal CK4, first termination of described 28th transistor T28 receives described pulldown signal VGL, and second end of described 28th transistor T28 is connected with described second outfan GOUT2.

Please continue to refer to Fig. 2, and in conjunction with the driver' s timing figure in Fig. 3 A, the operation principle of the shift register cell in this example embodiment is described in more detail.In this example embodiment, described first sequential scan signal FW can control described shift register cell along the first sequential scan, described second sequential scan signal BW can control described shift register cell along the second sequential scan, described first order is in opposite direction with described second order, for instance respectively forward scan and reverse scan.When forward scan, the first sequential scan signal FW is high level signal, and the second sequential scan signal BW is low level signal, and when reverse scan, the first sequential scan signal FW is low level signal, and the second sequential scan signal BW is high level signal；Hereinafter will illustrate for forward scan.With reference to shown in Fig. 3 A, in this example embodiment, clock signal CK31/2 the signal period of phase-lead the 3rd of the first clock signal CK1, the dutycycle of the first clock signal CK1 and the 3rd clock signal CK3 is 1/2, and the first clock signal CK1 and the three clock signal CK3 is complementary.Clock signal CK41/2 the signal period of phase-lead the 4th of second clock signal CK2, the dutycycle of second clock signal CK2 and the 4th clock signal CK4 is 1/2, and second clock signal CK2 and the four clock signal CK4 is complementary.Described first clock signal CK1 and described second clock signal CK2 partly overlaps, for instance phase-lead CK21/4 the signal period of second clock signal of the first clock signal CK1.Described 3rd clock signal CK3 and described 4th clock signal CK4 partly overlaps, for instance clock signal CK41/4 the signal period of phase-lead the 4th of the 3rd clock signal CK3.In this example embodiment, first stage t1 in the example shown～the 5th stage t5, the first charging signals V1 is such as low level, and the second charging signals V2 is such as high level.With reference to shown in Fig. 3 B, in this example embodiment, phase-lead V21/2 the signal period of the second charging signals of the first charging signals V1, the dutycycle of the first charging signals V1 and the second charging signals V2 is 1/2, and the signal period of the first charging signals V1 and the second charging signals V2 such as can be 2 seconds.For the first shift register cell in shift register cell, its work process can include with the next stage:

Continuing with combining referring to figs. 2 and 3 A, at first stage t1, first input signal SET1 is that high level is (in this example embodiment, input signal SET1 and second input signal SET2 for described first and be initial signal STV), the first clock signal CK1, the 3rd clock signal CK3 and the first reset signal RESET1 are low level；The first transistor T1 turns on.First sequential scan signal FW of high level is inputted to primary nodal point P1 by the first transistor T1, charges to the first electric capacity C1.Owing to the voltage of primary nodal point P1 is high level, so that third transistor T3, the 6th transistor T6, the 7th transistor T7, the 20th two-transistor T22 and the 23rd transistor T23 conducting.Pulldown signal VGL is inputted to secondary nodal point P2 by the 6th transistor T6, and making secondary nodal point P2 is low level.Pulldown signal VGL is inputted to the 3rd node P3 by the 7th transistor T7, and making the 3rd node P3 is low level.Pulldown signal VGL is inputted to the 5th node P5 by the 20th two-transistor T22, and making the 5th node P5 is low level.Pulldown signal VGL is inputted to the 6th node P6 by the 23rd transistor T23, and making the 6th node P6 is low level (in this example embodiment, the absolute value of the voltage of the described pulldown signal VGL absolute value more than described second charging signals V2).Additionally, in the t1 stage, the voltage of fourth node P4 is high level, so that the 8th transistor T8 and the 9th transistor T9 conducting.Pulldown signal VGL is inputted to secondary nodal point P2 by the 8th transistor T8, makes the level of secondary nodal point P2 by drop-down further.Pulldown signal VGL is inputted to the 3rd node P3 by the 9th transistor T9, makes the level of Psychotria rubra (Lour.) Poir. point by drop-down further.First clock signal CK1 export from the first outfan GOUT1 by third transistor T3, and owing to the first clock signal CK1 is low level in the t1 stage, what therefore the first shift register cell in shift register cell exported is low level signal.

With reference to shown in Fig. 3 A, at second stage t2, the first clock signal CK1 is high level, and the first input signal SET1, the 3rd clock signal CK3 and the first reset signal RESET1 is low level, and the first transistor T1 turns off.Under the high level voltage signal function of the first electric capacity C1 storage, the voltage of primary nodal point P1 is still high level, so that third transistor T3, the 6th transistor T6, the 7th transistor T7, the 20th two-transistor T22 and the 23rd transistor T23 are held on.Pulldown signal VGL is inputted to secondary nodal point P2 by the 6th transistor T6, and making secondary nodal point P2 is low level.Pulldown signal VGL is inputted to the 3rd node P3 by the 7th transistor T7, and making the 3rd node P3 is low level.Pulldown signal VGL is inputted to the 5th node P5 by the 20th two-transistor T22, and making the 5th node P5 is low level.Pulldown signal VGL is inputted to the 6th node P6 by the 23rd transistor T23, and making the 6th node P6 is low level.Additionally, in the t2 stage, the voltage of fourth node P4 is high level, so that the 8th transistor T8 and the 9th transistor T9 conducting.Pulldown signal VGL is inputted to secondary nodal point P2 by the 8th transistor T8, makes the level of secondary nodal point P2 by drop-down further.Pulldown signal VGL is inputted to the 3rd node P3 by the 9th transistor T9, makes the level of Psychotria rubra (Lour.) Poir. point by drop-down further.First clock signal CK1 export from the first outfan GOUT1 by third transistor T3, and owing to the first clock signal CK1 is high level in the t2 stage, what therefore shift register cell exported is high level signal.

With reference to shown in Fig. 3 A, at phase III t3, the 3rd clock signal CK3 and the first reset signal RESET1 is high level, and the first input signal SET1 and the first clock signal CK1 is low level, transistor seconds T2 and the 14th transistor T14 conducting.Low level first reset signal RESET1 is inputted to primary nodal point P1 by transistor seconds T2, and the first electric capacity C1 is resetted.Owing to the voltage of primary nodal point P1 is low level, so that third transistor T3, the 6th transistor T6, the 7th transistor T7, the 20th two-transistor T22 and the 23rd transistor T23 turn off.Additionally, in the second half section in t3 stage, the voltage of fourth node P4 is low level, so that the 8th transistor T8, the 9th transistor T9 and the 21st transistor T21 turn off.Owing to the second charging signals V2 is high level, the 27th transistor T27 conducting, the second charging signals V2 inputs to the 6th node P6；Closing at the 21st transistor T21 and the 23rd transistor T23 and have no progeny, the voltage of described 6th node P6 is described second charging signals V2, and therefore described 6th node P6 is high level, described 26th transistor T26 conducting.The flat described second charging signals V2 of high point is by described 26th transistor T26 input to described 5th node P5, and making described 5th node P5 is high level.Owing to the voltage of the 5th node P5 is high level, so that the tenth transistor T10 and the 11st transistor T11 conducting.Pulldown signal VGL is inputted to primary nodal point P1 by the tenth transistor T10, makes the level of primary nodal point P1 by drop-down further.Pulldown signal VGL is by the 14th transistor T14 input to signal output part, and therefore shift register cell output is low level signal.Pulldown signal VGL is inputted to the first outfan GOUT1 by the 11st transistor T11, makes the level of the first outfan GOUT1 by drop-down further, and then makes the output of shift register cell more stable.

In above-mentioned exemplary embodiment, the second charging signals V2 is high level, and the first charging signals V1 is low level, but the second charging signals V2 is low level, the first charging signals V1 is that situation during high level is similar.Such as, owing to the first charging signals V1 is high level, the 13rd transistor T13 conducting, the first charging signals V1 inputs to the 3rd node P3；Closing at the 7th transistor T7 and the 9th transistor T9 and have no progeny, the voltage of described 3rd node P3 is described first charging signals V1, and therefore described 3rd node P3 is high level, described tenth two-transistor T12 conducting.The flat described first charging signals V1 of high point is by described tenth two-transistor T12 input to described secondary nodal point P2, and making described secondary nodal point P2 is high level.Owing to the voltage of secondary nodal point P2 is high level, so that the 4th transistor T4, the 5th transistor T5, the 24th transistor T24 and the 25th transistor T25 conducting.Pulldown signal VGL is inputted to primary nodal point P1 by the 4th transistor T4, makes the level of primary nodal point P1 by drop-down further.Pulldown signal VGL is inputted to the first outfan GOUT1 by the 5th transistor T5, makes the level of the first outfan GOUT1 by drop-down further, and then makes the output of shift register cell more stable.

With reference to shown in Fig. 3 A, in t4 to the t5 stage after phase III t3, under the effect of the second charging signals V2, described 5th node P5 remains high level.Owing to the voltage of the 5th node P5 is high level, so that the tenth transistor T10 and the 11st transistor T11 is held on.Pulldown signal VGL is inputted to primary nodal point P1 by the tenth transistor T10, makes the level of primary nodal point P1 remain low level.Pulldown signal VGL is by the 11st transistor T11 input to signal output part, and therefore shift register cell output is low level signal.And, when the 3rd clock signal CK3 is high level, described 14th transistor T14 conducting, pulldown signal VGL is by the 14th transistor T14 input to the first outfan GOUT1, make the level of the first outfan GOUT1 by drop-down further, and then make the output of shift register cell more stable.

In shift register cell, the work schedule of the second shift register cell and the first shift register cell are similar, therefore repeat no more herein.Additionally, in above-mentioned exemplary embodiment, be illustrate for forward scan, but when reverse scan, the work schedule of shift register cell is similar with forward scan, therefore repeats no more equally herein.

The other advantage of above-mentioned shift register cell is exactly that the transistor that have employed single channel type is namely entirely for N-type TFT, the thin film transistor (TFT) adopting uniform type can reduce complexity and the production cost of preparation technology, and contributes to Improving The Quality of Products.Certainly, those skilled in the art are easy to show that shift register cell provided by the present invention can make into easily entirely for P-type transistor；Wherein, when each described transistor is P-type transistor, the level of above-mentioned each signal carries out accommodation, is therefore not limited to the implementation provided in this example embodiment.

Further, this example embodiment additionally provides a kind of gate driver circuit, and this gate driver circuit includes any one above-mentioned shift register cell.For example:

With reference to shown in Fig. 4, in this example embodiment, gate driver circuit can include N number of shift register cells (all the other more shift register cells are not shown) such as the first shift register cell SR1, the second shift register cell SR2, the 3rd shift register cell SR3 and the 4th shift register cell SR4, wherein, G1～G8 represents the gate line electrically connected with each shift register cell.In this example embodiment, the first input signal SET1 described in m+1 level shift register cell is the signal (described in the 1st grade of shift register cell, the first input signal SET1 is initial signal STV) of the first outfan GOUT1 output described in m level shift register cell；Second input signal SET2 described in m+1 level shift register cell is the signal (described in the 1st grade of shift register cell, the second input signal SET2 is initial signal STV) of the second outfan GOUT2 output described in m level shift register cell；First reset signal RESET1 described in m level shift register cell is the signal (most final stage shift register cell described in the first reset signal RESET1 be reset signal RST) of the first outfan GOUT1 output described in m+1 level shift register cell；Second reset signal RESET2 described in m level shift register cell is the signal (most final stage shift register cell described in the second reset signal RESET2 be reset signal RST2) of the second outfan GOUT2 output described in m+1 level shift register cell；Wherein, 0 < m < N.Namely as shown in FIG., the first input signal SET1 described in 3rd level shift register cell is the signal of the first outfan GOUT1 output described in the 2nd grade of shift register cell；Second input signal SET2 described in 3rd level shift register cell is the signal of the second outfan GOUT2 output described in the 2nd grade of shift register cell；First reset signal RESET1 described in 2nd grade of shift register cell is the signal of the first outfan GOUT1 output described in 3rd level shift register cell；Second reset signal RESET2 described in 2nd grade of shift register cell is signal of the second outfan GOUT2 output etc. described in 3rd level shift register cell.

With reference to shown in Fig. 5, in this example embodiment, gate driver circuit can include N number of shift register cells (all the other more shift register cells are not shown) such as the first shift register cell SR1, the second shift register cell SR2, the 3rd shift register cell SR3, the 4th shift register cell SR4, the 5th shift register cell SR5 and the 6th shift register cell SR6, wherein, G1～G12 represents the gate line electrically connected with each shift register cell.In this example embodiment, described in m+1 level shift register cell first input signal SET1 be described in m-1 level shift register cell second outfan GOUT2 output signal (the 1st grade and described in the 2nd grade of shift register cell first input signal SET1 be initial signal STV)；Second input signal SET2 described in m+1 level shift register cell is the signal (described in the 1st grade of shift register cell, the second input signal SET2 is initial signal STV) of the first outfan GOUT1 output described in m level shift register cell；Second reset signal RESET2 described in m-1 level shift register cell is the signal (the second reset signal RESET2 described in reciprocal 2nd grade and most final stage shift register cell is reset signal RST) of the first outfan GOUT1 output described in m+1 level shift register cell；First reset signal RESET1 described in m level shift register cell is the signal (most final stage shift register cell described in the first reset signal RESET1 be reset signal RST) of the second outfan GOUT2 output described in m+1 level shift register cell；Wherein, 1 < m < N.Namely as shown in FIG., the first input signal SET1 described in the 4th grade of shift register cell is the signal of the second outfan GOUT2 output described in the 2nd grade of shift register cell；Second input signal SET2 described in 4th grade of shift register cell is the signal of the first outfan GOUT1 output described in 3rd level shift register cell；Second reset signal RESET2 described in 2nd grade of shift register cell is the signal of the first outfan GOUT1 output described in the 4th grade of shift register cell；First reset signal RESET1 described in 3rd level shift register cell is signal of the second outfan GOUT2 output etc. described in the 4th grade of shift register cell.

Skilled addressee readily understands that, the gate driver circuit in Fig. 4 and Fig. 5 only plays example effect；In other exemplary embodiments of the disclosure, comprising the gate driver circuit of any one shift register cell above-mentioned in this example embodiment can also be other connected modes, and this does not do in this exemplary embodiment particular determination.

Further, this example embodiment additionally provides a kind of display device, and this display device includes any one above-mentioned gate driver circuit.In this exemplary embodiment, this display device can be liquid crystal indicator or OLED display, in other exemplary embodiments of the disclosure, this display device is also likely to be PLED (PolymerLight-EmittingDiode, polymer LED) display device, PDP (PlasmaDisplayPanel, plasma shows) other panel display apparatus such as display device, namely do not limit to the scope of application especially in this example embodiment.

In sum, in the shift register cell that this example embodiment provides, first shift register cell similar including structure and the second shift register cell, and the first shift register cell and the second shift register cell control mutually, therefore can better realize the first sequential scan and the second sequential scan.In addition, in the first shift register cell, primary nodal point and the first outfan drop-down is double; two drop-down, in the second shift register cell, be double; two drop-down for fourth node and the second outfan drop-down, therefore the waveform of the gated sweep signal of shift register cell output is more stable.And then the display effect of display device can be further promoted by the shift register cell in this example embodiment.

The disclosure is been described by by above-mentioned related embodiment, but above-described embodiment is only the example implementing the disclosure.It must be noted that, the embodiment disclosed is not limiting as the scope of the present disclosure.On the contrary, the change made in without departing from the spirit and scope of the disclosure and retouching, all belong to the scope of patent protection of the disclosure.

Claims

1. a shift register cell, it is characterised in that including:

2. shift register cell according to claim 1, it is characterised in that described shift register cell also includes:

3. shift register cell according to claim 2, it is characterised in that wherein:

Described first input module includes:

Described second input module includes:

4. shift register cell according to claim 2, it is characterised in that wherein:

Described first output module includes:

Described second output module includes:

5. shift register cell according to claim 2, it is characterised in that wherein:

Described first drop-down module includes:

Described 5th drop-down module includes:

6. shift register cell according to claim 2, it is characterised in that wherein:

Described second drop-down module includes:

Described 6th drop-down module includes:

7. shift register cell according to claim 2, it is characterised in that wherein:

Described 3rd drop-down module includes:

Described 7th drop-down module includes:

8. shift register cell according to claim 2, it is characterised in that wherein:

Described 4th drop-down module includes:

Described 8th drop-down module includes:

9. shift register cell according to claim 2, it is characterised in that wherein:

Described first charging module includes:

Described second charging module includes:

10. shift register cell according to claim 2, it is characterised in that wherein:

Described 9th drop-down module includes:

Described tenth drop-down module includes:

11. according to the shift register cell described in claim 1～10 any one, it is characterized in that, described first sequential scan signal controls described shift register cell along the first sequential scan, described second sequential scan signal controls described shift register cell along the second sequential scan, and described first order is in opposite direction with described second order.

12. according to the shift register cell described in claim 2～10 any one, it is characterised in that described first clock signal is overlapping with described second clock signal section；Described 3rd clock signal is overlapping with described 4th clock signal portion.

13. according to the shift register cell described in claim 3～10 any one, it is characterised in that described transistor is N-type channel transistor or is P-type channel transistor.

14. according to the shift register cell described in claim 3～10 any one, it is characterised in that described transistor is amorphous silicon transistor, low-temperature polycrystalline silicon transistor or oxide semi conductor transistor.

15. a gate driver circuit, it is characterised in that include the shift register cell according to claim 1～14 any one.

16. gate driver circuit according to claim 15, it is characterised in that described gate driver circuit includes the N number of described shift register cell of cascade；Wherein:

17. gate driver circuit according to claim 15, it is characterised in that described gate driver circuit includes the N number of described shift register cell of cascade；Wherein:

18. a display device, it is characterised in that include gate driver circuit according to claim 15～17 any one.