CN105761663B - Shift register cell, gate driving circuit and display device - Google Patents

Abstract

The disclosure provides a shift register unit, a gate driving circuit and a display device. The shift register unit includes a first shift register unit and a second shift register unit similar in structure, and the first shift register unit and the second shift register unit control each other, so the first sequence can be better realized scan and second order scan. In addition, in the first shift register unit, both the pull-down of the first node and the first output terminal are double-pull-down, and in the second shift register unit, the pull-down of the fourth node and the second output terminal are both double-pull-down, Therefore, the waveform of the gate scanning signal output by the shift register unit is more stable. Furthermore, the display effect of the display device can be further improved through the shift register unit provided by the exemplary embodiments of the present disclosure.

Description

Shift register unit, gate drive circuit and display device

technical field

The present disclosure relates to the field of display technology, and in particular to a shift register unit, a gate drive circuit using the shift register unit, and a display device using the gate drive circuit.

Background technique

With the development of optical technology and semiconductor technology, flat-panel display devices such as Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED) have thinner and thinner shapes, lower costs and lower energy consumption. , faster response, better color purity and brightness, and higher contrast have been widely used in various electronic products.

In the above-mentioned display device, the display is mainly implemented through a pixel matrix. Generally, each row of pixels is coupled to a corresponding scan gate line. During the working process of the display device, the input clock signal and other signals are converted into gate scanning signals to control the on/off of pixels through modules such as shift register units through the gate drive circuit, and then the gate scanning signals are applied to the The scanning gate lines of each row of pixels of the display device gate each row of pixels.

However, the shift register unit and the gate driving circuit in the prior art still have room for improvement.

It should be noted that the information disclosed in the above background section is only for enhancing the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.

Contents of the invention

The purpose of the present disclosure is to provide a shift register unit, a gate drive circuit using the shift register unit, and a display device using the gate drive circuit, which are used to overcome the limitations and defects of related technologies at least to a certain extent. resulting in one or more problems.

Other features and advantages of the present disclosure will become apparent from the following detailed description, or in part, be learned by practice of the present disclosure.

According to a first aspect of the present disclosure, there is provided a shift register unit, comprising:

The first input module is used to provide a first sequential scan signal to the first node in response to a first input signal, and provide a second sequential scan signal to the first node in response to a first reset signal;

a first output module, configured to provide a first clock signal to a first output terminal in response to a signal of the first node;

The first pull-down module is configured to provide a pull-down signal to the first node and the first output terminal in response to a signal of a second node;

a second pull-down module, configured to provide the pull-down signal to the second node and a third node in response to the signal of the first node;

a third pull-down module, configured to provide the pull-down signal to the second node and the third node in response to a signal of a fourth node;

a fourth pull-down module, configured to provide the pull-down signal to the first node and the first output terminal in response to a signal of a fifth node;

a first charging module, configured to provide a first charging signal to the second node in response to a signal from the third node;

A second input module, configured to provide the first sequential scan signal to the fourth node in response to a second input signal, and provide the second sequential scan signal to the fourth node in response to a second reset signal ;

a second output module, configured to provide a second clock signal to the second output terminal in response to the signal of the fourth node;

a fifth pull-down module, configured to provide the pull-down signal to the fourth node and the second output terminal in response to the signal of the fifth node;

a sixth pull-down module, configured to provide the pull-down signal to the fifth node and a sixth node in response to the signal of the fourth node;

a seventh pull-down module, configured to provide the pull-down signal to the fifth node and the sixth node in response to the signal of the first node;

an eighth pull-down module, configured to provide the pull-down signal to the fourth node and the second output terminal in response to the signal of the second node;

The second charging module is configured to provide a second charging signal to the fifth node in response to the signal of the sixth node, the second charging signal is complementary to the first charging signal.

In an exemplary embodiment of the present disclosure, the shift register unit further includes:

A ninth pull-down module, configured to provide the pull-down signal to the first output terminal in response to a third clock signal; the third clock signal is complementary to the first clock signal;

The tenth pull-down module is configured to provide the pull-down signal to the second output terminal in response to a fourth clock signal; the fourth clock signal is complementary to the second clock signal.

In an exemplary embodiment of the present disclosure, wherein:

The first input module includes:

A first transistor, the control terminal of the first transistor receives the first input signal, the first terminal of the first transistor receives the first sequential scanning signal, the second terminal of the first transistor is connected to the first node connection;

A second transistor, the control terminal of the second transistor receives the first reset signal, the first terminal of the second transistor receives the second sequential scan signal, the second terminal of the second transistor is connected to the first node connection;

The second input module includes:

A fifteenth transistor, the control end of the fifteenth transistor receives the second input signal, the first end of the fifteenth transistor receives the first sequential scan signal, and the second of the fifteenth transistor connected to the fourth node;

The sixteenth transistor, the control end of the sixteenth transistor receives the second reset signal, the first end of the sixteenth transistor receives the second sequential scan signal, the second of the sixteenth transistor connected to the fourth node.

In an exemplary embodiment of the present disclosure, wherein:

The first output module includes:

a third transistor, the control terminal of the third transistor is connected to the first node, the first terminal of the third transistor receives the first clock signal, and the second terminal of the third transistor is connected to the first node an output connection;

a first capacitor connected between the first node and the first output terminal;

The second output module includes:

A seventeenth transistor, the control end of the seventeenth transistor is connected to the fourth node, the first end of the seventeenth transistor receives the second clock signal, and the second end of the seventeenth transistor connected to the second output terminal;

The second capacitor is connected between the fourth node and the second output terminal.

In an exemplary embodiment of the present disclosure, wherein:

The first pull-down module includes:

A fourth transistor, the control end of the fourth transistor is connected to the second node, the first end of the fourth transistor receives the pull-down signal, the second end of the fourth transistor is connected to the first node connect;

a fifth transistor, the control terminal of the fifth transistor is connected to the second node, the first terminal of the fifth transistor receives the pull-down signal, and the second terminal of the fifth transistor is connected to the first output terminal connection;

The fifth pull-down module includes:

An eighteenth transistor, the control end of the eighteenth transistor is connected to the fifth node, the first end of the eighteenth transistor receives the pull-down signal, the second end of the eighteenth transistor is connected to the The fourth node is connected;

A nineteenth transistor, the control end of the nineteenth transistor is connected to the fifth node, the first end of the nineteenth transistor receives the pull-down signal, the second end of the nineteenth transistor is connected to the connected to the second output terminal.

In an exemplary embodiment of the present disclosure, wherein:

The second pull-down module includes:

A sixth transistor, the control terminal of the sixth transistor is connected to the first node, the first terminal of the sixth transistor receives the pull-down signal, and the second terminal of the sixth transistor is connected to the second node connect;

A seventh transistor, the control end of the seventh transistor is connected to the first node, the first end of the seventh transistor receives the pull-down signal, the second end of the seventh transistor is connected to the third node connect;

The sixth drop-down module includes:

A twentieth transistor, the control end of the twentieth transistor is connected to the fourth node, the first end of the twentieth transistor receives the pull-down signal, and the second end of the twentieth transistor is connected to the fourth node. The fifth node is connected;

A twenty-first transistor, the control terminal of the twenty-first transistor is connected to the fourth node, the first terminal of the twenty-first transistor receives the pull-down signal, and the first terminal of the twenty-first transistor receives the pull-down signal. The two ends are connected to the sixth node.

In an exemplary embodiment of the present disclosure, wherein:

The third pull-down module includes:

An eighth transistor, the control end of the eighth transistor is connected to the fourth node, the first end of the eighth transistor receives the pull-down signal, the second end of the eighth transistor is connected to the second node connect;

A ninth transistor, the control end of the ninth transistor is connected to the fourth node, the first end of the ninth transistor receives the pull-down signal, the second end of the ninth transistor is connected to the third node connect;

The seventh pull-down module includes:

A twenty-second transistor, the control terminal of the twenty-second transistor is connected to the first node, the first terminal of the twenty-second transistor receives the pull-down signal, and the first terminal of the twenty-second transistor receives the pull-down signal. The two ends are connected to the fifth node;

A twenty-third transistor, the control terminal of the twenty-third transistor is connected to the first node, the first terminal of the twenty-third transistor receives the pull-down signal, and the first terminal of the twenty-third transistor receives the pull-down signal. The two ends are connected to the sixth node.

In an exemplary embodiment of the present disclosure, wherein:

The fourth pull-down module includes:

A tenth transistor, the control end of the tenth transistor is connected to the fifth node, the first end of the tenth transistor receives the pull-down signal, the second end of the tenth transistor is connected to the first node connect;

An eleventh transistor, the control terminal of the eleventh transistor is connected to the fifth node, the first terminal of the eleventh transistor receives the pull-down signal, the second terminal of the eleventh transistor is connected to the The first output terminal is connected;

The eighth pull-down module includes:

A twenty-fourth transistor, the control end of the twenty-fourth transistor is connected to the second node, the first end of the twenty-fourth transistor receives the pull-down signal, and the first end of the twenty-fourth transistor The two ends are connected to the fourth node;

A twenty-fifth transistor, the control terminal of the twenty-fifth transistor is connected to the second node, the first terminal of the twenty-fifth transistor receives the pull-down signal, and the first terminal of the twenty-fifth transistor receives the pull-down signal. The two terminals are connected with the second output terminal.

In an exemplary embodiment of the present disclosure, wherein:

The first charging module includes:

A twelfth transistor, the control end of the twelfth transistor is connected to the third node, the first end of the twelfth transistor receives the first charging signal, and the second end of the twelfth transistor connected to said second node;

a thirteenth transistor, the control terminal and the first terminal of the thirteenth transistor receive the first charging signal, and the second terminal of the thirteenth transistor is connected to the third node;

The second charging module includes:

A twenty-sixth transistor, the control end of the twenty-sixth transistor is connected to the sixth node, the first end of the twenty-sixth transistor receives the second charging signal, and the twenty-sixth transistor The second end of is connected to the fifth node;

A twenty-seventh transistor, the control terminal and the first terminal of the twenty-seventh transistor receive the second charging signal, and the second terminal of the twenty-seventh transistor is connected to the sixth node.

In an exemplary embodiment of the present disclosure, wherein:

The ninth drop-down module includes:

A fourteenth transistor, the control end of the fourteenth transistor receives the third clock signal, the first end of the fourteenth transistor receives the pull-down signal, the second end of the fourteenth transistor is connected to the The first output terminal is connected;

The tenth pull-down module includes:

The twenty-eighth transistor, the control end of the twenty-eighth transistor receives the fourth clock signal, the first end of the twenty-eighth transistor receives the pull-down signal, and the first end of the twenty-eighth transistor receives the pull-down signal The two terminals are connected with the second output terminal.

In an exemplary embodiment of the present disclosure, the first sequence scan signal controls the shift register unit to scan along the first sequence, and the second sequence scan signal controls the shift register unit to scan along the first sequence. Two sequential scans, the first sequence and the second sequence are in opposite directions.

In an exemplary embodiment of the present disclosure, the first clock signal is partially overlapped with the second clock signal; the third clock signal is partially overlapped with the fourth clock signal.

In an exemplary embodiment of the present disclosure, the transistors are N-channel transistors or both are P-channel transistors.

In an exemplary embodiment of the present disclosure, the transistor is an amorphous silicon transistor, a low temperature polysilicon transistor or an oxide semiconductor transistor.

According to a second aspect of the present disclosure, there is provided a gate drive circuit, including any one of the above shift register units.

In an exemplary embodiment of the present disclosure, the gate drive circuit includes cascaded N shift register units; wherein:

The first input signal in the m+1th stage shift register unit is the signal output by the first output terminal in the mth stage shift register unit;

The second input signal in the m+1th stage shift register unit is the signal output by the second output terminal in the mth stage shift register unit;

The first reset signal in the shift register unit of the mth stage is the signal output by the first output terminal in the shift register unit of the m+1st stage;

The second reset signal in the m-th shift register unit is a signal output from the second output terminal in the m+1-th shift register unit; where 0<m<N.

In an exemplary embodiment of the present disclosure, the gate drive circuit includes cascaded N shift register units; wherein:

The first input signal in the m+1th stage shift register unit is the signal output by the second output terminal in the m-1th stage shift register unit;

The second input signal in the m+1th stage shift register unit is the signal output by the first output terminal in the mth stage shift register unit;

The second reset signal in the m-1th stage shift register unit is the signal output by the first output terminal in the m+1th stage shift register unit;

The first reset signal in the m-th shift register unit is a signal output from the second output terminal in the m+1-th shift register unit; wherein, 1<m<N.

According to a third aspect of the present disclosure, a display device is provided, including any one of the above-mentioned gate driving circuits.

The shift register unit provided in the exemplary embodiment of the present disclosure includes a first shift register unit and a second shift register unit with similar structures, and the first shift register unit and the second shift register unit control each other, Therefore, the first sequential scanning and the second sequential scanning can be better realized. In addition, in the first shift register unit, both the pull-down of the first node and the first output terminal are double-pull-down, and in the second shift register unit, the pull-down of the fourth node and the second output terminal are both double-pull-down, Therefore, the waveform of the gate scan signal output by the shift register unit is more stable. Furthermore, the display effect of the display device can be further improved through the shift register unit provided by the exemplary embodiments of the present disclosure.

Description of drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a shift register unit in an exemplary embodiment of the present invention;

FIG. 2 is a schematic structural diagram of another shift register unit in an exemplary embodiment of the present invention;

3A is a schematic diagram of the driving timing and signal waveform of the shift register unit in FIG. 2;

FIG. 3B is a schematic waveform diagram of a first charging signal and a second charging signal in the shift register unit in FIG. 2;

FIG. 4 is a schematic diagram of an implementation structure of a gate drive circuit in an exemplary embodiment of the present invention;

FIG. 5 is a schematic diagram of another realization structure of a gate driving circuit in an exemplary embodiment of the present invention.

Detailed ways

Exemplary embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments. communicated to those skilled in the art. In the drawings, shapes and dimensions are exaggerated, distorted or simplified for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.

Furthermore, the described features, structures, or steps may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or that other methods, steps, structures, etc. may be employed.

In this example embodiment, a shift register unit is firstly provided. The shift register unit includes a first shift register unit and a second shift register unit, and the first shift register unit and the second shift register unit have similar structures. As shown in Figure 1, the first shift register unit includes a first input module M1, a first output module M2, a first pull-down module M3, a second pull-down module M4, a third pull-down module M5, and a fourth pull-down module M6 And the first charging module M7; the second shift register unit includes a second input module M8, a second output module M9, a fifth pull-down module M10, a sixth pull-down module M11, a seventh pull-down module M12, an eighth pull-down module M13 and The second charging module M14. in:

The first input module M1 may be turned on in response to a first input signal SET1, so as to provide a first sequential scan signal FW to the first node P1, and be turned on in response to a first reset signal RESET1, so as to turn on a first node P1. The two sequential scan signals BW are provided to the first node P1. The first output module M2 can be configured to be turned on in response to the signal of the first node P1 , so as to provide a first clock signal CK1 to the first output terminal GOUT1 . The first pull-down module M3 can be configured to be turned on in response to a signal of a second node P2, so as to provide a pull-down signal VGL to the first node P1 and the first output terminal GOUT1. The second pull-down module M4 can be configured to be turned on in response to the signal of the first node P1, so as to provide the pull-down signal VGL to the second node P2 and a third node P3. The third pull-down module M5 may be turned on in response to a signal of a fourth node P4, so as to provide the pull-down signal VGL to the second node P2 and the third node P3. The fourth pull-down module M6 can be configured to be turned on in response to a signal of a fifth node P5, so as to provide the pull-down signal VGL to the first node P1 and the first output terminal GOUT1. The first charging module M7 can be configured to be turned on in response to the signal of the third node P3, so as to provide a first charging signal V1 to the second node P2.

The second input module M8 may be turned on in response to a second input signal SET2, thereby providing the first sequential scan signal FW to the fourth node P4, and turned on in response to a second reset signal RESET2, thereby The second sequential scan signal BW is supplied to the fourth node P4. The second output module M9 can be configured to be turned on in response to the signal of the fourth node P4, so as to provide a second clock signal CK2 to the second output terminal GOUT2. The fifth pull-down module M10 may be configured to be turned on in response to the signal of the fifth node P5, so as to provide the pull-down signal VGL to the fourth node P4 and the second output terminal GOUT2. The sixth pull-down module M11 may be turned on in response to the signal of the fourth node P4, so as to provide the pull-down signal VGL to the fifth node P5 and a sixth node P6. The seventh pull-down module M12 can be configured to be turned on in response to the signal of the first node P1, so as to provide the pull-down signal VGL to the fifth node P5 and the sixth node P6. The eighth pull-down module M13 can be configured to be turned on in response to the signal of the second node P2, so as to provide the pull-down signal VGL to the fourth node P4 and the second output terminal GOUT2. The second charging module M14 can be configured to be turned on in response to the signal of the sixth node P6, so as to provide a second charging signal V2 to the fifth node P5; in this example implementation, the second charging signal V2 is complementary to the first charging signal V1, that is, when the second charging signal V2 is at a high level, the first charging signal V1 is at a low level; when the second charging signal V2 is at a low level, the first charging signal V1 is at a high level flat.

In the shift register unit provided in this exemplary embodiment, a first shift register unit and a second shift register unit with a similar structure are included, and the first shift register unit and the second shift register unit control each other, so The first sequential scanning and the second sequential scanning can be better realized. In addition, in the first shift register unit, both the pull-down of the first node P1 and the first output terminal GOUT1 are double pull-down, and in the second shift register unit, the pull-down of the fourth node P4 and the second output terminal GOUT2 The pull-down is double pull-down, so the waveform of the gate scan signal output by the shift register unit is more stable. Furthermore, the display effect of the display device can be further improved through the shift register unit in this exemplary embodiment.

Continuing to refer to what is shown in FIG. 1, in order to further improve the stability of the waveform of the output gate scan signal, in this example implementation, the first shift register unit may further include a ninth pull-down module M15, and the second The shift register unit may include a tenth pull-down module M16. Wherein: the ninth pull-down module M15 can be configured to be turned on in response to a third clock signal CK3, so as to provide the pull-down signal VGL to the first output terminal GOUT1; the third clock signal CK3 and the first The clock signal CK1 is complementary, for example, the third clock signal CK3 is an inversion signal of the first clock signal CK1 and the like. The tenth pull-down module M16 can be configured to be turned on in response to a fourth clock signal CK4, so as to provide the pull-down signal VGL to the second output terminal GOUT2; the fourth clock signal CK4 and the second clock signal CK2 is complementary, for example, the fourth clock signal CK4 is an inversion signal of the second clock signal CK2 and the like.

Next, the shift register unit in this exemplary embodiment will be further described by taking the above-mentioned modules mainly composed of transistors as an example. In this example embodiment, each of the transistors includes a first terminal, a second terminal and a control terminal, for example, the first terminal, the second terminal and the control terminal are respectively the source, the drain and the gate of the transistor; or, The first terminal, the second terminal and the control terminal are respectively the drain, the source and the gate of the transistor. The transistors may all be N-channel transistors or all be P-channel transistors. In this exemplary embodiment, the transistors may all be N-channel transistors as an example for description. The transistors may be amorphous silicon transistors, low temperature polysilicon transistors, oxide semiconductor transistors or other types of transistors, which are not specifically limited in this exemplary embodiment.

Please refer to FIG. 1 in conjunction with FIG. 2 . In this exemplary embodiment, the first input module M1 may include a first transistor T1 and a second transistor T2 . Wherein: the control terminal of the first transistor T1 receives the first input signal SET1, the first terminal of the first transistor T1 receives the first sequential scanning signal FW, and the second terminal of the first transistor T1 connected to the first node P1. The second transistor T2, the control end of the second transistor T2 receives the first reset signal RESET1, the first end of the second transistor T2 receives the second sequential scanning signal BW, and the second transistor T2 The second end is connected to the first node P1.

Similar to the first input module M1, the second input module M8 may include a fifteenth transistor T15 and a sixteenth transistor T16. Wherein: the control terminal of the fifteenth transistor T15 receives the second input signal SET2, the first terminal of the fifteenth transistor T15 receives the first sequential scanning signal FW, and the fifteenth transistor T15 The second end is connected to the fourth node P4. The control end of the sixteenth transistor T16 receives the second reset signal RESET2, the first end of the sixteenth transistor T16 receives the second sequential scanning signal BW, and the second end of the sixteenth transistor T16 terminal is connected to the fourth node P4.

Continuing to refer to FIG. 2 , in this exemplary embodiment, the first output module M2 may include a third transistor T3 and a first capacitor C1. Wherein: the control terminal of the third transistor T3 is connected to the first node P1, the first terminal of the third transistor T3 receives the first clock signal CK1, and the second terminal of the third transistor T3 is connected to the first node P1. The first output terminal GOUT1 is connected. The first capacitor C1 is connected between the first node P1 and the first output terminal GOUT1.

Similar to the first output module M2, the second output module M9 may include a seventeenth transistor T17 and a second capacitor C2. Wherein: the control end of the seventeenth transistor T17 is connected to the fourth node P4, the first end of the seventeenth transistor T17 receives the second clock signal CK2, and the first end of the seventeenth transistor T17 The two terminals are connected with the second output terminal GOUT2. The second capacitor C2 is connected between the fourth node P4 and the second output terminal GOUT2.

Continuing to refer to FIG. 2 , in this exemplary embodiment, the first pull-down module M3 may include a fourth transistor T4 and a fifth transistor T5. Wherein: the control terminal of the fourth transistor T4 is connected to the second node P2, the first terminal of the fourth transistor T4 receives the pull-down signal VGL, the second terminal of the fourth transistor T4 is connected to the The first node P1 is connected. The control terminal of the fifth transistor T5 is connected to the second node P2, the first terminal of the fifth transistor T5 receives the pull-down signal VGL, and the second terminal of the fifth transistor T5 is connected to the first node P2. The output terminal GOUT1 is connected.

Similar to the first pull-down module M3, the fifth pull-down module M10 may include an eighteenth transistor T18 and a nineteenth transistor T19. Wherein: the control terminal of the eighteenth transistor T18 is connected to the fifth node P5, the first terminal of the eighteenth transistor T18 receives the pull-down signal VGL, and the second terminal of the eighteenth transistor T18 Connected to the fourth node P4. The control end of the nineteenth transistor T19 is connected to the fifth node P5, the first end of the nineteenth transistor T19 receives the pull-down signal VGL, the second end of the nineteenth transistor T19 is connected to the The second output terminal GOUT2 is connected.

Please continue to combine FIG. 1 and refer to FIG. 2 , in this exemplary embodiment, the second pull-down module M4 may include a sixth transistor T6 and a seventh transistor T7. Wherein: the control terminal of the sixth transistor T6 is connected to the first node P1, the first terminal of the sixth transistor T6 receives the pull-down signal VGL, and the second terminal of the sixth transistor T6 is connected to the The second node P2 is connected. The control terminal of the seventh transistor T7 is connected to the first node P1, the first terminal of the seventh transistor T7 receives the pull-down signal VGL, and the second terminal of the seventh transistor T7 is connected to the third node P1. Node P3 is connected.

Similar to the second pull-down module M4, the sixth pull-down module M11 may include a twentieth transistor T20 and a twenty-first transistor T21. Wherein: the control end of the twentieth transistor T20 is connected to the fourth node P4, the first end of the twentieth transistor T20 receives the pull-down signal VGL, and the second end of the twentieth transistor T20 connected to the fifth node P5. The control end of the twenty-first transistor T21 is connected to the fourth node P4, the first end of the twenty-first transistor T21 receives the pull-down signal VGL, and the second end of the twenty-first transistor T21 terminal is connected to the sixth node P6.

Please continue to combine FIG. 1 and refer to FIG. 2 , in this exemplary embodiment, the third pull-down module M5 may include an eighth transistor T8 and a ninth transistor T9 . Wherein: the control end of the eighth transistor T8 is connected to the fourth node P4, the first end of the eighth transistor T8 receives the pull-down signal VGL, the second end of the eighth transistor T8 is connected to the The second node P2 is connected. The control end of the ninth transistor T9 is connected to the fourth node P4, the first end of the ninth transistor T9 receives the pull-down signal VGL, and the second end of the ninth transistor T9 is connected to the third node P4. Node P3 is connected.

Similar to the third pull-down module M5, the seventh pull-down module M12 may include a twenty-second transistor T22 and a twenty-third transistor T23. Wherein: the control terminal of the twenty-second transistor T22 is connected to the first node P1, the first terminal of the twenty-second transistor T22 receives the pull-down signal VGL, and the control terminal of the twenty-second transistor T22 The second end is connected to the fifth node P5. The control end of the twenty-third transistor T23 is connected to the first node P1, the first end of the twenty-third transistor T23 receives the pull-down signal VGL, and the second end of the twenty-third transistor T23 terminal is connected to the sixth node P6.

Please continue to combine FIG. 1 and refer to FIG. 2 , in this exemplary embodiment, the fourth pull-down module M6 may include a tenth transistor T10 and an eleventh transistor T11 . Wherein: the control terminal of the tenth transistor T10 is connected to the fifth node P5, the first terminal of the tenth transistor T10 receives the pull-down signal VGL, the second terminal of the tenth transistor T10 is connected to the The first node P1 is connected. The control end of the eleventh transistor T11 is connected to the fifth node P5, the first end of the eleventh transistor T11 receives the pull-down signal VGL, the second end of the eleventh transistor T11 is connected to the The first output terminal GOUT1 is connected.

Similar to the fourth pull-down module M6, the eighth pull-down module M13 may include a twenty-fourth transistor T24 and a twenty-fifth transistor T25. Wherein: the control end of the twenty-fourth transistor T24 is connected to the second node P2, the first end of the twenty-fourth transistor T24 receives the pull-down signal VGL, and the twenty-fourth transistor T24 The second end is connected to the fourth node P4. The control end of the twenty-fifth transistor T25 is connected to the second node P2, the first end of the twenty-fifth transistor T25 receives the pull-down signal VGL, and the second end of the twenty-fifth transistor T25 The terminal is connected to the second output terminal GOUT2.

Please continue to combine FIG. 1 and refer to FIG. 2 , in this exemplary embodiment, the first charging module M7 may include a twelfth transistor T12 and a thirteenth transistor T13 . Wherein: the control end of the twelfth transistor T12 is connected to the third node P3, the first end of the twelfth transistor T12 receives the first charging signal V1, and the first end of the twelfth transistor T12 The two ends are connected to the second node P2. The control terminal and the first terminal of the thirteenth transistor T13 receive the first charging signal V1, and the second terminal of the thirteenth transistor T13 is connected to the third node P3.

Similar to the first charging module M7, the second charging module M14 may include a twenty-sixth transistor T26 and a twenty-seventh transistor T27. Wherein: the control end of the twenty-sixth transistor T26 is connected to the sixth node P6, the first end of the twenty-sixth transistor T26 receives the second charging signal V2, and the twenty-sixth transistor T26 The second end of T26 is connected to the fifth node P5. The control terminal and the first terminal of the twenty-seventh transistor T27 receive the second charging signal V2, and the second terminal of the twenty-seventh transistor T27 is connected to the sixth node P6.

Please continue to combine FIG. 1 and refer to FIG. 2 , in this exemplary embodiment, the ninth pull-down module M15 may include a fourteenth transistor T14. Wherein: the control terminal of the fourteenth transistor T14 receives the third clock signal CK3, the first terminal of the fourteenth transistor T14 receives the pull-down signal VGL, and the second terminal of the fourteenth transistor T14 It is connected with the first output terminal GOUT1.

Similar to the ninth pull-down module M15, the tenth pull-down module M16 may include a twenty-eighth transistor T28. Wherein: the control end of the twenty-eighth transistor T28 receives the fourth clock signal CK4, the first end of the twenty-eighth transistor T28 receives the pull-down signal VGL, and the twenty-eighth transistor T28 The second end is connected to the second output end GOUT2.

Please continue to refer to FIG. 2 , and describe the working principle of the shift register unit in this example embodiment in more detail in combination with the driving timing diagram in FIG. 3A . In this example embodiment, the first sequence scan signal FW can control the shift register unit to scan along the first sequence, and the second sequence scan signal BW can control the shift register unit to scan along the second sequence. For scanning, the first sequence and the second sequence are in opposite directions, for example forward scanning and reverse scanning respectively. In forward scanning, the first sequence scanning signal FW is a high level signal, and the second sequence scanning signal BW is a low level signal; in reverse scanning, the first sequence scanning signal FW is a low level signal, and the second The sequential scanning signal BW is a high-level signal; the following will take forward scanning as an example for illustration. Referring to FIG. 3A , in this exemplary embodiment, the phase of the first clock signal CK1 is ahead of the third clock signal CK3 by 1/2 signal period, and the duty ratios of the first clock signal CK1 and the third clock signal CK3 are equal. is 1/2, the first clock signal CK1 is complementary to the third clock signal CK3. The phase of the second clock signal CK2 is ahead of the fourth clock signal CK4 by 1/2 signal period, the duty ratios of the second clock signal CK2 and the fourth clock signal CK4 are both 1/2, the second clock signal CK2 and the fourth clock signal Signal CK4 is complementary. The first clock signal CK1 is partially overlapped with the second clock signal CK2 , for example, the phase of the first clock signal CK1 is ahead of the second clock signal CK2 by 1/4 signal period. The third clock signal CK3 partially overlaps with the fourth clock signal CK4, for example, the phase of the third clock signal CK3 is ahead of the fourth clock signal CK4 by 1/4 signal period. In this exemplary embodiment, in the first stage t1 to the fifth stage t5 in the figure, the first charging signal V1 is, for example, at a low level, and the second charging signal V2 is, for example, at a high level. Referring to FIG. 3B , in this exemplary embodiment, the phase of the first charging signal V1 is ahead of the second charging signal V2 by 1/2 signal period, and the duty ratios of the first charging signal V1 and the second charging signal V2 are both 1/2, the signal periods of the first charging signal V1 and the second charging signal V2 may both be 2 seconds, for example. Taking the first shift register unit in the shift register unit as an example, its working process may include the following stages:

Please continue to refer to FIG. 2 and FIG. 3A in combination. In the first stage t1, the first input signal SET1 is at a high level (in this example implementation, starting with both the first input signal SET1 and the second input signal SET2 Signal STV as an example), the first clock signal CK1, the third clock signal CK3 and the first reset signal RESET1 are all at low level; the first transistor T1 is turned on. The high-level first sequential scan signal FW is input to the first node P1 through the first transistor T1 to charge the first capacitor C1. Since the voltage of the first node P1 is at a high level, the third transistor T3 , the sixth transistor T6 , the seventh transistor T7 , the twenty-second transistor T22 and the twenty-third transistor T23 are turned on. The pull-down signal VGL is input to the second node P2 through the sixth transistor T6, so that the second node P2 is at a low level. The pull-down signal VGL is input to the third node P3 through the seventh transistor T7, so that the third node P3 is at a low level. The pull-down signal VGL is input to the fifth node P5 through the twenty-second transistor T22, so that the fifth node P5 is at a low level. The pull-down signal VGL is input to the sixth node P6 through the twenty-third transistor T23, so that the sixth node P6 is at a low level (in this exemplary embodiment, the absolute value of the voltage of the pull-down signal VGL is greater than that of the second charging signal absolute value of V2). In addition, in the stage t1, the voltage of the fourth node P4 is at a high level, so that the eighth transistor T8 and the ninth transistor T9 are turned on. The pull-down signal VGL is input to the second node P2 through the eighth transistor T8, so that the level of the second node P2 is further pulled down. The pull-down signal VGL is input to the third node P3 through the ninth transistor T9, so that the level of the ninth node is further pulled down. The first clock signal CK1 is output from the first output terminal GOUT1 through the third transistor T3. Since the first clock signal CK1 is at low level in the t1 stage, the output of the first shift register unit in the shift register unit is low. flat signal.

3A, in the second stage t2, the first clock signal CK1 is high level, the first input signal SET1, the third clock signal CK3 and the first reset signal RESET1 are all low level, the first transistor T1 off. Under the action of the high-level voltage signal stored in the first capacitor C1, the voltage of the first node P1 is still at a high level, so that the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the twenty-second transistor T22 And the twenty-third transistor T23 remains turned on. The pull-down signal VGL is input to the second node P2 through the sixth transistor T6, so that the second node P2 is at a low level. The pull-down signal VGL is input to the third node P3 through the seventh transistor T7, so that the third node P3 is at a low level. The pull-down signal VGL is input to the fifth node P5 through the twenty-second transistor T22, so that the fifth node P5 is at a low level. The pull-down signal VGL is input to the sixth node P6 through the twenty-third transistor T23, so that the sixth node P6 is at a low level. In addition, in the stage t2, the voltage of the fourth node P4 is at a high level, so that the eighth transistor T8 and the ninth transistor T9 are turned on. The pull-down signal VGL is input to the second node P2 through the eighth transistor T8, so that the level of the second node P2 is further pulled down. The pull-down signal VGL is input to the third node P3 through the ninth transistor T9, so that the level of the ninth node is further pulled down. The first clock signal CK1 is output from the first output terminal GOUT1 through the third transistor T3. Since the first clock signal CK1 is at a high level at the stage t2, the output of the shift register unit is a high level signal.

3A, in the third stage t3, the third clock signal CK3 and the first reset signal RESET1 are both high level, the first input signal SET1 and the first clock signal CK1 are both low level, and the second transistor T2 and the fourteenth transistor T14 are turned on. The low-level first reset signal RESET1 is input to the first node P1 through the second transistor T2 to reset the first capacitor C1. Since the voltage of the first node P1 is at a low level, the third transistor T3 , the sixth transistor T6 , the seventh transistor T7 , the twenty-second transistor T22 and the twenty-third transistor T23 are turned off. In addition, in the second half of the period t3 , the voltage of the fourth node P4 is at a low level, so that the eighth transistor T8 , the ninth transistor T9 and the twenty-first transistor T21 are turned off. Since the second charging signal V2 is at a high level, the twenty-seventh transistor T27 is turned on, and the second charging signal V2 is input to the sixth node P6; after the twenty-first transistor T21 and the twenty-third transistor T23 are turned off, The voltage of the sixth node P6 is the second charging signal V2, so the sixth node P6 is at a high level, and the twenty-sixth transistor T26 is turned on. The high level second charging signal V2 is input to the fifth node P5 through the twenty-sixth transistor T26, so that the fifth node P5 is at a high level. Since the voltage of the fifth node P5 is at a high level, the tenth transistor T10 and the eleventh transistor T11 are turned on. The pull-down signal VGL is input to the first node P1 through the tenth transistor T10, so that the level of the first node P1 is further pulled down. The pull-down signal VGL is input to the signal output terminal through the fourteenth transistor T14, so the output of the shift register unit is a low level signal. The pull-down signal VGL is input to the first output terminal GOUT1 through the eleventh transistor T11, so that the level of the first output terminal GOUT1 is further pulled down, thereby making the output of the shift register unit more stable.

In the above exemplary embodiments, the second charging signal V2 is at a high level and the first charging signal V1 is at a low level, but the situation when the second charging signal V2 is at a low level and the first charging signal V1 is at a high level is the same as This is similar. For example, since the first charging signal V1 is at a high level, the thirteenth transistor T13 is turned on, and the first charging signal V1 is input to the third node P3; after the seventh transistor T7 and the ninth transistor T9 are turned off, the thirteenth transistor T13 The voltage of the three nodes P3 is the first charging signal V1, so the third node P3 is at a high level, and the twelfth transistor T12 is turned on. The high level first charging signal V1 is input to the second node P2 through the twelfth transistor T12, so that the second node P2 is at a high level. Since the voltage of the second node P2 is at a high level, the fourth transistor T4 , the fifth transistor T5 , the twenty-fourth transistor T24 and the twenty-fifth transistor T25 are turned on. The pull-down signal VGL is input to the first node P1 through the fourth transistor T4, so that the level of the first node P1 is further pulled down. The pull-down signal VGL is input to the first output terminal GOUT1 through the fifth transistor T5, so that the level of the first output terminal GOUT1 is further pulled down, thereby making the output of the shift register unit more stable.

Referring to FIG. 3A , during the period from t4 to t5 following the third period t3 , under the action of the second charging signal V2 , the fifth node P5 remains at a high level. Since the voltage of the fifth node P5 is at a high level, the tenth transistor T10 and the eleventh transistor T11 are kept turned on. The pull-down signal VGL is input to the first node P1 through the tenth transistor T10 to keep the level of the first node P1 at a low level. The pull-down signal VGL is input to the signal output terminal through the eleventh transistor T11, so the output of the shift register unit is a low level signal. Moreover, when the third clock signal CK3 is at a high level, the fourteenth transistor T14 is turned on, and the pull-down signal VGL is input to the first output terminal GOUT1 through the fourteenth transistor T14, so that the level of the first output terminal GOUT1 is controlled by Pulling down further makes the output of the shift register unit more stable.

The working sequence of the second shift register unit in the shift register unit is similar to that of the first shift register unit, so it will not be repeated here. In addition, in the above exemplary embodiments, the forward scanning is taken as an example for illustration, but during the reverse scanning, the working sequence of the shift register unit is similar to that of the forward scanning, so it will not be repeated here.

Another advantage of the above-mentioned shift register unit is that it uses a single channel type of transistors, that is, all N-type thin film transistors. Using a uniform type of thin film transistors can reduce the complexity of the manufacturing process and production costs, and help improve product quality. Of course, those skilled in the art can easily find that the shift register unit provided by the present invention can be easily changed into all P-type transistors; wherein, when each of the transistors is a P-type transistor, the levels of the above-mentioned signals It only needs to be adjusted adaptively, so it is not limited to the implementation manner provided in this example embodiment.

Further, this exemplary embodiment also provides a gate driving circuit, which includes any one of the above-mentioned shift register units. For example:

Referring to FIG. 4, the gate drive circuit in this example embodiment may include a first shift register unit SR1, a second shift register unit SR2, a third shift register unit SR3, and a fourth shift register unit SR4, etc. N shift register units (more shift register units are not shown), wherein G1-G8 represent gate lines electrically connected to each shift register unit. In this exemplary embodiment, the first input signal SET1 in the shift register unit of the m+1st stage is the signal output by the first output terminal GOUT1 in the shift register unit of the mth stage (shift register unit of the first stage The first input signal SET1 in is the start signal STV); the second input signal SET2 in the m+1th stage shift register unit is the output of the second output terminal GOUT2 in the mth stage shift register unit signal (the second input signal SET2 in the first stage shift register unit is the start signal STV); the first reset signal RESET1 in the mth stage shift register unit is the m+1 stage shift register unit The signal output by the first output terminal GOUT1 (the first reset signal RESET1 in the last stage shift register unit is the reset signal RST); the second reset signal RESET2 in the mth stage shift register unit is the mth + the signal output by the second output terminal GOUT2 in the shift register unit of the first stage (the second reset signal RESET2 in the shift register unit of the last stage is the reset signal RST2); wherein, 0<m<N. That is, as shown in the figure, the first input signal SET1 in the third-stage shift register unit is the signal output by the first output terminal GOUT1 in the second-stage shift register unit; The second input signal SET2 is the signal output by the second output terminal GOUT2 in the second-stage shift register unit; the first reset signal RESET1 in the second-stage shift register unit is the third-stage shift register unit The signal output by the first output terminal GOUT1 in the above; the second reset signal RESET2 in the second-stage shift register unit is the signal output by the second output terminal GOUT2 in the third-stage shift register unit, and so on.

Referring to FIG. 5 , the gate drive circuit in this exemplary embodiment may include a first shift register unit SR1, a second shift register unit SR2, a third shift register unit SR3, a fourth shift register unit SR4, N shift register units such as the fifth shift register unit SR5 and the sixth shift register unit SR6 (other more shift register units are not shown), wherein G1～G12 represent the shift register units electrically connected gate line. In this exemplary embodiment, the first input signal SET1 in the shift register unit of the m+1st stage is the signal output by the second output terminal GOUT2 in the shift register unit of the m-1th stage (the first stage and the first stage The first input signal SET1 in the 2-stage shift register unit is the start signal STV); the second input signal SET2 in the m+1-stage shift register unit is the m-stage shift register unit The signal output by the first output terminal GOUT1 (the second input signal SET2 in the first stage shift register unit is the start signal STV); the second reset signal RESET2 in the m-1th stage shift register unit is the first signal STV The signal output by the first output terminal GOUT1 in the m+1 stage shift register unit (the second reset signal RESET2 in the penultimate stage and the last stage shift register unit is the reset signal RST); the mth stage The first reset signal RESET1 in the shift register unit is the signal output by the second output terminal GOUT2 in the m+1th stage shift register unit (the first reset signal RESET1 in the last stage shift register unit is reset signal RST); wherein, 1<m<N. That is, as shown in the figure, the first input signal SET1 in the fourth-stage shift register unit is the signal output by the second output terminal GOUT2 in the second-stage shift register unit; The second input signal SET2 is the signal output by the first output terminal GOUT1 in the third-stage shift register unit; the second reset signal RESET2 in the second-stage shift register unit is the fourth-stage shift register unit The signal output by the first output terminal GOUT1 in the above; the first reset signal RESET1 in the third-stage shift register unit is the signal output by the second output terminal GOUT2 in the fourth-stage shift register unit, and so on.

Those skilled in the art can easily understand that the gate drive circuits in FIG. 4 and FIG. 5 are only exemplary; in other exemplary embodiments of the present disclosure, any shift register unit described above in this exemplary embodiment is included The gate drive circuit can also be connected in other ways, which is not specifically limited in this exemplary embodiment.

Further, this exemplary embodiment also provides a display device, which includes any one of the above-mentioned gate driving circuits. In this exemplary embodiment, the display device may be a liquid crystal display device or an OLED display device, and in other exemplary embodiments of the present disclosure, the display device may also be a PLED (Polymer Light-Emitting Diode, polymer light-emitting diode) display devices, PDP (Plasma Display Panel, Plasma Display) display devices and other flat panel display devices, that is, the scope of application of this exemplary embodiment is not particularly limited.

In summary, in the shift register unit provided in this example embodiment, it includes a first shift register unit and a second shift register unit with similar structures, and the first shift register unit and the second shift register The units control each other, so that the first and second sequential scans can be better implemented. In addition, in the first shift register unit, both the pull-down of the first node and the first output terminal are double-pull-down, and in the second shift register unit, the pull-down of the fourth node and the second output terminal are both double-pull-down, Therefore, the waveform of the gate scan signal output by the shift register unit is more stable. Furthermore, the display effect of the display device can be further improved through the shift register unit in this exemplary embodiment.

The present disclosure has been described by the above-mentioned related embodiments, but the above-mentioned embodiments are only examples for implementing the present disclosure. It must be pointed out that the disclosed embodiments do not limit the scope of the present disclosure. On the contrary, changes and modifications made without departing from the spirit and scope of the present disclosure all belong to the patent protection scope of the present disclosure.

Claims (18)

1. A shift register unit, characterized in that, comprising: The first input module is used to provide a first sequential scan signal to the first node in response to a first input signal, and provide a second sequential scan signal to the first node in response to a first reset signal; a first output module, configured to provide a first clock signal to a first output terminal in response to a signal of the first node; The first pull-down module is configured to provide a pull-down signal to the first node and the first output terminal in response to a signal of a second node; a second pull-down module, configured to provide the pull-down signal to the second node and a third node in response to the signal of the first node; a third pull-down module, configured to provide the pull-down signal to the second node and the third node in response to a signal of a fourth node; a fourth pull-down module, configured to provide the pull-down signal to the first node and the first output terminal in response to a signal of a fifth node; a first charging module, configured to provide a first charging signal to the second node in response to a signal from the third node; A second input module, configured to provide the first sequential scan signal to the fourth node in response to a second input signal, and provide the second sequential scan signal to the fourth node in response to a second reset signal ; a second output module, configured to provide a second clock signal to the second output terminal in response to the signal of the fourth node; a fifth pull-down module, configured to provide the pull-down signal to the fourth node and the second output terminal in response to the signal of the fifth node; a sixth pull-down module, configured to provide the pull-down signal to the fifth node and a sixth node in response to the signal of the fourth node; a seventh pull-down module, configured to provide the pull-down signal to the fifth node and the sixth node in response to the signal of the first node; an eighth pull-down module, configured to provide the pull-down signal to the fourth node and the second output terminal in response to the signal of the second node; The second charging module is configured to provide a second charging signal to the fifth node in response to the signal of the sixth node, the second charging signal is complementary to the first charging signal. 2. shift register unit according to claim 1, is characterized in that, described shift register unit also comprises: A ninth pull-down module, configured to provide the pull-down signal to the first output terminal in response to a third clock signal; the third clock signal is complementary to the first clock signal; The tenth pull-down module is configured to provide the pull-down signal to the second output terminal in response to a fourth clock signal; the fourth clock signal is complementary to the second clock signal. 3. The shift register unit according to claim 2, wherein: The first input module includes: A first transistor, the control terminal of the first transistor receives the first input signal, the first terminal of the first transistor receives the first sequential scanning signal, the second terminal of the first transistor is connected to the first node connection; A second transistor, the control terminal of the second transistor receives the first reset signal, the first terminal of the second transistor receives the second sequential scan signal, the second terminal of the second transistor is connected to the first node connection; The second input module includes: A fifteenth transistor, the control end of the fifteenth transistor receives the second input signal, the first end of the fifteenth transistor receives the first sequential scan signal, and the second of the fifteenth transistor connected to the fourth node; The sixteenth transistor, the control end of the sixteenth transistor receives the second reset signal, the first end of the sixteenth transistor receives the second sequential scan signal, the second of the sixteenth transistor connected to the fourth node. 4. The shift register unit according to claim 2, wherein: The first output module includes: a third transistor, the control terminal of the third transistor is connected to the first node, the first terminal of the third transistor receives the first clock signal, and the second terminal of the third transistor is connected to the first node an output connection; a first capacitor connected between the first node and the first output terminal; The second output module includes: A seventeenth transistor, the control end of the seventeenth transistor is connected to the fourth node, the first end of the seventeenth transistor receives the second clock signal, and the second end of the seventeenth transistor connected to the second output terminal; The second capacitor is connected between the fourth node and the second output terminal. 5. The shift register unit according to claim 2, wherein: The first pull-down module includes: A fourth transistor, the control end of the fourth transistor is connected to the second node, the first end of the fourth transistor receives the pull-down signal, the second end of the fourth transistor is connected to the first node connect; a fifth transistor, the control terminal of the fifth transistor is connected to the second node, the first terminal of the fifth transistor receives the pull-down signal, and the second terminal of the fifth transistor is connected to the first output terminal connection; The fifth pull-down module includes: An eighteenth transistor, the control end of the eighteenth transistor is connected to the fifth node, the first end of the eighteenth transistor receives the pull-down signal, the second end of the eighteenth transistor is connected to the The fourth node is connected; A nineteenth transistor, the control end of the nineteenth transistor is connected to the fifth node, the first end of the nineteenth transistor receives the pull-down signal, the second end of the nineteenth transistor is connected to the connected to the second output terminal. 6. The shift register unit according to claim 2, wherein: The second pull-down module includes: A sixth transistor, the control terminal of the sixth transistor is connected to the first node, the first terminal of the sixth transistor receives the pull-down signal, and the second terminal of the sixth transistor is connected to the second node connect; A seventh transistor, the control end of the seventh transistor is connected to the first node, the first end of the seventh transistor receives the pull-down signal, the second end of the seventh transistor is connected to the third node connect; The sixth drop-down module includes: A twentieth transistor, the control end of the twentieth transistor is connected to the fourth node, the first end of the twentieth transistor receives the pull-down signal, and the second end of the twentieth transistor is connected to the fourth node. The fifth node is connected; A twenty-first transistor, the control terminal of the twenty-first transistor is connected to the fourth node, the first terminal of the twenty-first transistor receives the pull-down signal, and the first terminal of the twenty-first transistor receives the pull-down signal. The two ends are connected to the sixth node. 7. The shift register unit according to claim 2, wherein: The third pull-down module includes: An eighth transistor, the control end of the eighth transistor is connected to the fourth node, the first end of the eighth transistor receives the pull-down signal, the second end of the eighth transistor is connected to the second node connect; A ninth transistor, the control end of the ninth transistor is connected to the fourth node, the first end of the ninth transistor receives the pull-down signal, the second end of the ninth transistor is connected to the third node connect; The seventh pull-down module includes: A twenty-second transistor, the control terminal of the twenty-second transistor is connected to the first node, the first terminal of the twenty-second transistor receives the pull-down signal, and the first terminal of the twenty-second transistor receives the pull-down signal. The two ends are connected to the fifth node; A twenty-third transistor, the control terminal of the twenty-third transistor is connected to the first node, the first terminal of the twenty-third transistor receives the pull-down signal, and the first terminal of the twenty-third transistor receives the pull-down signal. The two ends are connected to the sixth node. 8. The shift register unit according to claim 2, wherein: The fourth pull-down module includes: A tenth transistor, the control end of the tenth transistor is connected to the fifth node, the first end of the tenth transistor receives the pull-down signal, the second end of the tenth transistor is connected to the first node connect; An eleventh transistor, the control terminal of the eleventh transistor is connected to the fifth node, the first terminal of the eleventh transistor receives the pull-down signal, the second terminal of the eleventh transistor is connected to the The first output terminal is connected; The eighth pull-down module includes: A twenty-fourth transistor, the control end of the twenty-fourth transistor is connected to the second node, the first end of the twenty-fourth transistor receives the pull-down signal, and the first end of the twenty-fourth transistor The two ends are connected to the fourth node; A twenty-fifth transistor, the control terminal of the twenty-fifth transistor is connected to the second node, the first terminal of the twenty-fifth transistor receives the pull-down signal, and the first terminal of the twenty-fifth transistor receives the pull-down signal. The two terminals are connected with the second output terminal. 9. The shift register unit according to claim 2, wherein: The first charging module includes: A twelfth transistor, the control end of the twelfth transistor is connected to the third node, the first end of the twelfth transistor receives the first charging signal, and the second end of the twelfth transistor connected to said second node; a thirteenth transistor, the control terminal and the first terminal of the thirteenth transistor receive the first charging signal, and the second terminal of the thirteenth transistor is connected to the third node; The second charging module includes: A twenty-sixth transistor, the control end of the twenty-sixth transistor is connected to the sixth node, the first end of the twenty-sixth transistor receives the second charging signal, and the twenty-sixth transistor The second end of is connected to the fifth node; A twenty-seventh transistor, the control terminal and the first terminal of the twenty-seventh transistor receive the second charging signal, and the second terminal of the twenty-seventh transistor is connected to the sixth node. 10. The shift register unit according to claim 2, wherein: The ninth drop-down module includes: A fourteenth transistor, the control end of the fourteenth transistor receives the third clock signal, the first end of the fourteenth transistor receives the pull-down signal, the second end of the fourteenth transistor is connected to the The first output terminal is connected; The tenth pull-down module includes: The twenty-eighth transistor, the control end of the twenty-eighth transistor receives the fourth clock signal, the first end of the twenty-eighth transistor receives the pull-down signal, and the first end of the twenty-eighth transistor receives the pull-down signal The two terminals are connected with the second output terminal. 11. The shift register unit according to any one of claims 1 to 10, wherein the first sequence scanning signal controls the shift register unit to scan along the first sequence, and the second sequence scans A signal controls the shift register cells to scan along a second sequence, the first sequence being opposite to the second sequence. 12. The shift register unit according to any one of claims 2 to 10, wherein the first clock signal partially overlaps with the second clock signal; the third clock signal overlaps with the fourth clock signal The clock signals partially overlap. 13. The shift register unit according to any one of claims 3-10, wherein the transistors are N-channel transistors or all are P-channel transistors. 14. The shift register unit according to any one of claims 3-10, wherein the transistor is an amorphous silicon transistor, a low temperature polysilicon transistor or an oxide semiconductor transistor. 15. A gate drive circuit, characterized by comprising the shift register unit according to any one of claims 1-14. 16. The gate drive circuit according to claim 15, wherein the gate drive circuit comprises N shift register units cascaded; wherein: The first input signal in the m+1th stage shift register unit is the signal output by the first output terminal in the mth stage shift register unit; The second input signal in the m+1th stage shift register unit is the signal output by the second output terminal in the mth stage shift register unit; The first reset signal in the shift register unit of the mth stage is the signal output by the first output terminal in the shift register unit of the m+1st stage; The second reset signal in the m-th shift register unit is a signal output from the second output terminal in the m+1-th shift register unit; where 0<m<N. 17. The gate drive circuit according to claim 15, wherein the gate drive circuit comprises N shift register units cascaded; wherein: The first input signal in the m+1th stage shift register unit is the signal output by the second output terminal in the m-1th stage shift register unit; The second input signal in the m+1th stage shift register unit is the signal output by the first output terminal in the mth stage shift register unit; The second reset signal in the m-1th stage shift register unit is the signal output by the first output terminal in the m+1th stage shift register unit; The first reset signal in the shift register unit of the mth stage is a signal output from the second output terminal of the shift register unit in the m+1st stage; wherein, 1<m<N. 18. A display device, comprising the gate driving circuit according to any one of claims 15-17.