CN106128347B - Shift register cell and its driving method, gate driving circuit, display device - Google Patents

Shift register cell and its driving method, gate driving circuit, display device Download PDF

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Publication number
CN106128347B
CN106128347B CN201610551812.4A CN201610551812A CN106128347B CN 106128347 B CN106128347 B CN 106128347B CN 201610551812 A CN201610551812 A CN 201610551812A CN 106128347 B CN106128347 B CN 106128347B
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China
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pull
node
control
signal
module
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CN201610551812.4A
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Chinese (zh)
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CN106128347A (en
Inventor
古宏刚
邵贤杰
宋洁
李磊
许徐飞
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to CN201610551812.4A priority Critical patent/CN106128347B/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using semiconductor elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit

Abstract

A kind of shift register cell of offer of the embodiment of the present invention and its driving method, gate driving circuit, display device, it is related to display technology field, so that touch scanning signals are not interfere with each other with gated sweep signal, and the gated sweep signal for avoiding shift register cell from exporting is pulled low or no signal output.The shift register cell includes that the first input module exports the signal at first voltage end to pull-up node;Second input module exports the signal at second voltage end to pull-up node;Pull-up module exports the signal of the first clock signal input terminal to signal output end;Pull-down control module exports the signal of the first clock signal input terminal, second clock signal input part or tertiary voltage end to pull-down node.The current potential of signal output end is pulled down to tertiary voltage end by touch-control pull-down module;Charging module exports the signal of touching signals control terminal to pull-up node;The current potential of pull-up node and signal output end is pulled down to tertiary voltage end by noise reduction module respectively.

Description

Shift register cell and its driving method, gate driving circuit, display device

Technical field

The present invention relates to display technology fields more particularly to a kind of shift register cell and its driving method, grid to drive Dynamic circuit, display device.

Background technology

(Thin Film Transistor Liquid Crystal Display, Thin Film Transistors-LCD are aobvious by TFT-LCD Show device) or OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) display in be provided with array Substrate, wherein array substrate can be divided into display area and the wiring area positioned at display area periphery.Wherein neighboring area Inside it is provided with the gate driving circuit for being progressively scanned to grid line.Existing gate driving circuit is frequently with GOA (Gate Driver on Array, the driving of array substrate row) it designs TFT (Thin Film Transistor, thin film field-effect crystal Pipe) gate switch circuit is integrated in above-mentioned neighboring area, to form gate driving circuit.

In addition as the continuous development of touch-control (Touch) technology, aforementioned display device include touch screen, which can be divided into External hanging type with it is embedded, the panel with touch function can be located in the light emission side of display by external hanging type, and cover display The visible area of device.Embedded is will have touch function to be integrated on the display panel (Panel) of display.

Above-mentioned gate driving circuit includes multiple cascade shift register cells, in the prior art, in order to avoid touch-control The gated sweep signal that scanning signal exports during inputting with the defeated shift register cell of GOA circuits clashes, usually When touch scanning signals input, the output end for controlling shift register cell is needed to be exported to grid line no signal.When touch-control is swept After retouching signal input, the output end of shift register cell continues to be scanned grid line.However, due to shift register cell In thin film transistor (TFT) there are leakage current so that after touch scanning signals input, the output end of shift register cell after It is continuous that the gated sweep signal of shift register cell output is pulled low or no signal output when being scanned to grid line, to Influence the normal display of display.

Invention content

A kind of shift register cell of the embodiment of the present invention offer and its driving method, gate driving circuit, display dress It sets, while enabling to touch scanning signals not interfere with each other with gated sweep signal, after touching signals end of input, avoids TFT electric leakage cause the gated sweep signal of GOA circuit outputs be pulled low or no signal output.

In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that:

The one side of the embodiment of the present invention provides a kind of shift register cell, including the first input module, the second input Module, pull-up module, pull-down control module, touch-control pull-down module, charging module, noise reduction module;First input module connects The first signal input part, first voltage end and pull-up node are connect, is used under the control of first signal input part, by institute The signal for stating first voltage end is exported to the pull-up node;The second input module connection second signal input terminal, second Voltage end and the pull-up node are used under the control of second signal input terminal, and the signal at the second voltage end is defeated Go out to the pull-up node;The pull-up module connect first clock signal input terminal, signal output end and it is described on Node is drawn, under the control of the pull-up node, the first clock signal of first clock signal input terminal to be exported To the signal output end, and the current potential of the pull-up node is stored;The pull-down control module connects the pull-up Node, first clock signal input terminal, second clock signal input part, tertiary voltage end and pull-down node are used for The first clock signal of first clock signal input terminal is exported to institute under the control of first clock signal input terminal State pull-down node;Or under the control of the second clock signal input part by the second clock signal input part Second clock signal is exported to the pull-down node;Or under the control of the pull-up node by the pull-down node Current potential is pulled down to the current potential at the tertiary voltage end;The touch-control pull-down module connects the signal output end, touching signals control End processed and the tertiary voltage end are used under the control of the touching signals control terminal, by the electricity of the signal output end Position is pulled down to the current potential at the tertiary voltage end;The charging module connects the touching signals control terminal and pull-up section Point, under the control at the pull-up node and touching signals end, the signal of the touching signals control terminal to be exported to institute State pull-up node;The noise reduction module connects the pull-down node, the pull-up node, signal output end and third electricity Pressure side, under the control of the pull-down node, respectively pulling down the current potential of the pull-up node and the signal output end To the current potential at the tertiary voltage end.

Preferably, first input module includes the first transistor, the grid of the first transistor connection described the One signal input part, the first pole connect the first voltage end, and the second pole is connected with the pull-up node.

Preferably, second input module includes second transistor, the grid of second transistor connection described the Binary signal input terminal, the first pole connect the second voltage end, and the second pole is connected with the pull-up node.

Preferably, the pull-up module includes third transistor and the first capacitance;The grid of the third transistor connects The pull-up node, the first pole connect first clock signal input terminal, and the second pole is connected with the signal output end;Institute The one end for stating the first capacitance is connected with the pull-up node, and the other end connects the signal output end.

Preferably, the pull-down control module includes the 4th transistor, the 5th transistor and the second capacitance;4th transistor Grid and the first pole connect first clock signal input terminal, the second pole is connected with the pull-down node;Described 5th The grid of transistor connects the pull-up node, and the first pole connects the pull-down node, the second pole and tertiary voltage end phase Connection;One end of second capacitance connects the second clock signal input part, and the other end is connected with the pull-down node.

Preferably, the touch-control pull-down module includes the 6th transistor, the grid connection touch-control letter of the 6th transistor Number control terminal, the first pole connect the signal output end.

Preferably, the charging module includes the 7th transistor and the 8th transistor;The grid of 7th transistor and First pole connects the touching signals control terminal, and the second pole connects the first pole of the 8th transistor;8th transistor Grid and the second pole connect the pull-up node.

Preferably, the charging module includes the 7th transistor and the 8th transistor;The grid of 7th transistor connects Pull-up node is connect, the first pole connects the touching signals control terminal, and the second pole is connected with the grid of the 8th transistor;Institute The first pole for stating the 8th transistor connects the touching signals control terminal, and the second pole is connected with the pull-up node.

Preferably, the noise reduction module includes the 9th transistor and the tenth transistor;The grid of 9th transistor connects The pull-down node is connect, the first pole connects the pull-up node, and the second pole is connected with the tertiary voltage end;Described tenth is brilliant The grid of body pipe connects the pull-down node, and the first pole connects the signal output end, the second pole and tertiary voltage end phase Connection.

The another aspect of the embodiment of the present invention provides a kind of gate driving circuit, including multiple cascade as described above Any one shift register cell, the first signal input part connection initial signal end of first order shift register cell;It removes Other than first order shift register cell, the signal output end of upper level shift register cell connects next stage shift LD First signal input part of device unit;Other than afterbody shift register cell, next stage shift register cell Second signal input terminal connects the signal output end of upper level shift register cell;The of afterbody shift register cell Binary signal input terminal connects the initial signal end.

The another aspect of the embodiment of the present invention provides a kind of display device, including gate driving circuit as described above.

The embodiment of the present invention in another aspect, provide a kind of driving method, including in a picture frame, the method packet It includes:Input phase:Under the control of the first signal input part, the first input module exports the signal at first voltage end to pull-up Node;Pull-up module stores the current potential of the pull-up node, and under the control of the pull-up node, the upper drawing-die Block exports the signal of the first clock signal input terminal to signal output end;The output stage:It will be deposited on last stage in pull-up module The signal of storage is exported to the pull-up node, and under the control of the pull-up node, the pull-up module is by first clock First clock signal of signal input part is exported to the signal output end, and the signal output end exports gated sweep signal; Reseting stage:Pull-down control module is under the control of the second clock signal input part and the pull-up node, by described The second clock signal of two clock signal input terminals is exported to pull-down node;Under the control of the pull-down node, the noise reduction The voltage of the pull-up node and the signal output end is pulled down to the current potential at the tertiary voltage end by module;Second input mould The current potential of pull-up node is pulled down to the current potential at the second voltage end by block under the control of second signal input terminal;Noise reduction is protected Hold the stage:The pull-down control module, will be described under the control of first clock signal input terminal and the pull-up node First clock signal of the first clock signal input terminal is exported to pull-down node;Under the control of the pull-down node, the drop The voltage of the pull-up node and the signal output end is pulled down to the current potential at the tertiary voltage end by module of making an uproar;In next figure The first signal input part of stage, second signal input terminal, first are kept as repeating the reseting stage and the noise reduction before frame The control signal of clock signal input terminal and second clock signal input part so that the signal output end keeps no signal defeated The state gone out;Touching signals input phase:Touch-control pull-down module exports the signal under the control of touching signals control terminal The current potential at end is pulled down to the current potential at the tertiary voltage end.

Preferably, the touching signals input phase is inserted between adjacent two field pictures frame.

Preferably, the output stage in a picture frame is inserted into the touching signals input phase, in the input phase, institute Stating driving method further includes:Charging module touches under the control of the pull-up node and the touching signals control terminal by described The signal of control signal control terminal is exported to pull-up node, and is stored to the current potential of the pull-up node by pull-up module.

Preferably, it when the transistor in the shift register cell is N-type transistor, is inputted at first voltage end High level, in the case of the input low level of tertiary voltage end, the method includes:The input phase:First signal is defeated Enter and hold input high level, first input module is under the control of the high level of first signal input part by described first The high level output of voltage end is to pull-up node;The output stage:Under the control of the pull-up node high level, it is described on Drawing-die block is by the high level output of first clock signal input terminal to the signal output end;The reseting stage:It is described The high level output of second clock signal input part is to the pull-down node, under the control of the pull-down node, the noise reduction The voltage of the pull-up node and the signal output end is pulled down to the low level at the tertiary voltage end by module;Described second Signal input part input high level, second input module is under the control for the high level that the second signal input terminal inputs The current potential of pull-up node is pulled down to the low level at the second voltage end;The noise reduction is kept for the stage:The first clock letter The high level output of number input terminal is to the pull-down node, and under the control of the pull-down node, the noise reduction module will be described The voltage of pull-up node and the signal output end is pulled down to the low level at the tertiary voltage end;The touching signals input rank Section:Touching signals control terminal exports high level, the high level that the touch-control pull-down module is exported in the touching signals control terminal Control under the current potential of the signal output end is pulled down to the low level at the tertiary voltage end.

Preferably, when the transistor in the shift register cell is N-type transistor, the touching signals input Stage:The touching signals control terminal exports high level, and the pull-up node exports high level, and the charging module is touched described The high level output of signal control terminal is controlled to the pull-up node

A kind of shift register cell of offer of the embodiment of the present invention and its driving method, gate driving circuit, display device. The shift register cell includes the first input module, the second input module, pull-up module, pull-down control module, touch-control drop-down Module, charging module, noise reduction module.Wherein, the first input module connects the first signal input part, first voltage end and pull-up Node, under the control of the first signal input part, the signal at first voltage end to be exported to pull-up node.Second input mould Block connects second signal input terminal, second voltage end and pull-up node, under the control of second signal input terminal, by the The signal of two voltage ends is exported to pull-up node.Pull-up module connect the first clock signal input terminal, signal output end and on Node is drawn, under the control of pull-up node, the first clock signal of the first clock signal input terminal being exported defeated to signal Outlet, and the current potential of pull-up node is stored.Pull-down control module connect pull-up node, the first clock signal input terminal, Second clock signal input part, tertiary voltage end and pull-down node, for the control in first clock signal input terminal Lower the first clock signal by first clock signal input terminal is exported to the pull-down node;Or for described second The second clock signal of the second clock signal input part is exported to the drop-down under the control of clock signal input terminal and is saved Point;Or the electricity for the current potential of the pull-down node to be pulled down to the tertiary voltage end under the control of the pull-up node Position.Touch-control pull-down module connection signal output end, touching signals control terminal and tertiary voltage end, for being controlled in touching signals Under the control at end, the current potential of signal output end is pulled down to the current potential at tertiary voltage end.Charging module connects touching signals control End and pull-up node, under the control of pull-up node, the signal of touching signals control terminal to be exported to pull-up node.Noise reduction Module connects pull-down node, pull-up node, signal output end and tertiary voltage end, under the control of pull-down node, dividing The current potential of pull-up node and signal output end is not pulled down to the current potential at tertiary voltage end.

So, on the one hand, can be by the voltage output of the first signal input part to pull-up by pulling up control module Node, in addition, the second input module can be supreme by the voltage output at second voltage end under the control of second signal input terminal Draw node.In the case, when the shift register cell uses forward scan, the voltage at first voltage end is used for pull-up Node charges, and the voltage at second voltage end is worked as the shift register cell and used for being resetted to pull-up node When reverse scan, for charging to pull-up node, the voltage at first voltage end is used for pull-up the voltage at second voltage end Node is resetted.

Based on this, after pull-up node is electrically charged, pull-up module, can be by the first clock under the control of the pull-up node First clock signal of signal input part is exported to signal output end so that signal output end output the stage can pair with should The grid line that signal output end is connected exports gated sweep signal, in addition, pull-down control module can control the electricity of pull-down node Position, so that the pull-down node can control noise reduction module is pulled down to tertiary voltage by the current potential of pull-up node and signal output end The current potential at end, with the carry out noise reduction to pull-up node and signal output end.

On the other hand, in the output stage of the shift register cell, when touch-control pull-down module can be defeated in touching signals It is fashionable, the current potential of signal output end is pulled down to the current potential at tertiary voltage end, to avoid touching signals defeated with signal output end The gated sweep signal gone out interferes with each other.In addition, charging module can by the voltage output of touching signals control terminal to pull up section Point, to charge to pull-up node so that after touching signals end of input, the current potential of pull-up node can be maintained, from And avoid the problem that the TFT in shift register cell the current potential for leaking electricity and leading to pull-up node occurs and reduces, so that letter Number output end keeps output gated sweep signal in the above-mentioned output stage.

Description of the drawings

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with Obtain other attached drawings according to these attached drawings.

Fig. 1 is a kind of structural schematic diagram of shift register cell provided in an embodiment of the present invention;

Fig. 2 is a kind of concrete structure schematic diagram of modules in Fig. 1;

Fig. 3 is another concrete structure schematic diagram of modules in Fig. 1;

A kind of signal timing diagram of Fig. 4 shift register cells shown in Fig. 2 or 3 in order to control;

Another signal timing diagram of Fig. 5 shift register cells shown in Fig. 2 or 3 in order to control;

Fig. 6 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention.

Reference numeral:

The first input modules of 10-;The second input modules of 20-;30- pull-up modules;40- pull-down control modules;Under 50- touch-controls Drawing-die block;60- charging modules;70- noise reduction modules;The first signal input parts of IN1-;IN2- second signal input terminals;CLK- first Clock signal input terminal;CLKB- second clock signal input parts;OUTPUT- signal output ends;V1- first voltages end;V2- Two voltage ends;V3- tertiary voltages end.

Specific implementation mode

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.

The embodiment of the present invention provides a kind of shift register cell, as shown in Figure 1, including the first input module 10, second Input module 20, pull-up module 30, pull-down control module 40, touch-control pull-down module 50, charging module 60, noise reduction module 70.

Wherein, the first input module 10 connects the first signal input part IN1, first voltage end V1 and pull-up node PU, For under the control of the first signal input part IN1, the signal of first voltage end V1 to be exported to pull-up node PU.

Second input module 20 connects second signal input terminal IN2, second voltage end V2 and pull-up node PU, is used for Under the control of second signal input terminal IN2, the signal of second voltage end V2 is exported to pull-up node PU.

Pull-up module 30 connects the first clock signal input terminal CLK, signal output end OUTPUT and pull-up node PU, uses Under the control in pull-up node PU, the first clock signal of the first clock signal input terminal CLK is exported to signal output end OUTPUT, and the current potential of pull-up node PU is stored.

Pull-down control module 40 connects pull-up node PU, the first clock signal input terminal CLK, second clock signal input part CLKB, tertiary voltage end V3 and pull-down node PD are used for the first clock under the control of the first clock signal input terminal CLK The first clock signal of signal input part CLK is exported to pull-down node PD.Alternatively, in second clock signal input part CLK Control under, the second clock signal of second clock signal input part CLKB is exported to pull-down node PD.Alternatively, being used for Under the control for drawing node PU, the current potential of pull-down node PD is pulled down to the current potential of tertiary voltage end V3.

50 connection signal output end OUTPUT of touch-control pull-down module, touching signals control terminal SW and tertiary voltage end V3, For under the control of touching signals control terminal SW, the current potential of signal output end OUTPUT to be pulled down to the electricity of tertiary voltage end V3 Position.

Charging module 60 connects touching signals control terminal SW and pull-up node PU, in pull-up node PU and touching signals Under the control for holding SW, the signal of touching signals control terminal SW is exported to pull-up node PU.

Noise reduction module 70 connects pull-down node PD, pull-up node PU, signal output end OUTPUT and tertiary voltage end V3, For under the control of pull-down node PD, the current potential of pull-up node PU and signal output end OUTPUT to be pulled down to third electricity respectively The current potential of pressure side V3.

So, on the one hand, can be by the voltage output of the first signal input part to pull-up by pulling up control module Node, in addition, the second input module can be supreme by the voltage output at second voltage end under the control of second signal input terminal Draw node.In the case, when the shift register cell uses forward scan, the voltage at first voltage end is used for pull-up Node charges, and the voltage at second voltage end is worked as the shift register cell and used for being resetted to pull-up node When reverse scan, for charging to pull-up node, the voltage at first voltage end is used for pull-up the voltage at second voltage end Node is resetted.

Based on this, after pull-up node is electrically charged, pull-up module, can be by the first clock under the control of the pull-up node First clock signal of signal input part is exported to signal output end so that signal output end output the stage can pair with should The grid line that signal output end is connected exports gated sweep signal, in addition, pull-down control module can control the electricity of pull-down node Position, so that the pull-down node can control noise reduction module is pulled down to tertiary voltage by the current potential of pull-up node and signal output end The current potential at end, with the carry out noise reduction to pull-up node and signal output end.

On the other hand, in the output stage of the shift register cell, when touch-control pull-down module can be defeated in touching signals It is fashionable, the current potential of signal output end is pulled down to the current potential at tertiary voltage end, to avoid touching signals defeated with signal output end The gated sweep signal gone out interferes with each other.In addition, charging module can by the voltage output of touching signals control terminal to pull up section Point, to charge to pull-up node so that after touching signals end of input, the current potential of pull-up node can be maintained, from And avoid the problem that the TFT in shift register cell the current potential for leaking electricity and leading to pull-up node occurs and reduces, so that letter Number output end keeps output gated sweep signal in the above-mentioned output stage.

The concrete structure of modules in Fig. 1 is described in detail below.

Specifically, above-mentioned first input module 10 includes the first transistor M1.The grid connection the of the first transistor M1 One signal input part IN1, the first pole connect first voltage end V1, and the second pole is connected with pull-up node PU.

Second input module 20 includes second transistor M2, and the grid of second transistor M2 connects second signal input terminal IN2, the first pole connect second voltage end V2, and the second pole is connected with pull-up node PU.

Pull-up module 30 may include third transistor M3 and the first capacitance C1.

Wherein, the grid of third transistor M3 connects pull-up node PU, and the first pole connects the first clock signal input terminal CLK, the second pole are connected with signal output end OUTPUT.

One end of first capacitance C1 is connected with pull-up node PU, other end connection signal output end OUTPUT.

Pull-down control module 40 includes the 4th transistor M4, the 5th transistor M5 and the second capacitance C2.

The grid of 4th transistor M4 and the first pole connect the first clock signal input terminal CLK, the second pole and pull-down node PD is connected.

The grid of 5th transistor M5 connects pull-up node PU, and the first pole connects pull-down node PD, the second pole and third electricity Pressure side V3 is connected.

One end of second capacitance C2 connects second clock signal input part CLKB, and the other end is connected with pull-down node PD.

Touch-control pull-down module 50 includes the 6th transistor M6, and the grid of the 6th transistor M6 connects touching signals control terminal SW, the first pole connection signal output end OUTPUT.

Charging module 60 includes the 7th transistor M7 and the 8th transistor M8.

Wherein, as shown in Fig. 2, the grid of the 7th transistor M7 and the first pole connect touching signals control terminal SW, the second pole Connect the first pole of the 8th transistor M8.The grid of 8th transistor M8 and the second pole connection pull-up node PU.

Alternatively, when charging module 60 includes the 7th transistor M7 and the 8th transistor M8, the 7th transistor M7 and the 8th The connection type of transistor M8 can be with as shown in figure 3, the grid of the 7th transistor M7 connects pull-up node PU, the connection of the first pole be touched Signal control terminal SW is controlled, the second pole is connected with the grid of the 8th transistor M8.The first pole of 8th transistor M8 connects touch-control Signal control terminal SW, the second pole are connected with pull-up node PU.

In addition, noise reduction module 70 includes the 9th transistor M9 and the tenth transistor M10.

Wherein, the grid of the 9th transistor M9 connects pull-down node PD, and the first pole connects pull-up node PU, the second pole and the Three voltage end V3 are connected.

The grid of tenth transistor M10 connects pull-down node PD, the first pole connection signal output end OUTPUT, the second pole with Tertiary voltage end V3 is connected.

It should be noted that above-mentioned transistor can be N-type transistor, or P-type transistor;Can be enhanced Transistor, or depletion mode transistor;The first of above-mentioned transistor extremely can be source electrode, and second extremely can be drain electrode, or The first of the above-mentioned transistor of person can be extremely drain electrode, and the second extremely source electrode, this is not limited by the present invention.

Below by taking above-mentioned transistor is N-type transistor as an example, and combine Fig. 4 or Fig. 5 to shifting as shown in Figures 2 and 3 Each transistor in bit register unit, in the different stages an of picture frame (such as U frames, U >=1, U are positive integer) The break-make situation of (P1~P4) carries out detailed illustration.Wherein, it is constant with first voltage end V1 in the embodiment of the present invention The explanation carried out for output high level, second voltage end V2 and V3 constant output low levels.In addition, following explanation is with first Signal input part IN1 receives input signal INPUT, and second signal input terminal IN2 is received for reset signal RESET.

When no touching signals input, above-mentioned touching signals control terminal SW input low levels, the 6th transistor M6, the 7th crystalline substance Body pipe M7 and the 8th transistor M8 are in cut-off state.

In the case, input phase P1, INPUT=1, RESET=0, CLK=0, CLKB=1;Wherein " 0 " indicates low Level, " 1 " indicate high level.

At this point, since the first signal input part IN1 exports high level, the first transistor M1 conductings, thus by first The high level output of voltage end V1 stores the high level to pull-up node PU, and by the first capacitance C1.It is saved in pull-up Under the control of point PU, third transistor M3 conductings, by the low level of the first clock signal input terminal CLK to signal output end OUTPUT。

Under the control of pull-up node PU high potentials, the 5th transistor M5 conductings.Therefore, even if second clock signal inputs CLKB is held to export high level, the current potential of pull-down node PD can also be pulled down to the low electricity of tertiary voltage end V3 by the 5th transistor M5 It is flat.In the case, the 9th transistor M9 and the tenth transistor M10 are in cut-off state.

In addition, the first clock signal input terminal CLK input low levels so that the 4th transistor M4 cut-offs, second signal are defeated Enter to hold IN2 input low levels so that second transistor M2 cut-offs.

In conclusion signal output end OUTPUT exports low level in above-mentioned input phase P1.

Output stage P2, INPUT=0, RESET=0, CLK=1, CLKB=0;

At this point, since the first signal input part IN1 exports low level, the first transistor M1 is in cut-off state.The One capacitance C1 charges to pull-up node PU the high level that input phase P1 is stored, so that third transistor M3 is kept Open state.In the case, the high level of the first clock signal input terminal CLK is exported defeated to signal by third transistor M3 Outlet OUTPUT.In addition, under bootstrapping (Bootstrapping) effect of the first capacitance C1, the current potential of pull-up node PU is into one Step increases, with the state for maintaining third transistor M3 to be on, so that the high level of the first clock signal input terminal CLK It can be exported as gated sweep signal to the grid line being connected with signal output end OUTPUT.

In addition, under the control of pull-up node PU high potentials, the 5th transistor M5 conductings, therefore, even if the first clock is believed The high level of number input terminal CLK inputs passes through the 4th transistor M4 conductings, the high level of first clock signal input terminal CLK 4th transistor M4 is exported to pull-down node, and the current potential of pull-down node PD still can be pulled down to third by the 5th transistor M5 The low level of voltage end V3.In the case, the 9th transistor M9 and the tenth transistor M10 are in cut-off state.

In addition, second signal input terminal IN2 input low levels so that second transistor M2 cut-offs.

In conclusion signal output end OUTPUT above-mentioned output stage P2 export high level, with to signal output end The grid line that OUTPUT is connected exports gated sweep signal.

Reseting stage P3, INPUT=0, RESET=1, CLK=0, CLKB=1;

At this point, since second signal input terminal IN2 exports high level, second transistor M2 conductings, thus by pull-up node The current potential of PU is pulled down to the low level of second voltage end V2, to be resetted to pull-up node PU, third transistor M3, the 5th crystalline substance Body pipe is in cut-off state.

Due to the first clock signal input terminal CLK input low levels, so that the 4th transistor M4 is in cut-off state. And second clock signal input part CLKB input high levels, under the boot strap of the second capacitance C2, the current potential of pull-down node PD It is increased to high level, to which by the 9th transistor M9 and the tenth transistor M10 conductings, the 9th will be passed through by the 9th transistor M9 The current potential of pull-up node PU is pulled down to the low level of tertiary voltage end V3 by transistor M9, to be resetted to pull-up node PU, And the current potential of signal output end OUTPUT is pulled down to the low level of tertiary voltage end V3 by the tenth transistor M10, with to letter Number output end OUTPUT is resetted.

In addition, third transistor M3 is connected second clock signal input part CLKB output high level, and second clock is believed Number input terminal CLKB output high level is transmitted to the grid of the 4th transistor M4, the 4th transistor by third transistor M3 M4 is connected so that second clock signal input part CLKB output high level is transmitted to pull-down node PD, and passes through the second capacitance C2 Above-mentioned high level is stored.

In addition, the first signal input part IN1 input low levels, second transistor M2 cut-offs.

Noise reduction keeps stage P4, INPUT=0, RESET=0, CLK=1, CLKB=0;

At this point, the first clock signal input terminal CLK input high levels, by the 4th transistor M4 conductings, so that first The high level output of clock signal input terminal CLK is to pull-down node, under the control of pull-down node PD, by the 9th transistor M9 With the tenth transistor M10 conductings, the current potential of pull-up node PU will be pulled down by the 9th transistor M9 by the 9th transistor M9 To the low level of tertiary voltage end V3, to carry out noise reduction to pull-up node PU, and by the tenth transistor M10 by signal output end The current potential of OUTPUT is pulled down to the low level of tertiary voltage end V3, to carry out noise reduction to signal output end OUTPUT.

In addition, in this stage other than the 9th transistor M9 and the tenth transistor M10 conductings, remaining transistor is in Cut-off state.

Next, can repeat reseting stage P3's and noise reduction holding stage P4 before next image frame (U+1 frames) First signal input part IN1, second signal input terminal IN2, the first clock signal input terminal CLK and the input of second clock signal The control signal for holding CLKB, to carry out continuing noise reduction to signal output end OUTPUT.

When there is touching signals input, as shown in figure 4, touching signals can be inserted between two adjacent picture frames, example Touching signals input phase P5 is inserted into such as between U frames and U+1 frames, to input touch-control in touching signals input phase P5 Signal.Alternatively, the scan frequency when grid line in display panel increases, it, can be with as shown in figure 5, in a figure when being greater than 60HZ It is inserted into above-mentioned touching signals input phase P5 in input phase P2 as insertion in frame, such as in a picture frame, with tactile at this It controls signal input phase P5 and inputs touching signals.

It should be noted that when above-mentioned touching signals input phase P5 is inserted between two adjacent picture frames, Huo Zhe When the stage is inserted into other than input phase P2 in one picture frame, although above-mentioned signal output end OUTPUT is inputted in touching signals Stage P5 is inserted into the state for being in the output of non-grid scanning signal at the moment, but in order to avoid due to signal output end OUTPUT The signal of output generates fluctuation to be interfered to touching signals, the shape that the 6th transistor M6 in Fig. 2 or Fig. 3 is on State, so as to which the current potential of signal output end OUTPUT to be pulled down to the low level of tertiary voltage end V3 so that signal output end OUTPUT avoids signal fluctuation from being interfered caused by touching signals in touching signals input phase P5.

In addition, when above-mentioned touching signals input phase P5 is as shown in figure 5, be inserted into the input phase in a picture frame P2, in order to avoid signal output end OUTPUT is interfered with each other in input phase P2 output gated sweep signals with touching signals, Fig. 2 Or the 6th transistor M6 conductings in Fig. 3, the current potential of signal output end OUTPUT can be pulled down to the low of tertiary voltage end V3 Level so that signal output end OUTPUT avoids output gated sweep signal in touching signals input phase P5, to solve grid The problem of scanning signal can be interfered with each other with touching signals.

On this basis, the 7th transistor M7 in Fig. 2 or Fig. 3 and the 8th transistor M8 are in input phase P2 The state of conducting, so as to by the high level output of touching signals control terminal SW to pull-up node PU, with to pull-up node PU It charges so that after touching signals end of input (i.e. after touching signals input phase P5), the current potential of pull-up node PU It can be maintained, to avoid such as the tenth transistors 10 of the TFT in shift register cell and the 9th transistor M9 from occurring The phenomenon that leaking electricity and the current potential of pull-up node PU caused to reduce so that signal output end OUTPUT is kept in above-mentioned output stage P2 Export gated sweep signal.

It should be noted that the switching process of transistor is to be as N-type transistor using all transistors in above-described embodiment What example illustrated, when all transistors are p-type, need to overturn each control signal in Fig. 4 or Fig. 5, and move The make and break process of the transistor of modules is same as above in bit register unit, and details are not described herein again.

In addition, the course of work of above-mentioned shift register cell, is constituted with above-mentioned multiple shift register cell cascades Gate driving circuit by the way of forward scan for the explanation that carries out.When using reverse scan, in Fig. 2 and Fig. 3 institutes In the shift register cell shown, the first signal input part IN1 can be received reset signal RESET, second signal input terminal IN2 receives input signal INPUT.In addition, above-mentioned first voltage end V1 input low levels, second voltage end V2 input high levels are It can.

The embodiment of the present invention provides a kind of gate driving circuit, as shown in fig. 6, including multiple cascade as described above Any one shift register cell (RS1, RS2 ... RSn).

The first signal input part IN1 connection initial signal end STV of first order shift register cell RS1, in addition to first Other than grade shift register cell RS1, the signal output end OUTPUT and next stage of upper level shift register cell RS (n-1) The first signal input part IN1 of shift register cell RS (n) is connected.Wherein, initial signal end STV is for exporting starting letter Number, the first order shift register cell RS1 of the gate driving circuit starts after receiving above-mentioned initial signal to grid line (G1, G2 ... Gn) is progressively scanned.

In addition, other than afterbody shift register cell RSn, the second signal of next stage shift register cell The signal output end OUTPUT of input terminal IN2 connection upper level shift register cells.Afterbody shift register cell RSn The above-mentioned initial signal end STV of second signal input terminal IN2 connections.So, when the initial signal of initial signal end STV is defeated When entering the first signal input part IN1 of first order shift register cell RS1, the of afterbody shift register cell RSn Binary signal input terminal IN2 can be using the initial signal of initial signal end STV as reset signal to afterbody shift register The signal output end OUTPUT of unit R Sn is resetted.

It should be noted that in order to enable the first clock signal input terminal CLK of each shift register cell and The signal frequency of waveform, the amplitude as shown in Fig. 4 or Fig. 5 of two clock signal input terminal CLKB outputs are identical, opposite in phase.It can be with As shown in fig. 6, the first clock signal input terminal CLK on different shift register cells and second clock signal input part CLKB Replace connection with the first system clock signal input terminal CLK1 and second system clock signal input terminal CLK2 respectively.

For example, the first clock signal input terminal CLK connection the first system clocks letter of first order shift register cell RS1 Number input terminal CLK1, second clock signal input part CLKB connection second system clock signal input terminals CLK2;The second level shifts The first clock signal input terminal CLK connection second system clock signal input terminal CLK2 of register cell RS2, second clock letter Number input terminal CLKB connection the first system clock signal input terminals CLK3.The connection type of following shift register cell is same as above institute It states.

On this basis, per the first voltage end V1 connection high level VDD of level-one shift register cell, second voltage end V1 connection low level VSS, tertiary voltage end V3 connection low levels VGL.

In addition, the connection side of gate driving circuit shown in fig. 6 each control signal when being to grid line progress forward scan Method.When carrying out reverse scan to grid line using the gate driving circuit,

The second signal input terminal IN2 connection initial signal end STV of first order shift register cell RS1, in addition to first Other than grade shift register cell RS1, the signal output end OUTPUT and next stage of upper level shift register cell RS (n-1) The second signal input terminal IN2 of shift register cell RS (n) is connected.In addition to afterbody shift register cell RSn with Outside, the signal output of the first signal input part IN1 connection upper level shift register cells of next stage shift register cell Hold OUTPUT.The first above-mentioned initial signal end STV of signal input part IN1 connections of afterbody shift register cell RSn.

On this basis, per the first voltage end V1 connection low level VSS of level-one shift register cell, second voltage end V1 connection high level VDD, tertiary voltage end V3 connection low levels VGL.

The embodiment of the present invention provides a kind of display device, including any one gate driving circuit as described above, has Structure identical with the gate driving circuit that previous embodiment provides and advantageous effect.Since previous embodiment drives grid The structure and advantageous effect of dynamic circuit are described in detail, and details are not described herein again.

The embodiment of the present invention provides a kind of method for driving any one of the above shift register cell, specifically exists In one picture frame, the method includes:

Such as Fig. 4 or shown in fig. 5 input phases P1:

Under the control of the first signal input part IN1, the first input module 10 by the signal of first voltage end V1 export to Pull-up node PU.Pull-up module 30 stores the current potential of pull-up node PU, and under the control of pull-up node PU, upper drawing-die Block 30 exports the signal of the first clock signal input terminal CLK to signal output end OUTPUT.

In addition, pull-down control module 40 is under the control of second clock signal input part CLKB and pull-up node PU, will under The current potential of node PD is drawn to be pulled down to tertiary voltage end V3.In addition, the second input module 20 and noise reduction module 70 are not opened.

When modules in above-mentioned shift register cell structure as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, in input phase P1, the first clock signal input terminal CLK inputs low electricity It is flat, second clock signal input part CKLB input high levels, the first signal input part IN1 input high levels, second signal input It is high level to hold IN2 input low levels, pull-up node PU, and pull-down node PD is low level, and signal output end OUTPUT outputs are low Level.

Based on this, the first signal input part IN1 input high levels, the first input module 10 is in first signal input part High level control under by the high level output of first voltage end V1 to pull-up node PU.Specifically, in input phase P1 In in above-mentioned modules the break-make situation of transistor be:Since the first signal input part IN1 exports high level, first is brilliant The M1 conductings of body pipe, thus by the high level output of first voltage end V1 to pull-up node PU, and by the first capacitance C1 to the height Level is stored.Under the control of pull-up node PU, third transistor M3 conductings, by the first clock signal input terminal CLK's Low level is to signal output end OUTPUT.

Under the control of pull-up node PU high potentials, the 5th transistor M5 conductings.Therefore, even if second clock signal inputs CLKB is held to export high level, the current potential of pull-down node PD can also be pulled down to the low electricity of tertiary voltage end V3 by the 5th transistor M5 It is flat.In the case, the 9th transistor M9 and the tenth transistor M10 are in cut-off state.

In addition, the first clock signal input terminal CLK input low levels so that the 4th transistor M4 cut-offs, second signal are defeated Enter to hold IN2 input low levels so that second transistor M2 cut-offs.

In output stage P2:

The signal stored on last stage is exported to pull-up node PU in pull-up module 30, in the control of pull-up node PU Under, pull-up module 30 exports the first clock signal of the first clock signal input terminal CLK to signal output end OUTPUT, the letter Number output end OUTPUT exports gated sweep signal.

In addition, pull-down control module 40 is under the control of second clock signal input part CLKB and pull-up node PU, will under The current potential of node PD is drawn to be pulled down to tertiary voltage end V3.In addition, at this stage, the first input module 10, the second input module 20 It is not opened with noise reduction module 70.

When modules in above-mentioned shift register cell structure as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, in output stage P2, the first high electricity of clock signal input terminal CLK inputs It is flat, second clock signal input part CLKB input low levels, the first signal input part IN1 input low levels, second signal input Hold IN2 input low levels;Pull-up node PU is high level, and pull-down node PD is low level, and signal output end OUTPUT outputs are high Level.

Based on this, under the control of pull-up node PU high level, pull-up module 30 is by the first clock signal input terminal CLK's High level output is to signal output end OUTPUT.Specifically, in output stage P2 in above-mentioned modules transistor it is logical Disconnected situation is:Since the first signal input part IN1 exports low level, the first transistor M1 is in cut-off state.First electricity Hold C1 the high level that input phase P1 is stored charges to pull-up node PU, so that third transistor M3 is kept it turning on State.In the case, the high level of the first clock signal input terminal CLK is exported by third transistor M3 to signal output end OUTPUT.In addition, under bootstrapping (Bootstrapping) effect of the first capacitance C1, the current potential of pull-up node PU further rises Height, with the state for maintaining third transistor M3 to be on, so that the high level of the first clock signal input terminal CLK can It is exported to the grid line being connected with signal output end OUTPUT as gated sweep signal.

In addition, under the control of pull-up node PU high potentials, the 5th transistor M5 conductings, therefore, even if the first clock is believed The high level of number input terminal CLK inputs passes through the 4th transistor M4 conductings, the high level of first clock signal input terminal CLK 4th transistor M4 is exported to pull-down node, and the current potential of pull-down node PD still can be pulled down to third by the 5th transistor M5 The low level of voltage end V3.In the case, the 9th transistor M9 and the tenth transistor M10 are in cut-off state.

In addition, second signal input terminal IN2 input low levels so that second transistor M2 cut-offs.

Reseting stage P3:

Pull-down control module 40 is under the control of second clock signal input part CLKB and pull-up node PU, by second clock The second clock signal of signal input part CLKB is exported to pull-down node PD.Under the control of pull-down node PD, noise reduction module 70 are pulled down to the voltage of pull-up node PU and signal output end OUTPUT the current potential of tertiary voltage end V3.Second input module 20 Under the control of second signal input terminal IN2, the current potential of pull-up node PU is pulled down to the current potential of second voltage end V2.

In addition, at this stage, the first input module 20, pull-up module 30 and pull-down control module 40 are not opened.

When modules in above-mentioned shift register cell structure as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, in reseting stage P3, the first clock signal input terminal CLK inputs low electricity It is flat, second clock signal input part CLKB input high levels, the first signal input part IN1 input low levels, second signal input Hold IN2 input high levels;Pull-up node PU is low level, and pull-down node PD is high level, and signal output end OUTPUT outputs are low Level.

Based on this, the high level output of second clock signal input part CLKB is to pull-down node PD, pull-down node PD's Under control, the voltage of pull-up node PU and signal output end OUTPUT are pulled down to the low electricity of tertiary voltage end V3 by noise reduction module 70 It is flat.The current potential of pull-up node PU is pulled down to the second electricity by second signal input terminal CLKB input high levels, the second input module 20 The low level of pressure side V2.Specifically, the break-make situation of transistor is in above-mentioned modules in reseting stage P3:Due to Binary signal input terminal IN2 exports high level, second transistor M2 conductings, to which the current potential of pull-up node PU is pulled down to the second electricity The low level of pressure side V2, to be resetted to pull-up node PU, third transistor M3, the 5th transistor are in cut-off state.

Due to the first clock signal input terminal CLK input low levels, so that the 4th transistor M4 is in cut-off state. And second clock signal input part CLKB input high levels, under the boot strap of the second capacitance C2, the current potential of pull-down node PD It is increased to high level, to which by the 9th transistor M9 and the tenth transistor M10 conductings, the 9th will be passed through by the 9th transistor M9 The current potential of pull-up node PU is pulled down to the low level of tertiary voltage end V3 by transistor M9, to be resetted to pull-up node PU, And the current potential of signal output end OUTPUT is pulled down to the low level of tertiary voltage end V3 by the tenth transistor M10, with to letter Number output end OUTPUT is resetted.

In addition, third transistor M3 is connected second clock signal input part CLKB output high level, and second clock is believed Number input terminal CLKB output high level is transmitted to the grid of the 4th transistor M4, the 4th transistor by third transistor M3 M4 is connected so that second clock signal input part CLKB output high level is transmitted to pull-down node PD, and passes through the second capacitance C2 Above-mentioned high level is stored.

In addition, the first signal input part IN1 input low levels, second transistor M2 cut-offs.

Noise reduction keeps stage P4:

Pull-down control module 40 is under the control of the first clock signal input terminal CLK and pull-up node PU, by the first clock The first clock signal of signal input part CLK is exported to pull-down node PD.Under the control of pull-down node PD, noise reduction module 70 will The voltage of pull-up node PU and signal output end OUTPUT are pulled down to the current potential of tertiary voltage end V3.

Next, repeating the first of reseting stage P3 and noise reduction holding stage P4 before next image frame (U+1 frames) Signal input part IN1, second signal input terminal IN2, the first clock signal input terminal CLK and second clock signal input part The control signal of CLKB so that signal output end OUTPUT keeps the state of no signal output.

When modules in above-mentioned shift register cell structure as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, stage P4, the first high electricity of clock signal input terminal CLK inputs are kept in noise reduction It is flat, second clock signal input part CLKB input low levels, the first signal input part IN1 input low levels, second signal input Hold IN2 input low levels;Pull-up node PU is low level, and pull-down node PD is high level, and signal output end OUTPUT outputs are low Level.

Based on this, the high level output of the first clock signal input terminal CLK is to pull-down node PD, in the control of pull-down node PD Under system, the voltage of pull-up node PU and signal output end OUTPUT are pulled down to the low electricity of tertiary voltage end V3 by noise reduction module 70 It is flat.Specifically, the break-make situation of transistor is in above-mentioned modules in noise reduction holding stage P4:First clock signal is defeated Enter to hold CLK input high levels, by the 4th transistor M4 conductings, so that the high level of the first clock signal input terminal CLK is defeated Go out to pull-down node, under the control of pull-down node PD, by the 9th transistor M9 and the tenth transistor M10 conductings, by the The current potential of pull-up node PU will be pulled down to the low level of tertiary voltage end V3 by nine transistor M9 by the 9th transistor M9, with right Pull-up node PU carries out noise reduction, and the current potential of signal output end OUTPUT is pulled down to tertiary voltage by the tenth transistor M10 The low level for holding V3, to carry out noise reduction to signal output end OUTPUT.

In addition, in this stage other than the 9th transistor M9 and the tenth transistor M10 conductings, remaining transistor is in Cut-off state.

Further, when there is touching signals input, above-mentioned driving method is also believed such as Fig. 4 or shown in fig. 5 including touch-control Number input phase P5, touch-control pull-down module 50 is under the control of touching signals control terminal SW in the stage, by signal output end The current potential of OUTPUT is pulled down to the current potential of tertiary voltage end V3.

When modules in above-mentioned shift register cell structure as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, in touching signals input phase P5, touching signals control terminal 50 inputs high electricity It is flat;The signal output end exports low level.

Based on this, touching signals control terminal SW exports high level, and touch-control pull-down module 50 is by signal output end OUTPUT's Current potential is pulled down to the low level of tertiary voltage end V3.Specifically, the touch-control pull-down module 50 in touching signals input phase P5 In the states that are on of the 6th transistor M6, so as to which the current potential of signal output end OUTPUT is pulled down to tertiary voltage Hold the low level of V3 so that signal output end OUTPUT avoids signal fluctuation from making touching signals in touching signals input phase P5 At interference.

It should be noted that as shown in figure 4, touching signals can be inserted between two adjacent picture frames, adjacent two Above-mentioned touching signals input phase P5 is inserted between frame picture frame, such as between U frames and U+1 frames.

Alternatively, when there is touching signals input, as shown in figure 5, the output stage in a picture frame (such as U frames) inserts Enter touching signals input phase P5, which further includes:

Charging module 60 is under the control of pull-up node PU and touching signals control terminal SW, by touching signals control terminal SW's Signal is exported to pull-up node PU, and is stored to the current potential of pull-up node PU by pull-up module 30.

When modules in above-mentioned shift register cell structure as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, in touching signals input phase P5, touching signals control terminal 50 inputs high electricity It is flat;Pull-up node PU is high level, and pull-down node PD is low level, and signal output end OUTPUT exports low level.

Based on this, touching signals control terminal SW exports high level, and pull-up node PU exports high level, and charging module 60 will touch The high level output of signal control terminal SW is controlled to pull-up node PU.Specifically, above-mentioned each in touching signals input phase P5 The break-make situation of transistor is in a module:The 6th transistor M6 conductings in Fig. 2 or Fig. 3, can be by signal output end The current potential of OUTPUT is pulled down to the low level of tertiary voltage end V3 so that signal output end OUTPUT is in touching signals input phase P5 avoids output gated sweep signal, to solve the problems, such as that gated sweep signal can be interfered with each other with touching signals.

On this basis, the 7th transistor M7 in Fig. 2 or Fig. 3 and the 8th transistor M8 are in input phase P2 The state of conducting, so as to by the high level output of touching signals control terminal SW to pull-up node PU, with to pull-up node PU It charges so that after touching signals end of input (i.e. after touching signals input phase P5), the current potential of pull-up node PU It can be maintained, to avoid such as the tenth transistors 10 of the TFT in shift register cell and the 9th transistor M9 from occurring The phenomenon that leaking electricity and the current potential of pull-up node PU caused to reduce so that signal output end OUTPUT is kept in above-mentioned output stage P2 Export gated sweep signal.

The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims (16)

1. a kind of shift register cell, which is characterized in that including the first input module, the second input module, pull-up module, under Draw control module, touch-control pull-down module, charging module, noise reduction module;
First input module connects the first signal input part, first voltage end and pull-up node, for described first Under the control of signal input part, the signal at the first voltage end is exported to the pull-up node;
The second input module connection second signal input terminal, second voltage end and the pull-up node, for second Under the control of signal input part, the signal at the second voltage end is exported to the pull-up node;
The pull-up module connects the first clock signal input terminal, signal output end and the pull-up node, for described Under the control of pull-up node, the first clock signal of first clock signal input terminal is exported to the signal output end, And the current potential of the pull-up node is stored;
The pull-down control module connects the pull-up node, first clock signal input terminal, the input of second clock signal End, tertiary voltage end and pull-down node are used for first clock under the control of first clock signal input terminal First clock signal of signal input part is exported to the pull-down node;Or in the second clock signal input part The second clock signal of the second clock signal input part is exported to the pull-down node under control;Or for described The current potential of the pull-down node is pulled down to the current potential at the tertiary voltage end under the control of pull-up node;
The touch-control pull-down module connects the signal output end, touching signals control terminal and the tertiary voltage end, is used for Under the control of the touching signals control terminal, the current potential of the signal output end is pulled down to the electricity at the tertiary voltage end Position;
The charging module connects the touching signals control terminal and the pull-up node, in the pull-up node and touch-control Under the control of signal end, the signal of the touching signals control terminal is exported to the pull-up node;
The noise reduction module connects the pull-down node, the pull-up node, signal output end and the tertiary voltage end, uses Under the control in the pull-down node, the current potential of the pull-up node and the signal output end is pulled down to described respectively The current potential of three voltage ends.
2. shift register cell according to claim 1, which is characterized in that first input module includes first brilliant Body pipe, grid connection first signal input part of the first transistor, the first pole connection first voltage end, second Pole is connected with the pull-up node.
3. shift register cell according to claim 1, which is characterized in that second input module includes second brilliant Body pipe, the grid connection second signal input terminal of the second transistor, the first pole connection second voltage end, second Pole is connected with the pull-up node.
4. shift register cell according to claim 1, which is characterized in that the pull-up module includes third transistor With the first capacitance;
The grid of the third transistor connects the pull-up node, and the first pole connects first clock signal input terminal, the Two poles are connected with the signal output end;
One end of first capacitance is connected with the pull-up node, and the other end connects the signal output end.
5. shift register cell according to claim 1, which is characterized in that the pull-down control module includes the 4th brilliant Body pipe, the 5th transistor and the second capacitance;
The grid of 4th transistor and the first pole connect first clock signal input terminal, the second pole and the pull-down node phase Connection;
The grid of 5th transistor connects the pull-up node, and the first pole connects the pull-down node, the second pole with it is described Tertiary voltage end is connected;
One end of second capacitance connects the second clock signal input part, and the other end is connected with the pull-down node.
6. shift register cell according to claim 1, which is characterized in that the touch-control pull-down module includes the 6th brilliant The grid of body pipe, the 6th transistor connects touching signals control terminal, and the first pole connects the signal output end.
7. shift register cell according to claim 1, which is characterized in that the charging module includes the 7th transistor With the 8th transistor;
The grid of 7th transistor and the first pole connect the touching signals control terminal, and the second pole connects the 8th crystal First pole of pipe;
The grid of 8th transistor and the second pole connect the pull-up node.
8. shift register cell according to claim 1, which is characterized in that the charging module includes the 7th transistor With the 8th transistor;
The grid of 7th transistor connects pull-up node, and the first pole connects the touching signals control terminal, the second pole and institute The grid for stating the 8th transistor is connected;
First pole of the 8th transistor connects the touching signals control terminal, and the second pole is connected with the pull-up node.
9. shift register cell according to claim 1, which is characterized in that the noise reduction module includes the 9th transistor With the tenth transistor;
The grid of 9th transistor connects the pull-down node, and the first pole connects the pull-up node, the second pole with it is described Tertiary voltage end is connected;
The grid of tenth transistor connects the pull-down node, and the first pole connects the signal output end, the second pole and institute Tertiary voltage end is stated to be connected.
10. a kind of gate driving circuit, which is characterized in that including multiple cascade as claim 1-9 any one of them is moved Bit register unit, which is characterized in that
The first signal input part connection initial signal end of first order shift register cell;
Other than first order shift register cell, the signal output end connection next stage of upper level shift register cell moves First signal input part of bit register unit;
Other than afterbody shift register cell, in the second signal input terminal connection of next stage shift register cell The signal output end of level-one shift register cell;
The second signal input terminal of afterbody shift register cell connects the initial signal end.
11. a kind of display device, which is characterized in that including gate driving circuit as claimed in claim 10.
12. a kind of driving method of shift register cell, which is characterized in that in a picture frame, the method includes:
Input phase:
Under the control of the first signal input part, the first input module exports the signal at first voltage end to pull-up node;
Pull-up module stores the current potential of the pull-up node, and under the control of the pull-up node, the upper drawing-die Block exports the signal of the first clock signal input terminal to signal output end;
The output stage:
The signal stored on last stage is exported to the pull-up node in pull-up module, under the control of the pull-up node, The pull-up module exports the first clock signal of first clock signal input terminal to the signal output end, the letter Number output end exports gated sweep signal;
Reseting stage:
Pull-down control module is under the control of second clock signal input part and the pull-up node, by the second clock signal The second clock signal of input terminal is exported to pull-down node;
Under the control of the pull-down node, the voltage of the pull-up node and the signal output end is pulled down to by noise reduction module The current potential at tertiary voltage end;
The current potential of pull-up node is pulled down to the electricity at second voltage end by the second input module under the control of second signal input terminal Position;
Noise reduction is kept for the stage:
The pull-down control module is under the control of first clock signal input terminal and the pull-up node, by described first First clock signal of clock signal input terminal is exported to pull-down node;
Under the control of the pull-down node, the noise reduction module will be under the voltage of the pull-up node and the signal output end It is pulled to the current potential at the tertiary voltage end;
The reseting stage is repeated before next image frame and the noise reduction keeps first signal input part in stage, the second letter The control signal of number input terminal, the first clock signal input terminal and second clock signal input part so that the signal output End keeps the state of no signal output;
Touching signals input phase:
Touch-control pull-down module is pulled down to the third under the control of touching signals control terminal, by the current potential of the signal output end The current potential of voltage end.
13. the driving method of shift register cell according to claim 12, which is characterized in that in adjacent two field pictures The touching signals input phase is inserted between frame.
14. the driving method of shift register cell according to claim 12, which is characterized in that defeated in a picture frame Go out the stage insertion touching signals input phase, in the input phase, the driving method further includes:
Charging module is under the control of the pull-up node and the touching signals control terminal, by the touching signals control terminal Signal is exported to pull-up node, and is stored to the current potential of the pull-up node by pull-up module.
15. the driving method of shift register cell according to claim 12, which is characterized in that when the shift LD When transistor in device unit is N-type transistor, in first voltage end input high level, tertiary voltage end input low level In the case of, the method includes:
The input phase:The first signal input part input high level, first input module is in first signal By the high level output at the first voltage end to pull-up node under the control of the high level of input terminal;
The output stage:Under the control of the pull-up node high level, the pull-up module is by first clock signal The high level output of input terminal is to the signal output end;
The reseting stage:The high level output of the second clock signal input part is to the pull-down node, in the drop-down Under the control of node, the voltage of the pull-up node and the signal output end is pulled down to the third electricity by the noise reduction module The low level of pressure side;
The second signal input terminal input high level, the height that second input module is inputted in the second signal input terminal The current potential of pull-up node is pulled down to the low level at the second voltage end under the control of level;
The noise reduction is kept for the stage:The high level output of first clock signal input terminal is to the pull-down node, described Under the control of pull-down node, the voltage of the pull-up node and the signal output end is pulled down to described by the noise reduction module The low level of three voltage ends;
The touching signals input phase:The touching signals control terminal exports high level, and the touch-control pull-down module is described The current potential of the signal output end is pulled down to the tertiary voltage end under the control of the high level of touching signals control terminal output Low level.
16. the driving method of shift register cell according to claim 14, which is characterized in that when the shift LD When transistor in device unit is N-type transistor,
The touching signals input phase:The touching signals control terminal exports high level, and the pull-up node exports high level, The charging module is by the high level output of the touching signals control terminal to the pull-up node.
CN201610551812.4A 2016-07-13 2016-07-13 Shift register cell and its driving method, gate driving circuit, display device CN106128347B (en)

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