KR20140133033A - Scan Driver and Display Device Using the same - Google Patents

Abstract

The present invention includes a shift register composed of stages for outputting scan signals in response to clock signals, and the K^th stage among the stages has a scan driving unit including: a scan direction control unit that outputs a first voltage to a Q sub-node and sets the shift direction of the scan signals to a forward direction in response to a front carry signal inputted through a first input terminal, or outputs a second voltage to the Q sub-node and sets the shift direction of the scan signals to a backward direction in response to a rear carry signal inputted through a second input terminal; a node control unit that controls the charging/discharging of a Q node in response to the voltage of the Q sub-node and controls the charging/discharging of a QB node in response to the voltage of the Q sub-node, the first voltage, and the second voltage; and an output control unit that outputs a first scan signal through a first output node in response to the voltage of the Q and the QB node and outputs a second scan signal through a second output node in response to the voltage of the Q and the QB node.

Description

[0001] The present invention relates to a scan driver and a display device using the same,

The present invention relates to a scan driver and a display device using the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Some of the above-described display devices, for example, a liquid crystal display device and an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form and a driver for driving the display panel. The driving unit includes a scan driver for supplying a scan signal (or a gate signal) to the display panel, and a data driver for supplying a data signal to the display panel.

When a scan signal, a data signal, or the like is supplied to the subpixels arranged in a matrix form, the selected subpixel emits light so that an image can be displayed.

The scan driver for outputting a scan signal is divided into an external type to be mounted on an external substrate of the display panel in the form of an integrated circuit, and a built-in type to be formed on the display panel in a gate in panel form combined with the thin film transistor process. The built-in scan driver includes a thin film transistor based on low temperature polysilicon (LTPS), amorphous silicon (a-Si), or oxide.

Meanwhile, as narrow bezel competition has intensified in recent years, researchers are studying and implementing display devices that reduce the size of the bezel occupied by the built-in scan driver. However, the scan driver, which has been proposed and implemented in the past, occupies one scan line per one stage, which limits the size of the bezel.

In order to solve the above problems, the present invention provides a scan driver capable of reducing the size of a pull-up transistor and reducing the size of a bezel by simplifying the structure of a pull-down transistor and a display using the same.

According to an aspect of the present invention, there is provided a semiconductor memory device including a shift register configured by stages for outputting a scan signal in response to clock signals, and a K stage of the stages, in response to a previous carry signal input through a first input terminal The second voltage is outputted to the Q sub node in response to the last carry signal inputted through the second input terminal and the second voltage is outputted to the Q sub node in the shift direction of the scan signal A scan direction controller for setting the scan direction in the reverse direction; A node controller for controlling charging and discharging of the Q node corresponding to the voltage of the Q sub node and for controlling charge and discharge of the QB node corresponding to the voltage of the Q sub node and the first voltage and the second voltage; And an output controller for outputting a first scan signal through a first output node corresponding to a voltage of a Q node and a QB node and outputting a second scan signal through a second output node corresponding to voltages of the Q node and the QB node, And a scan driver for driving the scan driver.

The first scan signal and the second scan signal have the same rising edge period, and the time for maintaining the gate high can be overlapped differently.

When the shift direction of the scan signal is set to the forward direction, the time for maintaining the gate high is longer than that of the first scan signal. When the shift direction of the scan signal is set to the reverse direction, The first scan signal may be longer than the scan signal.

The output control unit includes a first pull-up transistor having a gate electrode connected to the Q node, a first A electrode connected to the A clock signal terminal and a second electrode connected to the first output node, a gate electrode connected to the QB node, A first pull-down transistor having a first electrode connected to a low-potential voltage terminal to which the first electrode is connected and a second electrode connected to a first output node, a gate electrode connected to the Q node, and a first electrode connected to the B clock signal terminal A second pull-up transistor having a gate electrode connected to the QB node, a first electrode connected to the low-potential voltage terminal, and a second electrode connected to the second output node, the second pull- .

The scan direction control unit includes a first transistor having a gate electrode connected to a first input terminal and a first electrode connected to a first voltage terminal to which a first voltage is supplied and a second electrode connected to a Q sub node, And a second transistor having a first electrode connected to a second voltage terminal to which a gate electrode is connected and a second voltage is supplied, and a second electrode connected to the Q sub node.

The node controller includes a third transistor having a gate electrode connected to a high potential terminal to which a high potential voltage is supplied, a first electrode connected to the Q sub node and a second electrode connected to the Q node, and a gate electrode connected to the QB node A fourth transistor having a first electrode connected to the low potential voltage terminal and a second electrode connected to the Q sub node, a fifth transistor having a gate electrode connected to the first voltage terminal and a first electrode connected to the C clock signal terminal, A sixth transistor having a gate electrode connected to the second voltage terminal and a first electrode connected to the D clock signal terminal, a gate electrode connected to the second electrode of the fifth transistor and the sixth transistor, A seventh transistor having a first electrode connected to the QB node and a second electrode connected to the QB node, an eighth transistor having a gate electrode connected to the Q node, a first electrode connected to the low potential voltage terminal and a second electrode connected to the QB node, Include There.

The node control unit includes capacitors for stabilizing outputs of the first output node and the second output node, the capacitors having a first capacitor connected at one end to the Q node and the other end connected to the low potential voltage terminal, And a second capacitor connected at the other end to the low potential voltage terminal.

In another aspect, the present invention provides a display panel comprising: a display panel; A data driver connected to the data lines of the display panel; And a shift register connected to the scan lines of the display panel and configured to output a scan signal in response to the clock signals, wherein the K stage of the stages is responsive to a front carry signal input through the first input terminal And outputs a second voltage to a Q sub node in response to a subsequent carry signal input through a second input terminal and outputs a second voltage to a Q sub node, And a controller for controlling charging and discharging of the Q node corresponding to the voltage of the Q sub node and for controlling the charging and discharging of the QB node corresponding to the voltage of the Q sub node and the first voltage and the second voltage, And a second output node corresponding to the voltages of the Q node and the QB node and outputting a first scan signal through the first output node in response to the voltages of the Q node and the QB node, It provides a display device characterized in that it comprises an output control section for outputting a second scanning signal through the node.

The first scan signal and the second scan signal have the same rising edge period, and the time for maintaining the gate high can be overlapped differently.

When the shift direction of the scan signal is set to the forward direction, the time for maintaining the gate high is longer than that of the first scan signal. When the shift direction of the scan signal is set to the reverse direction, The first scan signal may be longer than the scan signal.

The output control unit includes a first pull-up transistor having a gate electrode connected to the Q node, a first A electrode connected to the A clock signal terminal and a second electrode connected to the first output node, a gate electrode connected to the QB node, A first pull-down transistor having a first electrode connected to a low-potential voltage terminal to which the first electrode is connected and a second electrode connected to a first output node, a gate electrode connected to the Q node, and a first electrode connected to the B clock signal terminal A second pull-up transistor having a gate electrode connected to the QB node, a first electrode connected to the low-potential voltage terminal, and a second electrode connected to the second output node, the second pull- .

The scan direction control unit includes a first transistor having a gate electrode connected to a first input terminal and a first electrode connected to a first voltage terminal to which a first voltage is supplied and a second electrode connected to a Q sub node, And a second transistor having a first electrode connected to a second voltage terminal to which a gate electrode is connected and a second voltage is supplied, and a second electrode connected to the Q sub node.

The node controller includes a third transistor having a gate electrode connected to a high potential terminal to which a high potential voltage is supplied, a first electrode connected to the Q sub node and a second electrode connected to the Q node, and a gate electrode connected to the QB node A fourth transistor having a first electrode connected to the low potential voltage terminal and a second electrode connected to the Q sub node, a fifth transistor having a gate electrode connected to the first voltage terminal and a first electrode connected to the C clock signal terminal, A sixth transistor having a gate electrode connected to the second voltage terminal and a first electrode connected to the D clock signal terminal, a gate electrode connected to the second electrode of the fifth transistor and the sixth transistor, A seventh transistor having a first electrode connected to the QB node and a second electrode connected to the QB node, an eighth transistor having a gate electrode connected to the Q node, a first electrode connected to the low potential voltage terminal and a second electrode connected to the QB node, Include There.

The node control unit includes capacitors for stabilizing outputs of the first output node and the second output node, the capacitors having a first capacitor connected at one end to the Q node and the other end connected to the low potential voltage terminal, And a second capacitor connected at the other end to the low potential voltage terminal.

The present invention provides a display device that reduces the size of the bezel occupied by the built-in scan driver using a shift register having two or more output nodes per stage. Also, since two or more clock signals are superimposed and supplied to the present invention, the voltage of the Q node becomes high, so that the size of the pull-up transistor outputting the Q signal is reduced. Further, the present invention has the effect of simplifying the configuration of the pull-down transistor that outputs the QB node as the charging of the QB node continues for a certain period of time.

1 is a schematic block diagram of a display device;
FIG. 2 is a schematic configuration example of a subpixel shown in FIG. 1; FIG.
Figures 3 and 4 are schematic diagrams of stages of a shift register according to an embodiment of the present invention.
5 is a circuit diagram of a Kth stage according to an embodiment of the present invention;
6 is a diagram for explaining a state of charge of a Q node in a Kth stage;
7 is a diagram for explaining a charging state of a QB node of a K-th stage;
8 is a diagram showing driving and output waveforms of a Kth stage;
9 is a diagram showing an output waveform diagram when the drive mode of the Kth stage is in the forward direction;
10 is a diagram showing an output waveform diagram when the drive mode of the Kth stage is in the reverse direction.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic block diagram of a display device, and Fig. 2 is a schematic configuration diagram of a subpixel shown in Fig.

1, the display device includes a display panel 100, a timing controller 110, a data driver 120, and a scan driver 130 and 140, as shown in FIG.

The display panel 10 includes sub-pixels connected to the intersecting data lines DL and the scan lines GL separately. The display panel 10 includes a display region 100A in which subpixels are formed and a non-display region 100B in which various signal lines, pads, and the like are formed outside the display region 100A. The display panel 100 may be implemented by a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), or the like.

As shown in FIG. 2, one subpixel SP includes data corresponding to a scan signal supplied through the switching transistor SW and the switching transistor SW connected to the scan line GL1 and the data line DL1, And a pixel circuit PC that stores the signal DATA as a data voltage and operates in response to the signal DATA. The subpixel SP is implemented by a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of the pixel circuit PC.

When the display panel 100 is composed of a liquid crystal display panel, it may be a twisted nematic (TN) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, a FFS (Fringe Field Switching) mode, or an ECB (Electrically Controlled Birefringence) Mode. When the display panel 100 is formed of an organic light emitting display panel, it may be implemented as a top emission, a bottom emission, or a dual emission.

The timing controller 110 receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal through an LVDS or TMDS interface receiving circuit connected to an image board. The timing controller 110 generates timing control signals for controlling the operation timings of the data driver 120 and the scan drivers 130 and 140 based on the input timing signal.

The data driver 120 includes a plurality of source drive ICs (Integrated Circuits). The source drive ICs are supplied with digital data signals (RGB) and source timing control signals (DDC) from the timing controller 110. The source drive ICs convert digital data signals (RGB) into analog data signals in response to a source timing control signal (DDC). The source driver ICs supply the converted analog data signals through the data lines DL of the display panel 100. [ The source drive ICs are connected to the data lines DL of the display panel 100 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The scan drivers 130 and 140 include a level shifter 130 and a shift register 140. The scan driver 130 and the scan driver 140 are formed in a gate in panel (GIP) scheme in which the level shifter 130 and the shift register 140 are separately formed. The level shifter 130 is formed on an external substrate connected to the display panel 100 in the form of an IC.

The level shifter 130 shifts the level of the clock signals clk input from the timing controller 11 to the TTL (Transistor-Transistor-Logic) level of 0 V to 3.3 V and supplies the shifted level to the shift register 140 . The level shifter 130 converts an output waveform of the clock signals clk into a forward mode and a reverse mode according to a driving mode and outputs the output waveform. For this purpose, the timing controller 11 can vary the phase of the clock signals clk output from the timing controller 11. However, the level shifter 130 itself can change the output waveform of the clock signal clk according to the driving mode, And can be designed in various forms.

The shift register 140 is formed in the non-display area 100B of the display panel 100 in the form of a thin film transistor (hereinafter referred to as TFT) by the GIP method. The shift register 140 may include a thin film transistor based on low temperature polysilicon (LTPS), amorphous silicon (a-Si), or oxide. The shift register 140 can reduce the number of thin film transistors and capacitors, especially when formed on a low temperature polysilicon (LTPS) basis.

The shift register 140 is controlled in accordance with the clock signals clk, the start signal vst, the high potential power supply Vdd, the low potential power supply Vss, the first voltage Vdd_F and the second voltage Vdd_R. And a stage for outputting a signal. The stages included in the shift register 140 sequentially output the scan signals through the output nodes. On the other hand, the shift register 140 outputs the scan signals in the forward direction or the reverse direction in accordance with the driving mode.

Hereinafter, a shift register constituting a scan driver according to an embodiment of the present invention will be described in more detail.

3 and 4 are diagrams schematically illustrating stages of a shift register according to an embodiment of the present invention.

As shown in Figs. 3 and 4, the shift register includes the first stage SG_1 to the Nth stage SG_n, which are connected in a dependent manner. Although not shown, the shift register may include one or more dummy stages at the front end of the first stage SG_1 and at the rear end of the Nth stage SG_n.

The stages SG_1 to SG_n are supplied with at least two clock signals. The stages SG_1 to SG_n receive a total of four phase clock signals from the four clock signal terminals CLK1 to CLK4.

The stages SG_1 to SG_n have two output nodes for outputting at least two scan signals to different channels in response to a clock signal. For example, the first stage SG_1 has a first output node OUT1 and a second output node OUT2, and the Nth stage ST_n has an Nth output node OUT_n and an Nth output node OUT_n- 1). In the drawing, the stages SG_1 to SG_n have two output nodes as an example. However, it may have N (N is 2 or more) output nodes according to the number of circuits and clock signals forming the stages SG_1 to SG_n. Therefore, the present invention enables one stage to drive a plurality of scan lines since one stage has a plurality of output nodes.

The stages SG_1 to SG_n use scan signals, which are output signals at the front end and the rear end, as carry signals. For example, the first stage SG_1 uses the scan signal of the third output node OUT3 of the second stage SG_2 as a carry signal, and the second stage SG_2 uses the scan signal of the first stage SG_1, The scan signal of the second output node OUT1 is used as the carry signal.

When the driving mode of the scan driver is set to the forward direction, the stages SG_1 to SG_n are shifted in the order of the first stage SG_1 to the fourth stage SG_4 as shown in FIG. 3, and the scan signals are outputted. At this time, the start signal output from the start signal terminal VST is supplied to the first stage SG_1.

The stages SG_1 to SG_n are shifted in the order of the N-th stage SG_n to the N-7th stage SG_n-7 as shown in FIG. 4 when the driving mode of the scan driver is set in the reverse direction . At this time, the start signal output from the start signal terminal VST is supplied to the Nth stage SG_n.

The stages SG_1 to SG_n output the gate signal H of high level for a predetermined time according to the driving mode of the scan driver and output the gate signal of low level during the remaining time. Referring to the first scan signal output through the first output node OUT1 of the first stage SG_1 and the second scan signal output from the second output node OUT2, It can be seen that the first scan signal and the second scan signal have overlapping periods. At this time, when all the output nodes OUT1 to OUT_n of the stages SG_1 to SG_n are seen, the rising edge period of the first scan signal and the second scan signal are the same, and the time for maintaining the gate high is overlapped differently.

Specifically, when the shift direction of the scan signal is set to the forward direction as shown in FIG. 3, the second scan signal is longer than the first scan signal. Referring to the first stage SG_1, the first scan signal outputted through the first output node OUT1 becomes 2H (Horizontal), and the second scan signal outputted through the second output node OUT2 becomes 2H Becomes 4H.

However, when the shift direction of the scan signal is set to the reverse direction as shown in FIG. 4, the first scan signal is longer than the second scan signal. The first scan signal outputted through the first output node OUT_n-1 is 2H, and the second scan signal output through the second output node OUT_n is 4H. That is, the first scan signal and the second scan signal have the same rising edge period. However, when one of the scan signals maintains the gate high, the other one is shortened so that the scan signal alternates and overlaps according to the shift direction of the scan signal.

Hereinafter, the circuit constituting the stage according to the embodiment of the present invention will be described in more detail.

5 is a diagram showing a circuit configuration of a Kth stage according to an embodiment of the present invention.

5, the K-th stage includes scan direction control units Tr1 and Tr2, node control units Tr3 to Tr8, and output control units Tpu1, Tpu2, Tpd1, and Tpd2.

The scan direction control units Tr1 and Tr2 output the first voltage to the Q sub node Q sub in response to the previous carry signal input through the first input terminal Prev and set the shift direction of the scan signal in the forward direction , And outputs a second voltage to the Q sub node (Q sub) in response to a subsequent carry signal input through the second input terminal (Next), and sets the shift direction of the scan signal in the reverse direction.

The scan direction control units Tr1 and Tr2 include first and second transistors Tr1 and Tr2. The first transistor Tr1 has a first electrode connected to a first voltage terminal VDD_F to which a gate electrode is connected to a first input terminal Prev and to which a first voltage is supplied, Electrodes are connected. The second transistor Tr2 has a first electrode connected to a second voltage terminal VDD_R to which a gate electrode is connected to a second input terminal Next and a second voltage is supplied, Electrodes are connected.

The node controllers Tr3 to Tr8 control the charging and discharging of the Q node Q in response to the voltage of the Q sub node Q sub and control the charge and discharge of the Q node Q sub to the first voltage and the second voltage And controls the charging and discharging of the QB node QB correspondingly.

The node control units Tr3 to Tr8 include the third to eighth transistors Tr3 to Tr8. The third transistor Tr3 has a gate electrode connected to a high potential terminal VDD to which a high potential is supplied, a first electrode connected to the Q sub node Q sub, a second electrode connected to the Q node Q, . The fourth transistor Tr4 has a gate electrode connected to the QB node QB, a first electrode connected to the low potential voltage terminal VSS, and a second electrode connected to the Q sub node Q sub. The fifth transistor Tr5 has a gate electrode connected to the first voltage terminal VDD_F and a first electrode connected to the C clock signal terminal CLK_C. The sixth transistor Tr6 has a gate electrode connected to the second voltage terminal VDD_R and a first electrode connected to the D clock signal terminal CLK_D. The seventh transistor Tr7 has a gate electrode commonly connected to a second electrode of the fifth and sixth transistors Tr5 and Tr6 and a first electrode connected to the high potential terminal VDD and a QB node QB And the second electrode is connected. In the eighth transistor, the gate electrode is connected to the Q node Q, the first electrode is connected to the low potential voltage terminal VSS, and the second electrode is connected to the QB node QB.

The node controllers Tr3 to Tr8 include first and second capacitors CQ and CQ_B for stabilizing outputs of the first output node OUT1 and the second output node OUT2. The first capacitor CQ has one end connected to the Q node Q and the other end connected to the low potential voltage terminal VSS. The second capacitor CQ_B has one end connected to the QB node QB and the other end connected to the low potential voltage terminal VSS.

The output control units Tpu1, Tpu2, Tpd1 and Tpd2 output the first scan signal through the first output node OUT1 corresponding to the voltages of the Q node QB and the QB node QB, And outputs the second scan signal through the second output node OUT2 corresponding to the voltage of the QB node QB.

The output control units Tpu1, Tpu2, Tpd1 and Tpd2 include first and second pull-up transistors Tpu1 and Tpu2 and first and second pull-down transistors Tpd1 and Tpd2. The first pull-up transistor Tpu1 has a gate electrode connected to the Q node Q, a first electrode connected to the A clock signal terminal CLK_A, and a second electrode connected to the first output node OUT1. The first pull-down transistor Tpd1 has a first electrode connected to a low-potential voltage terminal VSS to which a gate electrode is connected to the QB node QB and a low-potential voltage is supplied, and a second electrode connected to the first output node OUT1, Lt; / RTI >

The second pull-up transistor Tpu2 has a gate electrode connected to the Q node Q, a first electrode connected to the B clock signal terminal CLK_B, and a second electrode connected to the second output node OUT2. The second pull-down transistor Tpd2 has a first electrode connected to the low potential voltage terminal VSS to which the gate electrode is connected to the QB node QB and to which a low potential voltage is supplied and a second electrode connected to the second output node OUT2, Lt; / RTI >

Hereinafter, a driving method of a circuit constituting the K-th stage will be described in more detail according to an embodiment of the present invention.

Fig. 6 is a view for explaining the charging state of the Q node of the K-th stage, Fig. 7 is a view for explaining the charging state of the QB node of the K-th stage, Fig.

As shown in FIGS. 6 to 8, the Q node Q becomes a charging period and the QB node QB becomes a discharging period during a period from T1 to T3. During the period after T4 and T5, the Q node Q becomes the discharge interval and the QB node QB becomes the charge interval.

The first transistor Tr1 is turned on when the carry signal prev of the previous stage is supplied in the logic high state to the first transistor Tr1 during the T1 period. As the first transistor Tr1 is turned on, the first voltage Vdd_F corresponding to the logic high H supplied through the first voltage terminal VDD_F is output through the Q sub node Q sub. In this way, when the Q sub node Q sub is charged with the first voltage Vdd_F corresponding to the logic high H, the shift register including the K stage becomes a mode for outputting the scan signal in the forward direction.

The second transistor Tr2 is turned off since the carry signal at the subsequent stage corresponds to the logic low (L). However, when the carry signal of the subsequent stage is supplied in a logic high (H) state, the second transistor Tr2 is turned on. As the second transistor Tr2 is turned on, the second voltage Vdd_R corresponding to the logic high H supplied through the second voltage terminal VDD_R is output through the Q sub node Q sub. In this manner, when the Q sub node Q sub is charged with the second voltage Vdd_R corresponding to the logic high H, the shift register including the K stage becomes a mode for outputting the scan signal in the reverse direction.

As described above, when the first transistor Tr1 is turned on, the first voltage Vdd_F corresponding to the logic high H is supplied through the first voltage terminal VDD_F, and the K- . On the contrary, when the second transistor Tr2 is turned on, the second voltage Vdd_R corresponding to the logic low L is supplied through the second voltage terminal VDD_R, and the K-th stage becomes the reverse mode. That is, the first transistor Tr1 and the second transistor Tr2 alternately turn on / off according to the driving mode. The first voltage Vdd_F and the second voltage Vdd_R supplied to the first voltage terminal VDD_F and the second voltage terminal VDD_R are set to a voltage corresponding to the logic high H and a logic low L in response to the voltage swing.

The Q node Q is charged by the third transistor Tr3 when the first voltage Vdd_F corresponding to the logic high H is charged to the Q sub node Q sub during the T1 period. On the other hand, since the eighth transistor Tr8 is turned on as the Q node Q is charged, the QB node QB is discharged by the low potential voltage. On the other hand, in the case of the third transistor Tr3, since the gate electrode is connected to the high-potential voltage terminal VDD, it is always turned on. Therefore, when the Q node B can form a stable charging state or to simplify the circuit, the third transistor Tr3 may be omitted.

The first clock signal fclk1 corresponding to the logic high H is supplied to the A clock signal terminal CLK_A during the T2 interval and the second clock signal fclk1 corresponding to the logic high H is supplied to the B clock signal terminal CLK_B, The clock signal fclk2 is supplied. The first clock signal fclk1 maintains logic high H during the T2 interval while the second clock signal fclk2 remains at logic high H during the T2 and T3 intervals. That is, the period in which the second clock signal fclk2 maintains the logic high H is at least 1H longer than the first clock signal fclk1.

The first and second pull-up transistors Tpu1 and Tpu2 are turned on by the voltage charged in the Q node Q. Since the first clock signal fclk1 and the second clock signal fclk2 are simultaneously supplied through the first and second pull-up transistors Tpu1 and Tpu2, the Q node Q largely generates bootstrapping, .

When the first clock signal fclk1 and the second clock signal fclk2 are superimposed and supplied in this way, the voltage of the Q node Q becomes high, so that the potential of the first and second pull- up transistors Tpu1 and Tpu2 The size can be reduced. In the present invention, as described above, the clock signals are superimposed to reduce the size of the buffer transistor. However, the clock signals can be input in a form superimposed on each other in accordance with necessity (driving method of subpixel, etc.).

The first output node OUT1 outputs the first scan signal out1 of the gate high H by the first pull-up transistor Tpu1 and the second output node OUT2 outputs the first scan signal OUT2 of the second And the second scan signal out2 of the gate high H is output by the pull-up transistor Tpu2. At this time, the first and second scan signals out1 and out2 output from the first and second output nodes OUT1 and OUT2 correspond to the first clock signal fclk1 and the second clock signal fclk2, The intervals are the same (or synchronized). However, since the phases of the first clock signal fclk1 and the second clock signal fclk2 are different from each other, the time during which the first and second scan signals out1 and out2 are superimposed is 1/2.

The third clock signal fclk3 corresponding to the logic high H is supplied to the C clock signal terminal CLK_C during the period T4 and the fourth clock signal fclk2 corresponding to the logic high H is supplied to the D clock signal terminal CLK_D, A clock signal fclk4 is supplied. The third clock signal fclk3 maintains a logic high H during the T4 interval while the fourth clock signal fclk4 maintains a logic high H during the T4 and T5 intervals. That is, the section in which the fourth clock signal fclk4 maintains the logic high H is at least 1H longer than the third clock signal fclk3.

Since the fifth transistor Tr5 is turned on by the first voltage Vdd_F and the sixth transistor Tr6 is turned off by the second voltage Vdd_R, the seventh transistor Tr7 is turned off by the third And turned on in response to the clock signal fclk3. As the seventh transistor Tr7 is turned on, the QB node QB is charged according to the high-potential voltage. At this time, as the QB node QB is charged, the fourth transistor Tr4 is turned on and the Q node Q is discharged by the low potential voltage.

Since the first and second pull-down transistors Tpd1 and Tpd2 are turned on by the voltage charged in the QB node QB, the first output node OUT1 is turned on by the first pull-down transistor Tpd1 in the gate- And the second output node OUT2 outputs the second scan signal out2 of the gate line L by the second down transistor Tpd2.

Meanwhile, since the seventh transistor Tr7 is coupled by the first voltage Vdd_F and the second voltage Vdd_R, the QB node QB can maintain a constant charging state. That is, the seventh transistor Tr7 serves to prevent the Q node Q from being charged. To this end, the seventh transistor Tr7 is coupled by the first voltage Vdd_F and the second voltage Vdd_R to maintain the QB node QB at the gate-high voltage and the gate-low voltage. As a result, the first scan signal out1 of the gate line L and the second scan signal out2 of the gate line L are output stably through the first and second pull-down transistors Tpd1 and Tpd2, The output state can be maintained continuously. In addition, since the seventh transistor Tr7 is coupled by the first voltage Vdd_F and the second voltage Vdd_R, a transistor for maintaining the QB node QB in a charged state need not be separately formed, . ≪ / RTI >

In the above description, a logic high H signal is supplied to the first transistor Tr1 during the T1 period, and a forward mode in which the shift register including the Kth stage outputs the scan signal in the forward direction has been described. However, if a logic high signal is supplied to the second transistor Tr2 during the T1 period, the shift register including the Kth stage is switched to the reverse mode in which the scan signal is output in the reverse direction. At this time, the operation characteristics of the scan direction control units Tr1 and Tr2, the node control units Tr3 to Tr8, and the output control units Tpu1, Tpu2, Tpd1, and Tpd2 are similar to those described above. And therefore, a description thereof will be omitted.

Hereinafter, an output pattern of the scan signal will be described with reference to the output waveform according to the drive mode of the K-th stage according to the embodiment of the present invention. 3 and 4 together for an understanding of the configuration of the stages.

FIG. 9 is a diagram showing an output waveform when the drive mode of the K-th stage is forward, and FIG. 10 is a diagram showing an output waveform when the drive mode of the K-th stage is reverse.

[Forward mode]

As shown in FIGS. 3, 4 and 9, when the drive mode of the K-th stage is the forward direction, the first to N-th clock signals fclk1 to fclkn of the forward mode are supplied. The first stage SG_1 outputs the first scan signal out1 and the second scan signal out2 of the gate high H through the first output node OUT1 and the second output node OUT2 thereof . At this time, the first scan signal out1 and the second scan signal out2 are outputted with the same rising edge interval (or synchronized) and have overlapping intervals. The first scan signal out1 becomes a gate low L ahead of the second scan signal out2. Then, after a predetermined time, the second scan signal out2 becomes a gate low (L).

The second stage SG_2 outputs the third scan signal out3 and the fourth scan signal out4 of the gate high H through the third output node OUT3 and the fourth output node OUT4 thereof, do. At this time, the third scan signal out3 and the fourth scan signal out4 are also output in the same rising or falling edge period and have overlapping periods. And the third scan signal out3 becomes a gate low L ahead of the fourth scan signal out4. After a predetermined time, the fourth scan signal out4 also becomes a gate low (L).

Therefore, when the drive mode of the K-th stage is the forward direction, all the stages SG_1 to SG_n are shifted in the order of the first stage SG_1 to the N-th stage SG_n in this manner, .

[Reverse mode]

As shown in FIGS. 3, 4 and 10, when the drive mode of the K-th stage is the reverse direction, the first to N-th clock signals rclk1 to rclkn in the reverse mode are supplied. The N-th stage SG_N outputs the first scan signal out_n and the second scan signal out_n of the gate high H through the Nth output node OUT_n and the N-1th output node OUT_n- -1). At this time, the first scan signal out_n and the second scan signal out_n-1 are output in the same rising edge period (or synchronously) and have overlapping intervals. The first scan signal out_n becomes a gate low L ahead of the second scan signal out_n-1. After a predetermined period of time, the second scan signal out_n-1 becomes gate low (L).

The N-1 stage (SG_n-1) of the gate high (H) through the N-2th output node OUT_n-2 and the N-3th output node OUT_n- And outputs the signal out_n-2 and the (N-3) th scan signal out_n-3. At this time, the rising edge sections of the (N-2) th scan signal out_n-2 and the (N-3) th scan signal out_n-3 are output in the same (or synchronized) manner and have overlapping sections. The N-2 scan signal out_n-2 becomes gate-low L ahead of the N-3 scan signal out_n-3. After a predetermined time has elapsed, the (N-3) th scan signal out_n-3 becomes a gate low (L).

When the drive mode of the K-th stage is the reverse direction, all stages SG_1 to SG_n are shifted in the order of the N-th stage SG_n to the first stage SG_1 in this manner and sequentially output scan signals .

As described above, the present invention provides a display device that reduces the size of the bezel occupied by the built-in scan driver using a shift register having two or more output nodes per stage. Also, since two or more clock signals are superimposed and supplied to the present invention, the voltage of the Q node becomes high, so that the size of the pull-up transistor outputting the Q signal is reduced. Further, the present invention has the effect of simplifying the configuration of the pull-down transistor that outputs the QB node as the charging of the QB node continues for a certain period of time.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130, 140: scan driver
SG_1 to SG_n: Stages Tr1 and Tr2:
Tr3 to Tr8: Node control units Tpu1, Tpu2, Tpd1, Tpd2:

Claims (14)

And a shift register composed of stages for outputting a scan signal in response to the clock signals,
The K stage of the stages
In response to the previous carry signal inputted through the first input terminal, the first voltage is outputted to the Q sub node, and the shift direction of the scan signal is set in the forward direction. In response to the carry signal inputted through the second input terminal, A scan direction controller for outputting a second voltage to the Q sub node and setting a shift direction of the scan signal in a reverse direction;
A node controller for controlling charging and discharging of the Q node corresponding to the voltage of the Q sub node and controlling charging and discharging of the QB node corresponding to the voltage of the Q sub node and the first voltage and the second voltage; And
Outputting a first scan signal through a first output node corresponding to a voltage of the Q node and the QB node and outputting a second scan signal through a second output node corresponding to a voltage of the Q node and the QB node, And an output control unit for driving the scan driver. The method according to claim 1,
The first scan signal and the second scan signal are
And the rising edge period is the same, and the time for maintaining the gate high is overlapped differently. 3. The method of claim 2,
When the shift direction of the scan signal is set to the forward direction, the time for maintaining the gate high is longer than the first scan signal,
Wherein the first scan signal is longer than the second scan signal when the shift direction of the scan signal is set to the opposite direction. The method according to claim 1,
The output control unit
A first pull-up transistor having a gate electrode connected to the Q node, a first A electrode connected to the A clock signal terminal and a second electrode connected to the first output node,
A first pull-down transistor having a gate electrode connected to the QB node and a first electrode connected to a low-potential voltage terminal to which a low-potential voltage is supplied, and a second electrode connected to the first output node;
A second pull-up transistor having a gate electrode connected to the Q node, a first clock terminal connected to the B clock signal terminal, and a second electrode connected to the second output node;
And a second pull-down transistor having a gate electrode connected to the QB node, a first electrode connected to the low potential voltage terminal, and a second electrode connected to the second output node. 5. The method of claim 4,
The scan direction control unit
A first transistor having a gate electrode connected to the first input terminal, a first electrode connected to the first voltage terminal to which the first voltage is supplied, and a second electrode connected to the Q sub node;
And a second transistor having a gate electrode connected to the second input terminal, a first electrode connected to a second voltage terminal to which the second voltage is supplied, and a second electrode connected to the Q sub node. 6. The method of claim 5,
The node control unit
A third transistor having a gate electrode connected to a high potential voltage terminal to which a high potential voltage is supplied, a first electrode connected to the Q sub node, and a second electrode connected to the Q node;
A fourth transistor having a gate electrode connected to the QB node, a first electrode connected to the low potential voltage terminal and a second electrode connected to the Q sub node,
A fifth transistor having a gate electrode connected to the first voltage terminal and a first electrode connected to the C clock signal terminal,
A sixth transistor having a gate electrode connected to the second voltage terminal and a first electrode connected to the D clock signal terminal,
A seventh transistor having a gate electrode commonly connected to a second electrode of the fifth transistor and the sixth transistor, a first electrode connected to the high potential voltage terminal, and a second electrode connected to the QB node;
And an eighth transistor having a gate electrode connected to the Q node, a first electrode connected to the low potential voltage terminal, and a second electrode connected to the QB node. The method according to claim 6,
The node control unit
Capacitors for stabilizing the output of the first output node and the second output node,
The capacitors
A first capacitor having one end connected to the Q node and the other end connected to the low potential voltage terminal;
And a second capacitor having one end connected to the QB node and the other end connected to the low potential voltage terminal. Display panel;
A data driver connected to the data lines of the display panel; And
And a shift register connected to the scan lines of the display panel and configured of stages for outputting a scan signal in response to the clock signals,
The K stage of the stages
In response to the previous carry signal inputted through the first input terminal, the first voltage is outputted to the Q sub node, and the shift direction of the scan signal is set in the forward direction. In response to the carry signal inputted through the second input terminal, A scan direction controller for outputting a second voltage to the Q sub node and setting a shift direction of the scan signal in a reverse direction,
A node controller for controlling charging and discharging of the Q node corresponding to the voltage of the Q sub node and controlling charging and discharging of the QB node corresponding to the voltage of the Q sub node and the first voltage and the second voltage;
Outputting a first scan signal through a first output node corresponding to a voltage of the Q node and the QB node and outputting a second scan signal through a second output node corresponding to a voltage of the Q node and the QB node, And an output control unit for outputting a control signal to the display unit. 9. The method of claim 8,
The first scan signal and the second scan signal are
Wherein a rising edge period is the same and a time for maintaining the gate high is overlapped differently. 10. The method of claim 9,
When the shift direction of the scan signal is set to the forward direction, the time for maintaining the gate high is longer than the first scan signal,
Wherein when the shift direction of the scan signal is set to the opposite direction, the first scan signal is longer than the second scan signal by a time to maintain the gate high. 9. The method of claim 8,
The output control unit
A first pull-up transistor having a gate electrode connected to the Q node, a first A electrode connected to the A clock signal terminal and a second electrode connected to the first output node,
A first pull-down transistor having a gate electrode connected to the QB node and a first electrode connected to a low-potential voltage terminal to which a low-potential voltage is supplied, and a second electrode connected to the first output node;
A second pull-up transistor having a gate electrode connected to the Q node, a first clock terminal connected to the B clock signal terminal, and a second electrode connected to the second output node;
And a second pull-down transistor having a gate electrode connected to the QB node, a first electrode connected to the low potential voltage terminal, and a second electrode connected to the second output node. 12. The method of claim 11,
The scan direction control unit
A first transistor having a gate electrode connected to the first input terminal, a first electrode connected to the first voltage terminal to which the first voltage is supplied, and a second electrode connected to the Q sub node;
And a second transistor having a gate electrode connected to the second input terminal, a first electrode connected to the second voltage terminal to which the second voltage is supplied, and a second electrode connected to the Q sub node. 13. The method of claim 12,
The node control unit
A third transistor having a gate electrode connected to a high potential voltage terminal to which a high potential voltage is supplied, a first electrode connected to the Q sub node, and a second electrode connected to the Q node;
A fourth transistor having a gate electrode connected to the QB node, a first electrode connected to the low potential voltage terminal and a second electrode connected to the Q sub node,
A fifth transistor having a gate electrode connected to the first voltage terminal and a first electrode connected to the C clock signal terminal,
A sixth transistor having a gate electrode connected to the second voltage terminal and a first electrode connected to the D clock signal terminal,
A seventh transistor having a gate electrode commonly connected to a second electrode of the fifth transistor and the sixth transistor, a first electrode connected to the high potential voltage terminal, and a second electrode connected to the QB node;
And an eighth transistor having a gate electrode connected to the Q node, a first electrode connected to the low potential voltage terminal, and a second electrode connected to the QB node. 14. The method of claim 13,
The node control unit
Capacitors for stabilizing the output of the first output node and the second output node,
The capacitors
A first capacitor having one end connected to the Q node and the other end connected to the low potential voltage terminal;
And a second capacitor having one end connected to the QB node and the other end connected to the low potential voltage terminal.

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