KR20190071296A - Gate driver and display device having the same - Google Patents

Abstract

According to the present invention, a display device includes a display panel, a gate driver, and a mode controller. The display panel has a display portion in which gate lines and data lines connected to pixels are arranged and which is divided into a first display region and a second display region. The gate driver includes a plurality of stages and each of the stages outputs a gate pulse applied to the gate lines through an output terminal, in response to a voltage of a Q node. The mode controller displays an image in the first and second display regions in a first drive mode, and displays preset information in the first display region in a second drive mode, wherein the mode controller initializes the Q node of at least one stage among the stages driving the second display region in the second drive mode to a turn-off voltage. Thus, power consumption can be reduced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driver,

The present invention relates to a gate driver and a display device including the same.

The display device is arranged such that the data lines and the gate lines are orthogonal and the pixels are arranged in a matrix form. Video data voltages to be displayed are supplied to the data lines and gate pulses are sequentially supplied to the gate lines. The video data voltage is supplied to the pixels of the display line to which the gate pulse is supplied and all of the display lines are sequentially scanned by the gate pulse to display the video data.

Display devices are also applied to mobile terminals such as mobile phones, smart phones, tablet computers, notebook computers, and wearable devices. The mobile terminal stops driving the display device in order to reduce power consumption in the standby mode. Since the user restarts the mobile terminal when viewing simple information such as a clock, the mobile terminal is repeatedly turned on / off frequently. In order to reduce the inconvenience of users, an AOD (Alaways On Diplay) function for displaying user-designated information such as a clock, a calendar, etc. on the screen is always added to the mobile terminal. It is general that the information specified by the AOD function uses only a part of the display panel and the area where information is not displayed displays black. In the AOD function, there is a method of displaying black in a black region that does not display an image, or a method of not displaying pixels in a corresponding black region.

In order to use the method of writing black data in the black region, both the gate driver for generating the gate pulse and the data driver for generating the data voltage must operate, resulting in waste of power consumption.

There is a disadvantage that a gate driver for separately driving only the area where the AOD information is displayed must be additionally constructed in order to not drive the black area when using the AOD function to reduce power consumption.

The present invention provides a gate driver capable of stopping driving of an area where AOD information is not displayed, without separately configuring a gate driver for driving an area in which AOD information is displayed, and a display device including the same.

A display device according to the present invention includes a display panel, a gate driver, and a mode controller. The display panel has a display portion in which gate lines and data lines connected to the pixels are arranged and divided into a first display region and a second display region. The gate driver is composed of a plurality of stages, and each of the stages outputs a gate pulse applied to the gate lines through an output terminal in response to the voltage of the Q node. The mode control unit displays the image in the first and second display areas in the first drive mode, displays information preset in the first display area in the second drive mode, and drives the second display area in the second drive mode And initializes the Q node of at least one of the stages to a turn-off voltage.

Since the present invention drives only a part of the display panel when the AOD function operates without increasing the size of the bezel area in which the gate driver is disposed, power consumption can be reduced.

In particular, the present invention can prevent the stage from outputting a gate pulse because it resets the Q node of the stage driving the second display region in which the AOD function operates, to the turn-off voltage.

1 is a view showing a display device according to the present invention.
2 is a block diagram showing a configuration of a drive IC according to the present invention.
3 is a diagram showing the division of the display unit in the standby mode.
4 is a view showing a shift register of a gate driver according to the present invention.
5 is a diagram showing a stage of a shift register according to the present invention.
6 is a timing chart of a clock signal applied to the shift register in the first drive mode.
FIG. 7 is a diagram showing the timing and the data voltages of the clock signal applied to the shift register in the second drive mode.
8 is a diagram showing the operation of the abnormal power-off detection unit and the change in the output of the data voltage according to the operation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In the gate driving circuit of the present specification, the switching elements may be implemented as n-type or p-type metal oxide semiconductor field effect transistor (MOSFET) transistors. In the following embodiments, n-type transistors are exemplified, but the present specification is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. The source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the invention is not limited to the source and the drain of the transistor.

1 is a schematic view illustrating a display device according to an embodiment of the present invention. 2 is a block diagram showing a configuration of a drive integrated circuit (DIC) shown in FIG. 3 is a view showing that the display section of the display panel is divided according to the drive mode.

1 to 3, the display device of the present invention includes a display panel PNL and a drive IC (DIC) for driving the display panel PNL.

The display portion AA of the display panel PNL is formed by the data lines DL and the gate lines GL orthogonal to the data lines DL and the data lines DL and the gate lines GL (P) in the form of a defined matrix. The display portion AA of the display panel PNL can be divided into a TFT array and a color filter array. A TFT array may be formed on an upper plate or a lower plate of the display panel (PNL). The TFT array includes TFTs (Thin Film Transistors, T) formed at the intersections of the data lines DL and the gate lines GL, pixel electrodes of the liquid crystal cell Clc filling the voltage of the data signal, And a storage capacitor (Cst) (not shown) connected to the pixel electrode and holding a data voltage, and the like, and displays the input image. Storage capacitors are omitted from the drawing.

A color filter array may be formed on the upper panel or the lower panel of the display panel (PNL). The color filter array includes a black matrix, a color filter, and the like. In the case of a color filter on TFT (COT) or a TFT on color filter (TOC) model, a color filter and a black matrix together with a TFT array can be arranged on one substrate.

A gate driver 120 may be formed on the display panel PNL. The gate driver 120 includes a shift register that outputs a gate pulse synchronized with a data signal in response to a gate timing control signal input through a drive IC (DIC). The gate timing control signal includes a start pulse and a shift clock. The shift register sequentially supplies gate pulses to the gate lines GL by shifting the gate pulses by adjusting the start pulse to the shift clock timing.

The TFTs T of the display panel PNL are turned on according to the gate pulse to select a line of the display panel PNL into which the data of the input image is written. The shift register can be formed directly on the substrate of the display panel (PNL) in the same process together with the TFT array of the pixel array.

The drive IC DIC supplies a data signal of the input image to the data lines DL and supplies a gate timing control signal including the clock signals CLK to the gate driver 120. [ The drive IC DIC includes a power supply unit 10, a mode control unit 20, an abnormal power supply OFF sensing unit 30, a timing signal generating unit 100, and a data driver 110.

The power supply unit 10 generates a DC power required for driving the display panel PNL using a DC-DC converter. The DC-DC converter includes a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 10 receives a DC power source such as AVDD, AVEE, and VDDI from an external power source, for example, a power source necessary for driving the pixels and the touch sensors of the display panel PNL. AVDD and AVEE can be generated in mobile devices at voltages of + 5.5V and -5.5V, respectively, but are not limited thereto. The power supply unit 10 generates the liquid crystal driving voltage AVDD and AVEE using the regulator and the charge pump, the on / off voltages VGH and VGL of the TFT T, the gamma compensation voltage, and the voltage of the touch driving signal. VDDI may be generated as a voltage for controlling the drive IC (DIC), for example, 1.8 V as a drive voltage of the logic circuit portion of the drive IC.

The mode control unit 20 controls the display panel PNL to operate in the first drive mode or the second drive mode. The first drive mode corresponds to the normal drive mode, and in the first drive mode, the mode control unit 20 controls to display an image on the entire area of the display unit AA. The second drive mode corresponds to a drive mode in which a standby mode such as the AOD mode operates. In the second drive mode, the mode control unit 20 displays an image only in a partial area of the display unit AA.

3 is a diagram showing an example of the second drive mode operation.

3, the display unit AA may be divided into a first display area AA1 for displaying an image in a second driving mode and a second display area AA2 for not displaying an image in the second driving mode . The image displayed in the first display area AA1 in the second drive mode may be preset information and may be simple message information such as time or text notification. 3, the first display area AA1 is an area in which the first to k-1 (k is a natural number) pixel lines HL1 to HL [k-1] are arranged, and the second display area AA2 ) Is an area in which pixel lines HL [k] to hl [n] from k to n (n is a natural number larger than k) are arranged. One pixel line may be defined as pixels P connected to the same gate line GL and simultaneously receiving a gate pulse.

The mode control unit 20 does not generate the first APO signal APO1 and the second APO signal APO2 in the first drive mode. That is, the mode control unit 20 maintains the first APO signal APO1 and the second APO signal APO2 at the turn-off voltage when displaying an image on the entire display unit AA according to the normal driving mode.

The mode control unit 20 outputs the first APO signal APO1 at the timing of driving the second display area AA2 in the second drive mode. For example, the first APO signal APO1 is output at the time when the k-th gate pulse applied to the k-th pixel line HL [k] is applied.

The abnormal power off detection unit 30 monitors the DC input power source Vin such as AVDD, AVEE and VDDI and generates the first and second APO signals when the DC input power source Vin becomes abnormally low . In the case of a mobile device, first and second APO signals may be generated when the battery suddenly disconnects.

The timing signal generator 100 transmits pixel data of an input image received from a host system (not shown) to the data driver 110. The timing signal generator 100 receives a timing signal received in synchronism with the pixel data and generates a data timing control signal for controlling the operation timing of the data driver 110 and a data timing control signal for controlling the operation timing of the gate driver 120 And generates a gate timing control signal. A demultiplexer (MUX) may be disposed between the drive IC (DIC) and the data lines (DL). In this case, the timing signal generator 100 generates a MUX control signal for controlling the demultiplexer (MUX).

The data driver 110 receives pixel data (digital data) of an input image from the timing signal generator 100 during a display period and latches the pixel data to generate a digital-to-analog converter (DAC) Quot;). The DAC converts the pixel data into a gamma compensation voltage to generate a voltage of the data signal.

4 is a view showing a shift register included in the gate driver.

Referring to FIG. 4, the shift register according to the present invention includes first through n-th stages STG1 through STG [n] that are connected to each other in a dependent manner. The first stage STG generates and applies the first gate pulse Gout1 to the first gate line GL1. The n-th stage STG [n] generates the n-th gate pulse Gout [n] and applies it to the n-th gate line GL [n].

The first stage STG1 is set to the Q node in response to the start pulse VST and the second stage STG2 is set to the Q node in response to the first gate pulse Gout1. Similarly, the k-th stage STG [k] is set in response to the (k-1) -th gate pulse Gout [k-1], and the n-th stage STG [n] -1) gate pulse Gout [n-1]. Setting the Q node means that the Q node is precharged to the turn-on voltage.

The operation of discharging the Q node of each stage to the turn-off voltage utilizes the clock signals.

FIG. 5 is a diagram showing a k-th stage among the stages shown in FIG. 4, and FIG. 6 is a diagram showing output timings of gate signals and clock signals applied to the stages. 6 shows an embodiment in which the clock signal applied to the pull-up transistor Tpu of the k-th stage is the first clock signal CLK1.

5 and 6, the stage k of the shift register (k is a natural number less than n-2) includes a start control unit T1, a reset unit T2, third and fourth transistors T4, A pull-up transistor Tpd, and a pull-down transistor Tpd. The pull-down transistor Tpd is connected between the output terminal T7 and the sixth transistor T6.

 The start control unit T1 includes a gate electrode receiving a start pulse VST or a (k-1) th scan pulse Gout [k-1], a drain electrode connected to a high potential voltage (VDD) Source electrode. The start control unit T1 charges the Q node in response to the start pulse VST or the (k-1) th scan pulse Gout [k-1]. The signal applied to the start controller T1 is not limited to the (k-1) th scan pulse Gout [k-1] and may be any one of the previous scan pulses.

The reset unit T2 includes a gate electrode connected to the QB node, a drain electrode connected to the Q node, and a source electrode connected to a low potential voltage (VGL) input terminal. The reset section T2 responds to the QB node and discharges the Q node to the low potential voltage VGL.

The third transistor T3 includes a gate electrode and a drain electrode connected to the input terminal of the third clock signal CLK3, and a source electrode connected to the QB node. The third transistor T3 applies a turn-on voltage to the QB node at the timing when the third clock signal CLK3 is applied.

The fourth transistor T4 includes a gate electrode receiving the start pulse VST or the (k-1) th scan pulse Gout [k-1], a drain electrode connected to the QB node, And a source electrode connected to the source electrode. The fourth transistor T4 discharges the QB node to the low potential voltage VGL at the timing when the Q node is precharged by the start pulse VST or the (k-1) th scan pulse Gout [k-1] .

The fifth transistor T5 includes a gate electrode connected to the input terminal of the first APO signal APO1, a drain electrode connected to the Q node, and a source electrode connected to the input terminal of the low potential voltage VGL. The fifth transistor T5 responds to the first APO signal APO1 to discharge the Q node to the low potential voltage VGL.

The sixth transistor T6 includes a gate electrode connected to the input terminal of the first APO signal APO1, a drain electrode connected to the QB node, and a source electrode connected to the input terminal of the low potential voltage VGL. The sixth transistor T6 responds to the first APO signal APO1 to discharge the QB node to the low potential voltage VGL.

The seventh transistor T7 includes a gate electrode and a drain electrode connected to the input terminal of the second APO signal APO2, and a source electrode connected to the output terminal Nout. The seventh transistor T7 applies a turn-on voltage to the output terminal Nout in response to the second APO signal APO2.

The pull-up transistor Tpu includes a gate electrode connected to the Q node, a drain electrode connected to the input terminal of the first clock signal (CLK1), and a source electrode connected to the output terminal Nout.

The pull-down transistor Tpd includes a gate electrode connected to the QB node, a drain electrode connected to the output terminal Nout and a source electrode connected to the input terminal of the low potential voltage VGL.

The first capacitor CQ stably maintains the voltage of the Q node, and the second capacitor CQB stably maintains the voltage of the QB node.

Hereinafter, an operation in each driving mode of the gate driver constituted by the stages shown in FIG. 5 and an operation in the abnormal power-off state will be described.

≪ Operation of Gate Driver in First Drive Mode >

6 is a timing chart showing the output timing of the clock signal input to the stage and the gate pulse in the first driving mode. Hereinafter, the stage for outputting the first gate pulse Gout1 in the output period of the first clock signal CLK1 will be mainly described.

The operation of the k < th > stage STG [k] will now be described with reference to FIG. 5 and FIG.

Until the first timing t1, the QB node is in a high-potential state and the second capacitor (CQB) stably maintains that the QB node is a turn-on voltage.

At the first timing t1, the start control section T1 precharges the Q node in response to the start signal VST. The start control unit T1 of the k-th stage STG [k] outputs the (k-1) -th gate pulse Gout [k] when the k-th stage STG [k] is one of the rear stages of the second stage. k-1. < / RTI >

At the second timing t2, when the first clock signal CLK1 is input to the drain electrode of the pull-up transistor Tpu, the Q node is bootstrapped according to the voltage rise of the drain electrode of the pull-up transistor Tpu . As the Q node is bootstrapped, the potential difference between the gate and the source of the pull-up transistor Tpu increases, and the pull-up transistor Tpu is turned on. As a result, the pull-up transistor Tpu charges the output terminal Nout using the first clock signal CLK1.

At the third timing t3, the first clock signal CLK1 becomes a low potential voltage and the output terminal Nout becomes a turn-off voltage.

At the third timing t4, the third transistor T3 charges the QB node to the turn-on voltage in response to the third clock signal CLK3. The reset section T2 discharges the Q node to the low potential voltage VSS in response to the QB node voltage.

≪ Operation of Gate Driver in Second Drive Mode >

7 is a diagram showing drive signals in the second drive mode. 7, the first horizontal period (1st H) is a period during which the data voltage is supplied to the first pixel line HL1, and the n-th horizontal period (nth H) is a period during which the data voltage .

Referring to FIG. 5 and FIG. 7, the operation in the second drive mode will be described below.

In the second drive mode, the second APO signal APO2 maintains a turn-off voltage. As a result, the seventh transistor T7 does not operate and maintains the turn-off state.

The start control unit T1 of the first stage STG1 precharges the Q node in response to the start signal VST. During the first horizontal period (1st H), the first stage (STG1) outputs the first gate pulse (Gout1) during the output period of the first clock signal (CLK1). The operation of the first stage STG1 to output the first gate pulse Gout1 is the same as the operation of the k-th stage STG [k] described above.

Similarly, during the second horizontal period (2nd H), the second stage STG2 outputs the second gate pulse Gout2 during the output period of the second clock signal CLK2.

As described above, the first to (k-1) th stages STG1 to STG [k-1] are driven during the first to (k-1) 1 to (k-1) gate pulses Gout1 to Gout [k-1]. As a result, the first to (k-1) th pixel lines HL1 to HL [k-2] are turned on during the first to (k-1) Displays an image.

The mode control unit 20 generates the gate stop signal Gstop in the (k-1) th horizontal period ([k-1] th H). The timing signal generator 100 stops the output of the clock signal CLK in response to the gate stop signal Gstop. As a result, the gate driver 120 does not receive the clock signal CLK.

Then, the mode control unit 20 generates the first APO signal APO1 in the k-th horizontal period (kthH). The fifth transistor T5 and the sixth transistor T6 of the k-th stage STG [k] are turned on in response to the first APO signal APO1. As a result, the Q node and the QB node of the k-th stage STG [k] are discharged with the turn-off voltage, the transistors belonging to the k-th stage STG [k] are reset, and the operation is stopped. The (k + 1) -th stage STG [k + 1] to the n-th stage STG [n] do not generate the gate pulse because the k-th stage STG [k] stops operating.

The timing signal generator 100 does not supply the video data to the data driver 110 from the kth horizontal period (kth H). As a result, the data driver 110 does not generate the data voltage from the kth horizontal period (kth H).

Thus, the present invention does not drive the pixels belonging to the second display area AA2 in the second drive mode. The present invention does not write black image data to display a black screen in the second display area AA2 but stops the image display function at all. That is, since the present invention stops the output of the clock signal applied to the gate driver 120 and the data voltage applied to the data driver 110, the power consumption can be reduced.

In particular, the present invention stabilizes the operation of the gate driver 120 by initializing the Q-node and the QB node of the k-th stage STG [k] to a turn-off voltage in addition to stopping the clock signal of the gate driver 120 . If the voltages of the Q node and the QB node are not initialized to the mode turn-off voltage, the main node voltage of the stage becomes unstable, so that the gate pulse can be outputted even if the clock signal is not applied to the stage. On the other hand, since the present invention resets the Q-node and the QB node of the stage STG [k] driving the first pixel line of the second display area AA2 to the turn-off voltage, the stage outputs the gate pulse The operation can be prevented.

In addition, the present invention can drive the entire display unit AA or drive only a part of the display unit AA by using only one shift register constituting the gate driving unit, and distinguishing between the first driving mode and the second driving mode.

≪ Operation in abnormal power off state >

8 is a diagram showing generation of an abnormal power-off detection signal.

Referring to FIGS. 5 and 8, the abnormal power-off detection unit 30 detects a voltage level of one or more of the input power sources. The abnormal power off detection unit 30 generates the first and second APO signals APO1 and APO2 when the input power source is equal to or less than a preset threshold value Vr.

The gate driver 120 discharges the gate lines GL in response to the first and second APO signals APO1 and APO2. Specifically, the fifth to seventh transistors T5 to T7 of the first to n-th stages STG1 to STG [n] are turned on. The fifth transistor T5 resets the Q node to a turn-off voltage in response to the first APO signal APO1 and the sixth transistor T6 turns the QB node in response to the first APO signal APO1. Reset to off-voltage. That is, the Q node and the QB node are discharged with the turn-off voltage by the first APO signal APO1. The seventh transistor T7 applies a high potential voltage to the output terminal Nout in response to the second APO signal APO2. As a result, the transistors connected to the gate line GL in the pixels P are turned on, and the voltage charged in the pixels P is discharged.

The data driver 110 discharges the data lines DL in response to the first APO signal or the second APO signal.

The power supply unit 10 discharges the output terminals when the first APO signal or the second APO signal is generated.

The common voltage Vcom and the on / off voltages VGH and VGL of the TFT T are changed to the ground voltage GND-0V when the DC input power supply Vin such as AVDD, AVEE, VDDI is abnormally lowered, So that the voltage of the capacitor is discharged.

As a result, the display device of the present invention discharges all the wirings connected to the pixels when it is determined that the input power supply Vin is abnormally cut off, thereby preventing afterimage and smudge. If a voltage remains in the gate driver 120 and the pixels P, when the display device resumes normal operation, the pixels P may emit light at an undesired moment and cause a flicker phenomenon. In contrast, according to the present invention, by discharging the voltage between the gate driver 120 and the display panel PNL using the abnormal power-off detection unit 30, it is possible to prevent a flicker phenomenon that may occur at the time of re-starting the display device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL: Display panel DIC: Drive IC
10: power supply unit 20: mode control unit
30: abnormal power-off detection unit 100: timing signal generator
110: Data driver 120: Gate driver

Claims (12)

A display panel having gate lines and data lines connected to the pixels and having a display section divided into a first display area and a second display area;
Wherein each of the stages includes a gate driver for outputting a gate pulse applied to the gate lines through an output terminal in response to a voltage of the Q node; And
And displays the image in the first and second display areas in the first drive mode and displays the preset information in the first display area in the second drive mode and drives the second display area in the second drive mode And for initializing the Q node of at least one of the stages among the stages to be turned off. The method according to claim 1,
The first gate driver
First to (k-1) (k is a natural number) stage for supplying gate pulses to the first display region; And
(N is a natural number greater than k) for supplying gate pulses to the second display region,
And the mode control unit initializes the voltage of the Q node of the k-th stage. 3. The method of claim 2,
The mode control unit outputs a first APO signal at the time when the k-th stage is driven,
Each of the stages
And a Q-node discharging unit including a gate electrode receiving the first APO signal, a drain electrode connected to the Q-node, and a source electrode connected to an input terminal of a turn-off voltage. The method of claim 3,
Each of the stages
A pull-down transistor responsive to a QB node voltage having a voltage level opposite to the Q node, for applying a turn-off voltage to the output terminal; And
And a QB node discharger comprising a gate electrode receiving the first APO signal, a drain electrode connected to the QB node, and a source electrode connected to an input terminal of a turn-off voltage. The method according to claim 1,
An abnormal power off detection unit for monitoring the input power source and generating the first APO signal and the second APO signal when the input power source is below a predetermined threshold value; And
And an output terminal discharge unit for applying a turn-on voltage to the output terminal in response to the second APO signal. 3. The method of claim 2,
Wherein the first to n-th stages sequentially receive clock signals having the same phase and delayed by the same time. The method according to claim 6,
The mode control unit
And the clock signals applied to the k-th stage to the n-th stage are maintained at a turn-off voltage level. 8. The method of claim 7,
And a data driver for supplying a data voltage in synchronization with the gate pulse to the data line,
Wherein the data driver holds the data voltage written in the second display region in the second drive mode at a ground voltage. A gate driver for generating a gate pulse to be supplied to a gate line of a display panel, the gate driver comprising a plurality of stages,
A start controller for charging the Q node;
A pull-up transistor responsive to the voltage of the Q node for applying a turn-on voltage to an output terminal; And
And a Q node discharging unit responsive to the first APO signal for discharging the Q node to a turn-off voltage,
The first APO signal is applied as a turn-on voltage when the output of the gate pulse is stopped in accordance with the drive mode. 10. The method of claim 9,
A pull-down transistor responsive to a QB node voltage having a voltage level opposite to the Q node, for applying a turn-off voltage to the output terminal; And
And a QB node discharging unit including a gate electrode receiving the first APO signal, a drain electrode connected to the QB node, and a source electrode connected to an input terminal of a turn-off voltage. 10. The method of claim 9,
Wherein the first APO signal is applied at a turn-on voltage when the input power is below a preset threshold value. 12. The method of claim 11,
In response to a second APO signal, an output end discharge unit for applying a turn-on voltage to the output end,
And the second APO signal is a turn-on voltage when the input power source is below the threshold value.

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