CN111025808B - Display panel, working method thereof and display device - Google Patents
Display panel, working method thereof and display device Download PDFInfo
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- CN111025808B CN111025808B CN201911388487.4A CN201911388487A CN111025808B CN 111025808 B CN111025808 B CN 111025808B CN 201911388487 A CN201911388487 A CN 201911388487A CN 111025808 B CN111025808 B CN 111025808B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a display panel, a working method thereof and a display device, wherein the display panel is provided with a picture to be displayed, and the picture to be displayed comprises a first area and a second area; the display panel comprises a plurality of gate lines and a plurality of data lines, wherein the gate lines and the data lines are crossed to define sub-pixels; the brightness of the first area is less than that of the second area, or the data voltage input in the sub-pixels in the first area is negative voltage; the gate lines include first gate lines and second gate lines, the gate lines penetrating the first region being the first gate lines and transmitting a first output voltage to at least one of the first gate lines, the gate lines penetrating the second region being the second gate lines and transmitting a second output voltage to the second gate lines; the data voltage transmitted by the data lines to the sub-pixels of the first region is less than the data voltage transmitted by the data lines to the sub-pixels of the second region; the first output voltage is less than the second output voltage. The invention solves the technical problem of larger power consumption of the array substrate in a row driving mode.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a working method thereof and a display device.
Background
With the progress of technology, the development of the display technology field in recent years shows a trend of high integration and low cost, and most display devices such as liquid crystal display panels adopt the GOA (gate driver on array) technology, which is a technology that the GOA circuits for driving the gate lines are disposed on two sides of the effective display area of the array substrate of the display device.
In the prior art, a driving mode of a display panel is basically that a driving chip outputs a clock signal to drive a shift register circuit on the display panel to output a GOUT signal step by step, then gates of thin film transistors in a display area are opened line by line, and at the moment, a source electrode of the thin film transistor outputs a data voltage signal to charge a pixel, so that display is realized.
Disclosure of Invention
In view of the above, the present invention provides a display panel, a working method thereof and a display device, so as to solve the technical problem of large power consumption in a row driving mode of an array substrate.
In one aspect, the present invention provides a display panel, which has a to-be-displayed picture, wherein the to-be-displayed picture includes a first area and a second area;
the display panel comprises a plurality of gate lines extending along a first direction and arranged along a second direction and a plurality of data lines extending along the second direction and arranged along the first direction, the gate lines and the data lines are crossed to define sub-pixels, and the first direction and the second direction are crossed;
the brightness of the first area is less than that of the second area, or the data voltage input into the sub-pixels in the first area is a negative voltage;
the gate lines include a first gate line and a second gate line, the gate lines penetrating the first region are the first gate lines and transmit a first output voltage to at least one of the first gate lines, and the gate lines penetrating the second region are the second gate lines and transmit a second output voltage to the second gate lines;
the data lines transmit data voltages to the sub-pixels of the first region which are less than the data voltages transmitted to the sub-pixels of the second region;
the first output voltage is less than the second output voltage.
On the other hand, the invention also provides a working method of the display panel, wherein the display panel is the display panel, and the working method comprises the following steps:
determining a first area and a second area, wherein the brightness of the first area is smaller than that of the second area, or the polarity of the sub-pixels in the first area is negative;
transmitting a first output voltage to at least one of the first gate lines and a second output voltage to the second gate line, the first output voltage being less than the second output voltage;
and transmitting data voltages to the sub-pixels through the data lines, wherein the data voltages transmitted to the sub-pixels of the first region are less than the data voltages transmitted to the sub-pixels of the second region through the data lines.
Meanwhile, the invention also provides a display device which comprises the display panel.
Compared with the prior art, the display panel, the working method thereof and the display device provided by the invention at least realize the following beneficial effects:
the display panel is provided with a picture to be displayed, wherein the picture to be displayed comprises a first area and a second area, the brightness of the first area is less than that of the second area, or the data voltage input in the sub-pixels in the first area is negative voltage; the gate lines include first gate lines and second gate lines, the gate lines penetrating the first region being the first gate lines and transmitting a first output voltage to at least one of the first gate lines, the gate lines penetrating the second region being the second gate lines and transmitting a second output voltage to the second gate lines; the data voltage transmitted by the data lines to the sub-pixels of the first region is less than the data voltage transmitted by the data lines to the sub-pixels of the second region; the first output voltage is less than the second output voltage. In the invention, the data voltage transmitted by the data line to the sub-pixels of the first area is less than the data voltage transmitted by the data line to the sub-pixels of the second area, so that the voltage of at least one first gate line in the first area can be reduced, and the power consumption of the display panel can be reduced on the basis of not influencing the display effect of the display panel.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a planar structure of a display panel according to the present invention;
FIG. 2 is a timing diagram of driving the display panel of FIG. 1;
FIG. 3 is a schematic plane view of another display panel according to the present invention;
FIG. 4 is a timing diagram of driving the display panel of FIG. 3;
FIG. 5 is a schematic plane view of another display panel according to the present invention;
FIG. 6 is a schematic plane structure diagram of another display panel provided by the present invention;
FIG. 7 is a schematic plan view of another display panel provided in the present invention;
FIG. 8 is a schematic plane structure diagram of another display panel provided by the present invention;
FIG. 9 is a schematic plan view of a display panel according to another embodiment of the present invention;
FIG. 10 is a schematic plan view of a display panel according to another embodiment of the present invention;
FIG. 11 is a schematic plan view of a display panel according to another embodiment of the present invention;
FIG. 12 is a schematic plan view of a display panel according to another embodiment of the present invention;
FIG. 13 is a flowchart of a method for operating a display panel according to the present invention;
fig. 14 is a schematic plan view of a display device according to the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1 to 4, fig. 1 is a schematic plane structure diagram of a display panel according to the present invention, fig. 2 is a timing diagram of driving the display panel of fig. 1, fig. 3 is a schematic plane structure diagram of another display panel according to the present invention, and fig. 4 is a timing diagram of driving the display panel of fig. 3.
The display panel 100 in fig. 1 and 3 has a to-be-displayed picture, which includes a first region 1 and a second region 2; the display panel 100 includes a plurality of gate lines 3 extending along a first direction X and arranged along a second direction Y, and a plurality of data lines 4 extending along the second direction Y and arranged along the first direction X, the gate lines 3 and the data lines 4 crossing to define sub-pixels 5, and the first direction X and the second direction Y crossing.
The luminance of the first region 1 in fig. 1 is less than the luminance of the second region 2. The data voltage inputted in the sub-pixel 5 in the first region 1 in fig. 3 is a negative voltage.
In fig. 1 and 3, the gate lines 3 include first gate lines 6 and second gate lines 7, the gate lines penetrating the first area 1 are the first gate lines 6, and transmit a first output voltage to at least one of the first gate lines 6, and the gate lines penetrating the second area 7 are the second gate lines 7, and transmit a second output voltage to the second gate lines 7; the data voltage transmitted by the data line 4 to the sub-pixels 5 of the first region 1 is less than the data voltage transmitted by the data line 4 to the sub-pixels 5 of the second region 2; the first output voltage is less than the second output voltage.
Referring to fig. 1, the gate line 3 of fig. 1 includes a first gate line 6 and a second gate line 7, the gate line penetrating the first area 1 is the first gate line 6, and transmits a first output voltage to at least one first gate line 6, and the gate line penetrating the second area 7 is the second gate line 7, and transmits a second output voltage to the second gate line 7; the data voltage transmitted by the data line 4 to the sub-pixels 5 of the first region 1 is less than the data voltage transmitted by the data line 4 to the sub-pixels 5 of the second region 2; the first output voltage is less than the second output voltage, and the brightness of the first region 1 is less than that of the second region 2. Of course, any one or more first gate lines 6 transmitting the first output voltage in fig. 1 may be used, for example, any one of the first gate lines 61 to 63 in fig. 1 may input the first output voltage, and the first output voltage is input to the first gate line 6 during driving, at this time, the gate of the thin film transistor in the sub-pixel 5 is turned on, the data line 4 inputs the data voltage to the source of the thin film transistor, and the drain of the thin film transistor supplies the data voltage to the pixel electrode 8 in the sub-pixel 5, so that the sub-pixel 5 performs display. It should be noted that, since the process of transmitting the voltages by the gate lines is driven row by row, the data voltages transmitted by the data lines 4 to the sub-pixels 5 of the first area 1 can be smaller than the data voltages transmitted by the data lines 4 to the sub-pixels 5 of the second area 2.
In fig. 1, since the luminance of the first area 1 is less than that of the second area 2, that is, the data voltage transmitted by the data line 4 to the sub-pixel 5 of the first area 1 is less than the data voltage transmitted by the data line 4 to the sub-pixel 5 of the second area 2, the output voltage of the first gate line 6 can be reduced at this time because the data voltage transmitted by the data line 4 to the sub-pixel 5 in the first area 1 is reduced, and the power consumption of the display panel can be reduced without affecting the display effect of the display panel.
For the thin film transistor in the sub-pixel 5, the voltage difference between the gate and the source (i.e. the gate-source voltage) determines the turn-on degree of the thin film transistor, and since the gate voltage and the source voltage are reduced in the first region 1 at the same time, the gate-source voltage Vgs of the thin film transistor is not changed substantially, and the display screen is not affected.
Because the first output voltage is lower than the second output voltage, that is, the output voltage transmitted by the at least one first gate line 6 is reduced, the power consumption of the display panel can be reduced on the basis of not influencing the display effect of the display panel. Referring to fig. 2, fig. 2 is a driving timing diagram of the display panel of fig. 1, and it can be seen in fig. 2 that voltages of the first gate line 62 and the first gate line 63 in the first region 1 are reduced, that is, the first output voltage is input to the first gate line 62 and the first gate line 63, and the first output voltage is less than the second output voltage, thereby achieving reduction of power consumption. Of course, the output voltages of the first gate line 61, the first gate line 62 and the first gate line 63 may all be reduced, which is not limited herein.
Referring to fig. 3, the gate line 3 of fig. 3 includes a first gate line 6 and a second gate line 7, the gate line penetrating the first area 1 is the first gate line 6, and transmits a first output voltage to at least one first gate line 6, and the gate line penetrating the second area 7 is the second gate line 7, and transmits a second output voltage to the second gate line 7; the data voltage transmitted by the data line 4 to the sub-pixels 5 of the first region 1 is less than the data voltage transmitted by the data line 4 to the sub-pixels 5 of the second region 2; in fig. 3, the data voltage inputted to the sub-pixel 5 in the first region 1 is a negative voltage, that is, the polarity of the sub-pixel 5 is a negative polarity. In the driving process, a first output voltage is input into the first gate line 6, at this time, the gate of the thin film transistor in the sub-pixel 5 is turned on, the data line 4 inputs a data voltage to the source of the thin film transistor, the drain of the thin film transistor supplies the data voltage to the pixel electrode 8 in the sub-pixel 5, and the sub-pixel 5 performs display, it should be noted that since the gate line transmission process is driven row by row, the data voltage transmitted from the data line 4 to the sub-pixel 5 in the first area 1 can be smaller than the data voltage transmitted from the data line 4 to the sub-pixel 5 in the second area 2. It should be noted that the data voltage inputted to the sub-pixel 5 in the first region 1 is considered to be smaller than the data voltage inputted to the sub-pixel 5 in the second region 2 when the data voltage inputted to the sub-pixel 5 in the first region 1 is negative voltage, for example, the data voltage inputted to the sub-pixel 5 in the first region 1 is-5V, while the data voltage inputted to the sub-pixel 5 in the second region 2 is +5V, and +5V is larger than-5V. In this embodiment, the data voltage input to the sub-pixel 5 in the first area 1 is a negative voltage, that is, the data voltage transmitted from the data line 4 to the sub-pixel 5 in the first area 1 is less than the data voltage transmitted from the data line 4 to the sub-pixel 5 in the second area 2, and since the data voltage transmitted from the data line 4 to the sub-pixel 5 in the first area 1 is reduced, the output voltage of the first gate line 6 can be reduced at this time, for the thin film transistor in the sub-pixel 5, the voltage difference between the gate and the source (i.e., the gate-source voltage) determines the turn-on degree of the thin film transistor, and since the voltages of the gate and the source are reduced in the first area 1, the gate-source voltage is not changed substantially, and the display screen is not affected.
For example, the display panel 100 in fig. 3 is illustrated, for example, the data voltage transmitted to the sub-pixel 5 in the first region 1 is-3V, the data voltage transmitted to the sub-pixel 5 in the second region 2 is 3V, the first input voltage is 2V, and the second input voltage is 8V, so that the gate-source voltage of the tft in the first region 1 is 2- (-3) to 5V, the gate-source voltage of the tft in the second region 2 is also 5V, and the turn-on degree of the tft in the first region 1 is the same as the turn-on degree of the tft in the second region 2.
Thus, the data voltage inputted to the sub-pixel 5 in the first region 1 is a negative voltage, and since the first output voltage is lower than the second output voltage, that is, the output voltage transmitted by at least one first gate line 6 is reduced, the power consumption of the display panel can be reduced without affecting the display effect of the display panel.
Referring to fig. 4, fig. 4 is a driving timing diagram of the display panel in fig. 3, and it can be seen in fig. 4 that the polarity of the sub-pixels in the first area 1 is reduced to negative polarity, and the output voltages of the first gate line 61, the first gate line 62, and the first gate line 63 are reduced, that is, the first output voltage is input to the first gate line 61, the first gate line 62, and the first gate line 63, and the first output voltage is smaller than the second output voltage, so that the power consumption of the display panel can be reduced without affecting the display effect of the display panel.
Compared with the display panel in the prior art, the display panel of the invention has at least the following beneficial effects:
the display panel is provided with a picture to be displayed, wherein the picture to be displayed comprises a first area and a second area, the brightness of the first area is less than that of the second area, or the data voltage input in the sub-pixels in the first area is negative voltage; the gate lines include first gate lines and second gate lines, the gate lines penetrating the first region being the first gate lines and transmitting a first output voltage to at least one of the first gate lines, the gate lines penetrating the second region being the second gate lines and transmitting a second output voltage to the second gate lines; the data voltage transmitted by the data lines to the sub-pixels of the first region is less than the data voltage transmitted by the data lines to the sub-pixels of the second region; the first output voltage is less than the second output voltage. In the invention, the data voltage transmitted by the data line to the sub-pixels of the first area is less than the data voltage transmitted by the data line to the sub-pixels of the second area, so that the voltage of at least one first gate line in the first area can be reduced, and the power consumption of the display panel can be reduced on the basis of not influencing the display effect of the display panel.
In some alternative embodiments, with continued reference to fig. 1 and 3, each sub-pixel 5 includes a thin film transistor 9 and a pixel electrode 8, the thin film transistor 9 has a control terminal, an input terminal, and an output terminal (not shown in the figures), the sub-pixel 5 includes a first sub-pixel 51 located in the first region 1 and a second sub-pixel 52 located in the second region 2, the first sub-pixel 51 includes a first thin film transistor 10 and a first pixel electrode 81, and the second sub-pixel 11 includes a second thin film transistor 11 and a second pixel electrode 82.
The control end of the first thin film transistor 10 is electrically connected with the first gate line 6, the input end of the first thin film transistor 10 is electrically connected with the data line 4, and the output end of the first thin film transistor 10 is electrically connected with the first pixel electrode 81;
a control terminal of the second thin film transistor 11 is electrically connected to the second gate line 7, an input terminal of the second thin film transistor 11 is electrically connected to the data line 4, and an output terminal of the second thin film transistor 11 is electrically connected to the second pixel electrode 82;
the gate-source voltage of the first thin film transistor 10 electrically connected to the first gate line 6 transmitting the first output voltage is equal to the gate-source voltage of the second thin film transistor 11 within a preset range.
It can be understood that, since the data voltage transmitted by the data line 4 to the first pixel electrode 81 in the first region 1 is reduced, the output voltage of the first gate line 6 can be reduced, that is, the first output voltage is transmitted to the first gate line 6, for the first thin film transistor 10 in the first sub-pixel 51, the voltage difference between the gate and the source (that is, the gate-source voltage) determines the turn-on degree of the first thin film transistor 10, and since the gate voltage and the source voltage are reduced in the first region 1 at the same time, the gate-source voltage Vgs of the first thin film transistor 10 is not substantially changed, and is equal to the gate-source voltage Vgs of the second thin film transistor 11 in the preset range, which does not affect the display screen, and can reduce power consumption.
Note that the preset range here is that the gate-source voltage of the first thin film transistor 10 electrically connected to the first gate line 6 transmitting the first output voltage is substantially the same as the gate-source voltage of the second thin film transistor 11, not absolutely equal.
With continued reference to fig. 1 and fig. 5, fig. 5 is a schematic plan view of another display panel provided by the present invention, when the luminance of the first region 1 is less than the luminance of the second region 2, the number of sub-pixels covered by the first region 1 in the same row of sub-pixels is at least greater than 2/3 of the total number of sub-pixels in the same row.
In the same row of sub-pixels in fig. 1, the number of sub-pixels covered by the first area 1 is greater than 2/3, and in fig. 5, the number of sub-pixels covered by the first area 1 is equal to the total number of sub-pixels in the same row, i.e. completely covers a whole row of sub-pixels.
It can be understood that, for the output voltage transmitted by at least one first gate line 6 in the first area 1 being the first output voltage, in the same row of sub-pixels, the portion of sub-pixels not covered by the first area 1 is also the first output voltage, and at this time, the data voltage of the portion of sub-pixels not covered by the first area 1 does not change, so the gate-source voltage of the thin film transistor of the portion of sub-pixels not covered by the first area 1 will decrease, so that the portion of sub-pixels not covered by the first area 1 will be dark, and the number of sub-pixels not covered by the first area 1 will not affect the display screen of the display panel when the number of sub-pixels not covered by the first area 1 is smaller, in other words, in the same row of sub-pixels, the number of sub-pixels covered by the first area 1 is at least greater than 2/3 of the total number of sub-pixels in the same row, and decreasing the output voltage transmitted by at least one first gate line 6 will not affect the display screen, and power consumption can be reduced.
With continued reference to fig. 1 and 5, the gray scale of the display in the first region 1 is between 0 and 127. For the display picture, when the display gray scale is between 0 and 127, the display picture is a dark picture, and when the display picture is a dark picture, the data voltage transmitted from the data line 4 to the sub-pixel 5 of the first area 1 can be reduced, on the basis, the output voltage transmitted from the first gate line 6 can be reduced, but the display picture is not affected, and the power consumption can be reduced.
With continued reference to fig. 1 and 5, the first zone 1 and the second zone 2 are arranged in a second direction.
As can be seen from fig. 1 and 5, the first region 1 and the second region 2 are arranged along the second direction Y, and at this time, the data voltage transmitted by the data line 4 to the sub-pixel 5 of the first region 1 is less than the data voltage transmitted by the data line 4 to the sub-pixel 5 of the second region 2, so that the output voltage transmitted by the first gate line 6 can be reduced, and the power consumption of the display panel can be reduced without affecting the display effect of the display panel.
For the output voltage transmitted by at least one first gate line 6 in the first area 1 to be the first output voltage, in the same row of sub-pixels, the portion of sub-pixels not covered by the first area 1 is also the first output voltage, and at this time, the data voltage of the portion of sub-pixels not covered by the first area 1 does not change, so the gate-source voltage of the thin film transistor of the portion of sub-pixels not covered by the first area 1 will be reduced, so that the portion of sub-pixels not covered by the first area 1 will be darkened, and the display frame of the display panel will not be affected when the number of sub-pixels not covered by the first area 1 is smaller, in other words, in the same row of sub-pixels, the number of sub-pixels covered by the first area 1 is at least greater than 2/3 of the total number of sub-pixels in the same row, and reducing the output voltage transmitted by at least one first gate line 6 will not affect the display frame, and power consumption can be reduced.
Of course, in some alternative embodiments, the first region 1 and the second region 2 may also be arranged along the first direction X, and are not limited herein.
Referring to fig. 6, fig. 6 is a schematic plan view illustrating a display panel according to still another embodiment of the present invention, in which the polarities of the data voltages input to the sub-pixels in two adjacent columns in fig. 6 are opposite.
It can be understood that the driving manner of the display panel in this embodiment is column inversion. For the display panel with reversed columns, the data voltage transmitted by the data line 4 to the sub-pixel 5 of the first area 1 is less than the data voltage transmitted by the data line 4 to the sub-pixel 5 of the second area 2, the output voltage of the first gate line 6 in the first area 1 is reduced, the power consumption of the display panel is reduced on the basis of not influencing the display effect of the display panel, and meanwhile, the brightness of the first area 1 can be made less than that of the second area 2 by adjusting the magnitude of the data voltage, so that the purpose of reducing the power consumption is achieved. Referring to fig. 7, fig. 7 is a schematic plan view of another display panel provided by the present invention, in which the data voltage input to any sub-pixel 5 in fig. 7 is opposite in polarity to the data voltage input to the adjacent sub-pixel 5.
It can be understood that the driving method of the display panel in this embodiment is dot inversion, for the dot-inverted display panel, the data voltage transmitted by the data line 4 to the sub-pixel 5 of the first area 1 is less than the data voltage transmitted by the data line 4 to the sub-pixel 5 of the second area 2, the output voltage of the first gate line 6 in the first area 1 can be reduced, the power consumption of the display panel can be reduced on the basis of not affecting the display effect of the display panel, and meanwhile, the brightness of the first area 1 is less than the brightness of the second area 2 by adjusting the magnitude of the data voltage, so as to achieve the purpose of reducing the power consumption.
Compared with the prior art, the data voltage transmitted by the data line 4 to the sub-pixel 5 in the first area 1 is less than the data voltage transmitted by the data line 4 to the sub-pixel 5 in the second area 2, so that the output voltage of the first gate line 6 in the first area 1 is reduced, and the method is suitable for not only a display panel with reversed columns but also a display panel with reversed dots, and has wider applicability.
Referring to fig. 8, fig. 8 is a schematic plan view of another display panel provided in the present invention, when the data voltage input to the sub-pixel 5 in the first region 1 is a negative voltage, the data voltage input to the sub-pixel in the second region 2 is a positive voltage; the first region 1 covers a row of sub-pixels.
In this embodiment, the first region 1 only covers one row of sub-pixels 5, and the sub-pixels 5 in the first region 1 are negative in polarity, that is, the data voltage inputted to the sub-pixels 5 in the first region 1 is a negative voltage, at this time, the polarity of the sub-pixel in the second region 2 in the display panel is positive, that is, the data voltage inputted to the sub-pixel 5 in the first region 1 is positive, in the driving process, a first output voltage is input into the first gate line 6, when the gate of the thin film transistor in the sub-pixel 5 is turned on, the data line 4 inputs a data voltage to the source of the thin film transistor, the drain of the thin film transistor supplies the data voltage to the pixel electrode 8 in the sub-pixel 5, and the sub-pixel 5 displays, it should be noted that since the process of transmitting the voltage by the gate line is driven row by row, it can be achieved that the data voltage transmitted from the data line 4 to the sub-pixels 5 of the first region 1 is less than the data voltage transmitted from the data line 4 to the sub-pixels 5 of the second region 2. In this embodiment, the data voltage inputted to the sub-pixel 5 in the first region 1 is a negative voltage, that is, the data voltage transmitted from the data line 4 to the sub-pixel 5 in the first region 1 is reduced, and since the data voltage transmitted from the data line 4 to the sub-pixel 5 in the first region 1 is reduced, the output voltage of the first gate line 6 can be reduced at this time, for the thin film transistor in the sub-pixel 5, the voltage difference between the gate and the source (that is, the gate-source voltage) determines the turn-on degree of the thin film transistor, and since the voltage of the gate and the source is reduced in the first region 1, the gate-source voltage is not changed substantially, and the display screen is not affected.
Thus, the data voltage inputted to the sub-pixel 5 in the first region 1 is a negative voltage, and since the first output voltage is lower than the second output voltage, that is, the output voltage transmitted by at least one first gate line 6 is reduced, the power consumption of the display panel is reduced on the basis of not affecting the display effect of the display panel.
In some optional embodiments, when the data voltage input in the sub-pixel in the first region is a negative voltage, the data voltage input in the sub-pixel in the second region is a positive voltage; the first area covers at least two adjacent rows of sub-pixels.
Referring to fig. 9, fig. 9 is a schematic plan view of another display panel provided by the present invention, in fig. 9, when the data voltage input to the sub-pixel 5 in the first region 1 is a negative voltage, the data voltage input to the sub-pixel 5 in the second region 2 is a positive voltage, fig. 9 only shows that the first region 1 covers four adjacent rows of sub-pixels, but certainly, the first region 1 may also cover two adjacent rows of sub-pixels, three adjacent rows of sub-pixels, or more than four adjacent rows of sub-pixels, which is not limited in this respect.
The sub-pixels 5 in the first region 1 are of negative polarity, i.e. the data voltage inputted in the sub-pixels 5 in the first region 1 is of negative voltage, at this time, the polarity of the sub-pixels in the second area 2 in the display panel is positive, that is, the data voltage inputted to the sub-pixels 5 in the first area 1 is negative, in the driving process, a first output voltage is input into the first gate line 6, when the gate of the thin film transistor in the sub-pixel 5 is turned on, the data line 4 inputs a data voltage to the source of the thin film transistor, the drain of the thin film transistor supplies the data voltage to the pixel electrode 8 in the sub-pixel 5, and the sub-pixel 5 displays, it should be noted that since the process of transmitting the voltage by the gate line is driven row by row, it can be achieved that the data voltage transmitted from the data line 4 to the sub-pixels 5 of the first region 1 is less than the data voltage transmitted from the data line 4 to the sub-pixels 5 of the second region 2. In this embodiment, the data voltage inputted to the sub-pixel 5 in the first region 1 is a negative voltage, that is, the data voltage transmitted from the data line 4 to the sub-pixel 5 in the first region 1 is reduced, and the data voltage transmitted from the data line 4 to the sub-pixel 5 in the first region 1 is reduced, so that the output voltage of the first gate line 6 can be reduced, and for the thin film transistor in the sub-pixel 5, the voltage difference between the gate and the source (that is, the gate-source voltage) determines the turn-on degree of the thin film transistor, and since the voltage of the gate and the source is reduced in the first region 1, the gate-source voltage is not changed substantially, and the display screen is not affected.
Thus, the data voltage inputted to the sub-pixel 5 in the first region 1 is a negative voltage, and since the first output voltage is lower than the second output voltage, that is, the output voltage transmitted by at least one first gate line 6 is reduced, the power consumption of the display panel is reduced on the basis of not affecting the display effect of the display panel.
Referring to fig. 10 and 11, fig. 10 is a schematic plan view illustrating a display panel according to still another embodiment of the present invention, and fig. 11 is a schematic plan view illustrating a display panel according to still another embodiment of the present invention, in which the first regions and the second regions are alternately arranged along the second direction.
Referring to fig. 10, the gate line 3 of fig. 10 includes first gate lines 6 and second gate lines 7, the gate lines penetrating the first area 1 are the first gate lines 6, and transmit a first output voltage to at least one of the first gate lines 6, and the gate lines penetrating the second area 7 are the second gate lines 7, and transmit a second output voltage to the second gate lines 7; the data voltage transmitted by the data line 4 to the sub-pixels 5 of the first region 1 is less than the data voltage transmitted by the data line 4 to the sub-pixels 5 of the second region 2; the first output voltage is less than the second output voltage, and the brightness of the first region 1 is less than that of the second region 2. The first regions 1 and the second regions 2 are arranged to overlap in the second direction Y. Since the luminance of the first region 1 is less than that of the second region 2, the data voltage transmitted by the data line 4 to the sub-pixels 5 in the first region 1 can be reduced, and since the data voltage transmitted by the data line 4 to the sub-pixels 5 in the first region 1 is reduced, the output voltage of the first gate line 6 can be reduced at this time, for the thin film transistor in the sub-pixel 5, the voltage difference between the gate and the source (i.e. the gate-source voltage) determines the turn-on degree of the thin film transistor, and since the gate voltage and the source voltage are reduced in the first region 1 at the same time, the gate-source voltage Vgs of the thin film transistor is not changed basically, and the display picture is not affected. In this way, since the first output voltage is lower than the second output voltage, that is, the output voltage transmitted by the at least one first gate line 6 is reduced, the power consumption of the display panel is reduced on the basis of not affecting the display effect of the display panel.
Referring to fig. 11, the gate line 3 of fig. 11 includes a first gate line 6 and a second gate line 7, the gate line penetrating the first area 1 is the first gate line 6, and transmits a first output voltage to at least one first gate line 6, and the gate line penetrating the second area 7 is the second gate line 7, and transmits a second output voltage to the second gate line 7; the data voltage transmitted by the data line 4 to the sub-pixels 5 of the first region 1 is less than the data voltage transmitted by the data line 4 to the sub-pixels 5 of the second region 2; the first area 1 and the second area 2 are arranged in an overlapping manner in the second direction Y, the data voltage input in the sub-pixel 5 in the first area 1 is a negative voltage, and the first output voltage is lower than the second output voltage, that is, the output voltage transmitted by at least one first gate line 6 is reduced, so that the power consumption of the display panel is reduced on the basis of not influencing the display effect of the display panel.
With continued reference to fig. 1 to 11, the data voltage transmitted from the data line 4 to the sub-pixels of the first region 1 is at least 40% or less of the data voltage transmitted from the data line 4 to the sub-pixels of the second region 2.
It can be understood that the data voltage transmitted by the data line 4 to the sub-pixels of the first region 1 is at least 40% or less of the data voltage transmitted by the data line 4 to the sub-pixels of the second region 2, at this time, the output voltage of the first gate line 6 can be reduced, for the thin film transistor in the sub-pixel 5, the voltage difference between the gate and the source (i.e., the gate-source voltage) determines the turn-on degree of the thin film transistor, and since the gate voltage and the source voltage are reduced in the first region 1 at the same time, the gate-source voltage Vgs of the thin film transistor is not substantially changed, and the display screen is not affected. Therefore, the first output voltage is lower than the second output voltage, namely, the output voltage transmitted by at least one first gate line 6 is reduced, so that the power consumption of the display panel is reduced on the basis of not influencing the display effect of the display panel.
Referring to fig. 12, fig. 12 is a schematic plan view of another display panel provided in the present invention. The display panel 100 in fig. 12 further includes a first clock signal line CKV1 and a second clock signal line CKV2 arranged in parallel, and a plurality of cascaded shift register units VSR, wherein each shift register unit VSR includes a first driving signal input terminal 12, a second driving signal input terminal 13, a driving signal output terminal 14, a shift signal input terminal 15 and a shift signal output terminal 16;
the first driving signal input end 12 is electrically connected to the first clock signal line CKV1, the second driving signal input end 13 is electrically connected to the second clock signal line CKV2, the shift signal input end 15 is connected to a shift signal, and the shift signal output end 16 is electrically connected to the shift signal input end of the next shift register unit VSR in cascade connection; the driving signal output terminal 14 is electrically connected to the first gate line or the second gate line.
The first output voltage supplied to the first gate line 6 and the second output voltage supplied to the second gate line 7 in the present invention are supplied through the cascade of shift register units VSR.
It should be noted that in fig. 12, an initial signal STV is input at the shift signal input terminal 15 of the first stage shift register unit VSR, and then sequentially transmitted through the next stage shift register unit connected thereto, and the shift signal output terminal of the previous stage shift register unit is electrically connected to the shift signal input terminal of the next stage shift register unit, so as to realize transmission of the shift signal.
It is understood that the signal sources of the first clock signal line CKV1 and the second clock signal line CKV2 are driving chips, and then driving signals are input to the gate lines row by row through the shift register units VSR. In the prior art, signals of the first clock signal line CKV1 and the second clock signal line CKV2 are input to the shift register unit, and a driving signal is output after logic operation, in other words, the driving signal output by the shift register unit is controlled by signals of the first clock signal line CKV1 and the second clock signal line CKV2, but the power voltage provided by the driving chip itself is relatively low, which cannot meet the requirement that the signals of the first clock signal line CKV1 and the second clock signal line CKV2 control the shift register unit to normally operate, so that the boosting process of the power voltage needs to be completed inside the driving chip, and the requirement that the first clock signal line CKV1 and the second clock signal can control the shift register unit to normally operate can be met. In the embodiment, the output voltage transmitted by at least one first gate line 6 is reduced, so that the power consumption of the display panel is reduced on the basis of not influencing the display effect of the display panel; in addition, the output voltage transmitted by at least one first gate line 6 is reduced, and the loss in the boosting process can be reduced, so that the power consumption is reduced, when the output voltage transmitted by the first gate line 6 is reduced to the power voltage provided by the driving chip, at the moment, the driving chip can directly provide voltage for the first clock signal line CKV1 and the second clock signal line CKV2, the boosting process is omitted, the power consumption is further reduced, and the efficiency is improved.
Referring to fig. 13, fig. 13 is a flowchart of a working method of a display panel 100 according to any of the above embodiments, where the working method includes:
s1: determining a first area and a second area, wherein the brightness of the first area is less than that of the second area, or the polarity of the sub-pixels in the first area is negative;
s2: transmitting a first output voltage to at least one first gate line and a second output voltage to a second gate line, the first output voltage being less than the second output voltage;
s3: and transmitting data voltages to the sub-pixels through the data lines, wherein the data voltages transmitted to the sub-pixels of the first region are less than the data voltages transmitted to the sub-pixels of the second region by the data lines.
In the invention, the data voltage transmitted to the sub-pixels of the first area by the data line is less than the data voltage transmitted to the sub-pixels of the second area by the data line, so that the voltage of at least one first gate line in the first area can be reduced, and the power consumption of the display panel can be reduced on the basis of not influencing the display effect of the display panel.
Based on the same inventive concept, the invention further provides a display device comprising the display panel of any of the above embodiments. Referring to fig. 14, fig. 14 is a schematic plan view of a display device according to the present invention, and a display device 200 of the present embodiment includes the display panel 100 according to any one of the embodiments. Fig. 14 illustrates the display device 200 by taking a mobile phone as an example, and it is understood that the display device 200 provided in the embodiment of the present invention may be other display devices having a display function, such as a liquid crystal panel, electronic paper, a television, an electronic watch, and an in-vehicle display device, and the present invention is not limited thereto. The display device provided in the embodiment of the present invention has the beneficial effects of the display panel provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.
According to the embodiment, the display panel, the working method thereof and the display device provided by the invention at least realize the following beneficial effects:
the display panel is provided with a picture to be displayed, wherein the picture to be displayed comprises a first area and a second area, the brightness of the first area is less than that of the second area, or the data voltage input in the sub-pixels in the first area is negative voltage; the gate lines include first gate lines and second gate lines, the gate lines penetrating the first region being the first gate lines and transmitting a first output voltage to at least one of the first gate lines, the gate lines penetrating the second region being the second gate lines and transmitting a second output voltage to the second gate lines; the data voltage transmitted by the data lines to the sub-pixels of the first region is less than the data voltage transmitted by the data lines to the sub-pixels of the second region; the first output voltage is less than the second output voltage. In the invention, the data voltage transmitted by the data line to the sub-pixels of the first area is less than the data voltage transmitted by the data line to the sub-pixels of the second area, so that the voltage of at least one first gate line in the first area can be reduced, and the power consumption of the display panel can be reduced on the basis of not influencing the display effect of the display panel.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (14)
1. The display panel is characterized by comprising a picture to be displayed, wherein the picture to be displayed comprises a first area and a second area;
the display panel comprises a plurality of gate lines extending along a first direction and arranged along a second direction and a plurality of data lines extending along the second direction and arranged along the first direction, the gate lines and the data lines are crossed to define sub-pixels, and the first direction and the second direction are crossed; each sub-pixel comprises a thin film transistor and a pixel electrode, the thin film transistor is provided with a control end, an input end and an output end, the sub-pixel comprises a first sub-pixel positioned in the first area and a second sub-pixel positioned in the second area, the first sub-pixel comprises a first thin film transistor and a first pixel electrode, the second sub-pixel comprises a second thin film transistor and a second pixel electrode, the first thin film transistor and the second thin film transistor are simultaneously in an on state, the brightness of the first area is smaller than that of the second area, or the data voltage input into the sub-pixel in the first area is negative voltage;
the gate lines include a first gate line and a second gate line, the gate lines penetrating the first region are the first gate lines and transmit a first output voltage to at least one of the first gate lines, and the gate lines penetrating the second region are the second gate lines and transmit a second output voltage to the second gate lines;
the data lines transmit data voltages to the sub-pixels of the first region less than the data voltages to the sub-pixels of the second region;
the first output voltage is less than the second output voltage.
2. The display panel according to claim 1,
the control end of the first thin film transistor is electrically connected with the first gate line, the input end of the first thin film transistor is electrically connected with the data line, and the output end of the first thin film transistor is electrically connected with the first pixel electrode;
the control end of the second thin film transistor is electrically connected with the second gate line, the input end of the second thin film transistor is electrically connected with the data line, and the output end of the second thin film transistor is electrically connected with the second pixel electrode;
a gate-source voltage of the first thin film transistor electrically connected to the first gate line transmitting the first output voltage is equal to a gate-source voltage of the second thin film transistor.
3. The display panel according to claim 1, wherein when the luminance of the first region is less than the luminance of the second region, the number of the sub-pixels covered by the first region in the same row of the sub-pixels is at least greater than 2/3 of the total number of the sub-pixels in the same row.
4. The display panel of claim 3, wherein the gray scale of the first region is between 0 and 127.
5. The display panel according to claim 3, wherein the first region and the second region are arranged in the second direction.
6. The display panel according to claim 3, wherein the polarities of the data voltages inputted to the sub-pixels of two adjacent columns are opposite.
7. The display panel according to claim 3, wherein the data voltage inputted by any of the sub-pixels has a polarity opposite to that inputted by the adjacent sub-pixel.
8. The display panel according to claim 1, wherein when the data voltage inputted in the sub-pixel in the first region is a negative voltage, the data voltage inputted in the sub-pixel in the second region is a positive voltage; the first region covers a row of the subpixels.
9. The display panel according to claim 1, wherein when the data voltage inputted in the sub-pixel in the first region is a negative voltage, the data voltage inputted in the sub-pixel in the second region is a positive voltage; the first region covers at least two adjacent rows of the sub-pixels.
10. The display panel according to claim 1, wherein the first regions and the second regions are alternately arranged in the second direction.
11. The display panel of claim 1, wherein the data line transmits at least 40% or less of the data voltage transmitted to the sub-pixels of the first region.
12. The display panel according to claim 1, further comprising a first clock signal line and a second clock signal line arranged in parallel, and a plurality of cascaded shift register units, wherein the shift register units comprise a first driving signal input terminal, a second driving signal input terminal, a driving signal output terminal, a shift signal input terminal, and a shift signal output terminal;
the first driving signal input end is electrically connected with the first clock signal line, the second driving signal input end is electrically connected with the second clock signal, the shifting signal input end is accessed with a shifting signal, and the shifting signal output end is electrically connected with the shifting signal input end of the next cascaded shifting register unit; the driving signal output end is electrically connected with the first gate line or the second gate line.
13. An operating method of a display panel according to any one of claims 1 to 12, the operating method comprising:
determining a first area and a second area, wherein the brightness of the first area is smaller than that of the second area, or the polarity of the sub-pixels in the first area is negative;
transmitting a first output voltage to at least one of the first gate lines and a second output voltage to the second gate line, the first output voltage being less than the second output voltage;
and transmitting data voltages to the sub-pixels through the data lines, wherein the data voltages transmitted to the sub-pixels of the first region are less than the data voltages transmitted to the sub-pixels of the second region through the data lines.
14. A display device comprising the display panel according to any one of claims 1 to 12.
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