KR20110067450A - Liquid crystal display and driving method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display and a driving method thereof are provided to optimize MIP driving by initializing a memory driving circuit with identical polarity voltage and driving the memory driving circuit in MIP driving mode. CONSTITUTION: A liquid crystal cell(CIc) displays data. A storage capacitor(Cst) stores a high potential and low-potential power voltage alternately in a MIP driving mode. A first thin film transistor(T1) supplies a data voltage to the pixel electrode of the liquid crystal cell. A memory driver circuit(MC) reverses the voltage of the N1 node at 1 frame. A first switch circuit(SSW) switches a current path between an inverter(INV) and the N1 node. A second TFT(T2) connects the N1 node to the input node of the inverter. A third TFT(T3) opens the current path between the output node of the N1 node and the inverter. The inverter converts N1 node voltage at 1 frame period unit in an MIP driving mode.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

The present invention relates to a liquid crystal display device capable of driving a memory in pixel (hereinafter referred to as "MIP") and a driving method thereof.

Various flat panel displays (FPDs) that can reduce the weight and volume, which are disadvantages of cathode ray tubes, have been developed. Such flat panel displays include liquid crystal displays (LCDs), plasma display panels, and electroluminescent devices including inorganic electroluminescent devices and organic light emitting diodes (OLEDs). Device, EL), Field Emission Display, Electrophoresis Display, etc., are mostly commercialized, replacing the existing CRT market.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to the cathode ray tube (CRT), and thus replaces the cathode ray tube in most display device fields such as portable information devices, office equipment, computers, and televisions.

When an input image of a moving image or a still image is input, the liquid crystal display displays video data by addressing the data voltage of the input image to each pixel every frame period. Since data is written to each pixel every frame, power consumption of the data driving circuit and the gate driving circuit (or the scan driving circuit) of the liquid crystal display cannot be lowered below a certain level. In order to reduce the power consumption of the liquid crystal display, MIP technology has recently been proposed. MIP technology reduces the power consumption of the data driving circuit by embedding the memory circuit every pixel and rewriting the data with the data voltage embedded in the memory while the data driving circuit is disabled when a still image is input. While the MIP technology is in the spotlight as a low power consumption and eco-friendly technology, it is necessary to optimize the driving method in order to secure the operation reliability.

The present invention provides a liquid crystal display and a driving method thereof for optimizing MIP driving.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes: a liquid crystal display panel including data lines, gate lines crossing the data lines, and pixels in which a memory driving circuit is embedded and a pixel electrode and a common electrode are formed; A data driving circuit configured to float an output channel in a MIP driving mode after supplying one of a white gray voltage and a black gray voltage to the data lines in a pre-MIP driving mode; A gate driving circuit configured to sequentially supply a gate high voltage gate pulse to the gate lines in the pre-MIP driving mode, and then supply a gate low voltage lower than the gate high voltage to the gate lines in the MIP driving mode; A MIP driving circuit configured to supply a high potential power voltage and a low potential power voltage to the data lines in the MIP driving mode; A common voltage controller configured to invert the potential of the common voltage by a predetermined time unit in the MIP driving mode after supplying a common voltage having a predetermined voltage to the common electrode in the pre-MIP driving mode; And a controller controlling the data driving circuit, the gate driving circuit, the MIP driving circuit, and the common voltage controller.

In the driving method of the liquid crystal display device, one of the white gray voltage and the black gray voltage is supplied to the data lines through the output channels of the data driving circuit in the pre-MIP driving mode, and then, Plotting an output channel; Sequentially supplying a gate high voltage gate pulse to the gate lines in the pre-MIP driving mode, and then supplying a gate low voltage lower than the gate high voltage to the gate lines in the MIP driving mode; Supplying a high potential power voltage and a low potential power voltage to the data lines using a MIP driving circuit connected to the data lines in the MIP driving mode; And inverting the potential of the common voltage by a predetermined time unit in the MIP driving mode after supplying a common voltage having a constant voltage to the common electrode in the pre-MIP driving mode.

The present invention can optimize the MIP driving by initializing the memory driving circuit in pixels with voltages of the same polarity in the pre-MIP driving mode and then driving the memory driving circuit in the MIP driving mode.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Component names used in the following description are selected in consideration of ease of specification, and may be different from actual product part names.

The liquid crystal display of the present invention is driven in a normal mode and a MIP mode. The normal mode can be subdivided into normal drive mode and stand-by mode.

In the normal driving mode, data of the input image is written to each of the pixels of the liquid crystal display panel every frame to display the data on the liquid crystal display panel. In the normal driving mode, the output of the data driving circuit outputs a positive / negative analog data voltage corresponding to the data gray level of the input image, and the gate driving circuit sequentially outputs a gate pulse (or scan pulse) every frame. The standby mode does not display data of the input image because power is supplied to the liquid crystal display, but does not drive the liquid crystal display panel. In the standby mode, the output of the data driving circuit outputs only the high potential power supply voltage VDD or the low potential power supply voltage VSS, and the gate driving circuit outputs the gate low voltage VGL. Switching from the normal driving mode to the standby mode or from the standby mode to the normal driving mode is switched through the power off / power on sequence mode as shown in FIG. 1. The liquid crystal display discharges the driving voltages of the liquid crystal display device to the base voltage according to a preset power off sequence in the power off sequence mode. Occurs.

The MIP mode is divided into a pre-MIP drive mode and a MIP drive mode. As shown in FIG. 2, the liquid crystal display operates in the pre-MIP driving mode before switching from the normal driving mode to the MIP driving mode. The pre-MIP driving mode initializes the state of each pixel of the liquid crystal display panel to a state suitable for MIP driving in order to stabilize the MIP driving. In this pre-MIP driving mode, each pixel of the liquid crystal display panel is supplied with digital data including the highest gray level voltage or the lowest gray level voltage, and the data lines of the liquid crystal display panel are supplied with power for driving the MIP circuit embedded in each pixel. Is applied. In the MIP driving mode, a data voltage is applied to a pixel electrode by using a MIP circuit embedded in each pixel. In the MIP driving mode, the output of the data driving circuit is inactive and the gate driving circuit outputs the gate low voltage VGL. When switching from the MIP driving mode to the normal driving mode, the liquid crystal display is directly switched from the MIP driving mode to the normal driving mode without going through the pre-MIP driving mode as shown in FIG. 2.

3 and 4 illustrate a liquid crystal display according to an exemplary embodiment of the present invention.

3 and 4, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a system board 104, a mode controller 110, and a data driving circuit 102. ), A gate driving circuit 103, a MIP driving circuit 105, a power integrated circuit (hereinafter referred to as a power IC) 106, and a common voltage controller 107.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes pixels arranged in a matrix by a cross structure of the data lines D1 to Dm and the gate lines G1 to Gn. Each pixel includes a liquid crystal cell Clc, a TFT T, a memory driving circuit MC, and the like, as shown in FIGS. 4 to 6.

The lower substrate of the liquid crystal display panel 100 includes data lines D1 to Dm, gate lines G1 to Gn, first TFTs T1, pixel electrodes of the liquid crystal cell Clc, a common electrode, and a storage capacitor. A pixel array including a storage capacitor Cst, a memory driving circuit MC, and the like is formed. A pixel array including a black matrix, a color filter, and the like is formed on the upper substrate of the liquid crystal display panel 100. A column spacer may be formed between the lower substrate and the upper substrate to maintain a cell gap of the liquid crystal cell Clc.

A polarizing plate is attached to each of the upper substrate and the lower substrate of the liquid crystal display panel 100 to form an alignment layer for setting a pre-tilt angle of the liquid crystal.

The liquid crystal display panel 100 may be implemented in any liquid crystal mode, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, or fringe field switching (FFS) mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 receives digital video data RGB from the system board 104 through an interface receiving circuit such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling (TMDS) interface.

The timing controller 101 transmits the digital video data RGB input from the system board 104 to the data driving circuit 102 as a full bit in the normal driving mode. The timing controller 101 may switch the operation mode according to the mode signal MODE signal input from the mode controller 110 or the system board 104.

The timing controller 101 transmits the digital data consisting of only the most significant bit (MSB) of the digital video data RGB input from the system board 104 to the data driving circuit 102 in the pre-MIP driving mode. . For example, in the pre-MIP driving mode, if the 8-bit data of the input image is "1 ××××××× _2, ” the timing controller 101 converts the input data into “11111111” and the data driving circuit 102. To be sent). Pre-8 Bit data of the input image from MIP drive mode is "0 ××××××× _2" is a timing roller cone 101 is transmitted to the input data is converted into "00000000" to the data driving circuit 102 do. Here, '×' is a bit of '1' or '0'. The timing controller 101 does not transmit the digital video data RGB in the MIP driving mode.

The timing controller 101 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the dot clock CLK from the system board 104 through the LVDS or TMDS interface receiving circuit. An external timing signal such as The timing controller 101 generates control signals for controlling the operation timing of the data driving circuit 102 and the gate driving circuit 103 using an external timing signal. The control signals include a gate timing control signal for controlling the operation time of the gate driving circuit 103, and a data timing control signal for controlling the operation timing of the data driving circuit 102 and the polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse (GSP) is applied to a gate drive integrated circuit (IC) that generates the first gate pulse to control the gate drive IC to generate the first gate pulse. The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE). It includes. The source start pulse SSP controls the data sampling start timing of the data driving circuit. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the data driving circuit 102 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the data driving circuit 102. The source output enable signal SOE controls the output timing of the data driver circuit 102. If the digital video data to be input to the data driving circuit 102 is transmitted in mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

The system board 104 or the timing controller 101 may multiply the frame frequency by 60 × i (i is an integer of 2 or more) Hz to drive the liquid crystal display panel 100 at a frame frequency of 60 × iHz.

The timing controller 101 converts the data timing control signal and the gate timing control signal into a control signal format suitable for each mode in response to the mode signal MODE to operate the data driving circuit 102 and the gate driving circuit 103. Switch. The timing controller 101 controls the data driving circuit 102 and the gate driving circuit 103 in the pre-MIP driving mode for a predetermined time in the MIP mode, and then drives the driving circuits 102 and 103 in the MIP driving mode. To control.

The system board 104 transmits the digital video data RGB and the timing signals Vsync, Hsync, DE, and CLK to the timing controller 101 through an interface such as an LVDS interface and a TMDS interface. The system board 104 may generate a mode signal MODE according to user input data input through the user input device 109. The user input device 109 may include a touch screen, a touch pad, an on screen display (OSD), a keyboard, a keypad, a mouse, a remote controller, or the like attached or embedded on the liquid crystal display panel 100. Include. Accordingly, the user may control the liquid crystal display in the normal mode and the MIP mode through the user input device 109.

The mode controller 110 receives digital video data RGB and an external timing signal from the system board 104 and analyzes the input image data. The mode controller 110 outputs the mode signal MODE as the first logic value when the input image is a moving image, and outputs the mode signal MODE as the second logic value when the input image is a still image. In addition, the mode controller 110 outputs the mode signal MODE as the first logic value in the normal driving mode and the pre-MIP driving mode, and outputs the mode signal MODE as the second logic value in the MIP driving mode. Hereinafter, the first logic value of the memory control signal Cmem is assumed to be a low potential voltage value, and the second logic value of the memory control signal Cmem is assumed to be a high potential voltage value, respectively.

The mode controller 110 outputs the memory control signal Cmem as a first logic value to deactivate the memory driving circuit MC in the normal driving mode and the pre-MIP driving mode. The mode controller 110 swings the memory control signal Cmem between the first logic value and the second logic value in the MIP driving mode. The memory control signal Cmem is swinged in one frame period. Hereinafter, the first logic value of the memory control signal Cmem is assumed to be a high potential voltage value, and the second logic value of the memory control signal Cmem is assumed to be a low potential voltage value, respectively.

In another embodiment, when the mode controller 110 receives the mode signal MODE from the system board 104, the mode controller 110 receives the mode signal MODE received from the system board 104. 105, and transmitted to the common voltage controller 107, and outputs a memory control signal Cmem suitable for the mode indicated by the mode signal MODE. The mode controller 110 and the timing controller 101 may be integrated into a one chip controller.

The mode controller 110 swings the voltage of the memory control signal Cmem between "Vdh + α" and "Vdl- (Vch-Vcl)" in the MIP driving mode. Here, "Vdh" is a high potential power supply voltage supplied to the data lines D1 to Dm in the MIP driving mode, and "Vdh + α" is a voltage higher by α than the high potential supply voltage. "Vdl" is a low potential power supply voltage supplied to the data lines D1 to Dm in the MIP driving mode, and "Vch" and "Vcl" are high voltages of the common voltage Vcom supplied to the common electrode in the MIP driving mode, respectively. Above voltage and low potential voltage.

The data driver circuit 102 includes one or more source drive ICs. Each of the source drive ICs includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The data driving circuit 102 samples and latches the digital video data RGB under the control of the timing controller 101. The data driving circuit 102 converts the digital video data RGB into the positive / negative gamma compensation voltages VGMA1 to VGMAi to invert the polarity of the data voltage. The data driving circuit 102 inverts the polarities of the data voltages output to the data lines D1 to Dm in response to the second polarity control signal POL2. Each of the source drive ICs may be connected to the data lines D1 to Dm of the liquid crystal display panel 100 by a chip on glass (COG) process or a tape automated bonding (TAB) process. The source drive IC may be integrated in the timing controller 101 and implemented as a one-chip IC together with the timing controller 101.

The data driving circuit 102 converts digital data inputted from the timing controller 101, that is, "11111111" or "00000000" into white gray voltage or black gray voltage under the control of the timing controller 101 in the pre-MIP driving mode. Output to the data lines D1 to Dm. The data driving circuit 102 outputs the white gray voltage or the black gray voltage output in the pre-MIP driving mode as a voltage having the same polarity.

The data driving circuit 102 blocks the current path between the output channels and the data lines under the control of the timing controller 101 in the MIP driving mode, that is, floats all of the output channels. Therefore, in the MIP driving mode, the data driving circuit 102 does not generate an output, so there is no current consumption, so the current consumption is minimized.

The gate driving circuit 103 generates a gate pulse with a gate high voltage VGH under the control of the timing controller 101 in the normal driving mode and the pre-MIP driving mode, and sequentially sequates the gate pulse to the gate lines G1 to Gn. To supply. The gate driving circuit 103 supplies only the gate low voltage VGL to the gate lines G1 to Gn in the MIP driving mode. The gate high voltage VGH is a voltage higher than or equal to the threshold voltage of the first TFT T1 formed in the pixel array, and the gate low voltage VGL is lower than the threshold voltage of the first TFT T1. Accordingly, the first TFTs T1 formed in the pixel array are turned on in accordance with the gate pulse in the normal driving mode and the pre-MIP driving mode, so that the data voltages from the data lines D1 to Dm are applied to the liquid crystal cell Clc. While being supplied to the pixel electrode, it is kept off in the MIP driving mode. The gate drive ICs of the gate driving circuit 103 are connected to the gate lines G1 to Gn of the lower substrate of the liquid crystal display panel 100 through the TAP process or the liquid crystal display together with the pixel array in the GIP process. It may be formed directly on the lower substrate of the panel 100.

The MIP driving circuit 105 plots its output channels in the normal driving mode and the pre-MIP driving mode in response to the first logic value of the mode signal MODE to between the output channels and the data lines D1 to Dm. Shut off the current path. On the other hand, the MIP driving circuit 105 plots its output channels in the normal driving mode and the pre-MIP driving mode in response to the signal of the mode signal MODE to between the output channels and the data lines D1 to Dm. Shut off the current path. On the other hand, the MIP driving circuit 105 sets the low potential power supply voltage Vdl in the MIP driving mode in response to the second logic value of the mode signal MODE to the odd data lines D1, D3 ... Dm-1. The low potential supply voltage (Vdl) or the high potential supply voltage (Vdh) is supplied to the even data lines (D2, D4 ... Dm).

The MIP driving circuit 105 supplies the high potential power voltage Vdh to the odd data lines D1, D3, ... Dm-1 in response to the high potential voltage of the mode signal MODE as shown in FIG. Odd TFT groups for supplying the low potential power supply voltage Vdl to the even data lines D1, D3, ... Dm-1 in response to the high potential voltage of the mode signal MODE. Include them. The mode signal MODE is supplied to the gate electrode of each of the TFTs in the odd TFT group, and the high potential power voltage Vdh is supplied to the drain electrode thereof. The source electrodes of each of the TFTs of the odd TFT group are connected to odd data lines D1, D3, ... Dm-1. The mode signal MODE is supplied to the gate electrode of each of the TFTs of the even TFT group, and the low potential power supply voltage Vdl is supplied to the source electrode thereof. The drain electrodes of each of the TFTs of the even TFT group are connected to the even data lines D2, D4, ... Dm.

In Fig. 4, "CPL" is a mode signal supply line formed under the pixel array to supply the mode signal MODE to the gate voltage of the TFTs. &Quot; PL1 " is a first power line formed under the pixel array to supply high potential power voltage Vdh to the odd TFTs. &Quot; PL2 " is a second power supply line formed in the pixel array for supplying the low potential power supply voltage Vdh to the even TFTs. '41' is a memory control signal supply line which is formed in the pixel array and supplies a memory control signal Cmem to each of the pixels. '42' is a common voltage supply line formed in the pixel array to supply the common voltage Vcom to the common electrodes of each pixel.

The power IC 106 includes a DC-DC including a pulse width modulation (PWM) modulation circuit, a boost converter, a regulator, a charge pump, a voltage divider circuit, an operation amplifier, and the like. Built-in converter The power IC 106 adjusts an input voltage Vin input from the system board 104 to generate driving voltages of the liquid crystal display panel 100. The driving voltage of the liquid crystal display panel 100 includes a logic power supply voltage Vcc, a high potential power supply voltage VDD, a gate high voltage VGH, a gate low voltage VGL, a common voltage Vcom, and a positive / negative polarity. Gamma reference voltages VGMA1 to VGMAi and driving voltages Vdh, Vdl, Vch, Vcl, Vdh + α, and Vdl− (Vch−Vcl)} of the MIP driving mode. The Vdh voltage is a white gray voltage charged in the pixel in the MIP driving mode and may be a high potential power voltage VDD and an equipotential voltage. Vdl is a white gray voltage charged in the pixel in the MIP driving mode and may be a 1/2 VDD voltage and an equipotential voltage. The positive / negative gamma reference voltages VGMA1 to VGMAi are voltages divided between the high potential power voltage Vdd and the low potential power voltage VSS by the voltage dividing circuit. The logic power supply voltage Vcc is a driving power supply of the timing controller 101, the mode controller 110, the data driving circuit 102, the gate driving circuit 103, the MIP driving circuit 105, and the common voltage controller 107. .

The common voltage controller 107 receives the common voltage Vcom from the power IC 106 and adjusts the common voltage Vcom according to the mode signal MODE. The common voltage controller 107 outputs the common voltage Vcom at a constant DC voltage in the normal driving mode and the pre-MIP driving mode in response to the first logic value of the mode signal MODE, or the liquid crystal display panel 100 is connected to the line. When driven by Line inversion, it outputs with AC common voltage which inverts by one horizontal period. The common voltage controller 107 outputs a common voltage Vcom swinging between the high potential voltage Vch and the low potential voltage Vch in the MIP driving mode in response to the second logic value of the mode signal MODE. . The common voltage Vcom is swinged every two frame periods in the MIP driving mode.

4 and 5 are circuit diagrams showing pixels of the liquid crystal display panel 100 in detail.

4 and 5, each pixel includes a liquid crystal cell Clc, a storage capacitor Cst, a first TFT T1, and a memory driving circuit MC. 5, "Col1" and "Col2" are neighboring data lines. For example, Col1 may be an odd data line D1, D3, ... Dm-1, and Col2 may be an even data line D2, D4, ... Dm. Hereinafter, "Col1" will be referred to as a first data line, and Col2 will be referred to as a second data line.

The liquid crystal cell Clc displays data by adjusting light transmittance according to an electric field between a data voltage applied to the pixel electrode and a common voltage Vcom supplied to the common electrode. One electrode of the storage capacitor Cst is connected to the pixel electrode of the liquid crystal cell Clc through the N1 node, and the other electrode is connected to the common electrode supplied with the common voltage Vcom to maintain a constant voltage of the liquid crystal cell Clc. Keep it. The storage capacitor Cst serves as a memory that alternately stores the high potential power voltage Vdh and the low potential power voltage Vdl in units of one frame period in the MIP driving mode. The first TFT T1 is turned on according to the gate high voltage VGH of the gate pulse SCAN to supply the data voltage from the first data line Col1 to the pixel electrode of the liquid crystal cell Clc. The first TFT T1 may be implemented with an n-type MOSFET (metal-oxide semiconductor field-effect transistor). The gate electrode of the first TFT T1 is connected to the gate line. The drain electrode of the first TFT T1 is connected to the first data line Col1, and the source electrode thereof is connected to the pixel electrode of the liquid crystal cell Clc and one electrode of the storage capacitor Cst via the N1 node. .

The memory driving circuit MC is connected to the first data line Col1, the second data line, and the N1 node. The memory driving circuit MC is inactivated in the normal driving mode and the pre-MIP driving mode in response to the first logic value of the memory control signal Cmem, thereby not affecting the liquid crystal cell Clc and the storage capacitor Cst. The memory driving circuit MC inverts the voltage of the N1 node every one frame period in response to the memory control signal Cmem which is inverted in one frame period period in the MIP driving mode.

The memory driving circuit MC includes a first switch circuit SSW, an inverter INV, and a second switch circuit SW.

The first switch circuit SSW switches the current path between the N1 node and the inverter INV in response to the memory control signal Cmem. As shown in FIG. 5, the first switch circuit SSW may include second and third TFTs T2 and T3. The second TFT T2 may be implemented with an n-type MOSFET. The third TFT T3 may be implemented with a p-type MOSFET.

The second TFT T2 is turned on according to the high potential voltage of the memory control signal Cmem to connect the N1 node to the input node of the inverter INV, while the second TFT T2 is turned on according to the low potential voltage of the memory control signal Cmem. It is turned off to open the current path between the N1 node and the input node of the inverter INV. The memory control signal Cmem is supplied to the gate electrode of the second TFT T2. The drain electrode of the second TFT T2 is connected to the N1 node, and the source electrode thereof is connected to the input node of the inverter INV.

The third TFT T3 is turned on according to the low potential voltage of the memory control signal Cmem to connect the N1 node to the output node of the inverter INV, while the third TFT T3 is turned on according to the high potential voltage of the memory control signal Cmem. It is turned off to open the current path between the N1 node and the output node of the inverter INV. The memory control signal Cmem is supplied to the gate electrode of the third TFT T3. The drain electrode of the third TFT T3 is connected to the output node of the inverter INV, and its source electrode is connected to the N1 node.

As a second embodiment, the first switch circuit SSW may include a second TFT (T2), a 3-1 TFT (T31), and a 3-2 TFT (T32) as shown in FIG. Each of the 3-1 and 3-2 TFTs T31 and T32 may be implemented with a p-type MOSFET. The 3-1 and 3-2 TFTs T31 and T32 function substantially the same as the third TFT T3 shown in FIG. The third-1 and third-2 TFTs T31 and T32 have a greater leakage current blocking effect flowing in the off state than the third TFT T3. The memory control signal Cmem is supplied to each of the gate electrodes of the 3-1 and 3-2 TFTs T31 and T32. The drain electrode of the 3-1 TFT (T31) is connected to the output node of the inverter INV, and the source electrode thereof is connected to the drain electrode of the 3-2 TFT (T32). The source electrode of the third-2 TFT (T32) is connected to the N1 node.

The inverter INV inverts the N1 node voltage by one frame period in the MIP driving mode. The inverter INV may include fourth and fifth TFTs T4 and T5. The fourth TFT T4 may be implemented with an n-type MOSFET. The fifth TFT T5 may be implemented with a p-type MOSFET.

The fourth TFT T4 is turned on when the input node voltage of the inverter INV is a high potential voltage to supply the voltage of the second data line Col2 to the output node of the inverter INV, while the inverter INV is turned on. Is turned off when the input node voltage of the circuit is a high potential voltage to open a current path between the second data line Col2 and the output node of the inverter INV. The gate electrode of the fourth TFT T4 is connected to the input node of the inverter INV. The drain electrode of the fourth TFT T4 is connected to the second data line Col2, and the source electrode thereof is connected to the output node of the inverter INV.

The fifth TFT T5 is turned on when the input node voltage of the inverter INV is a low potential voltage to convert the power supply voltage from the first data line Col1 input via the second switch circuit SW. While supplying to the output node of INV, it is turned off when the input node voltage of the inverter INV is high potential voltage to open the current path between the second switch circuit SW and the output node of the inverter INV. Let's do it. The gate electrode of the fifth TFT T5 is connected to the input node of the inverter INV. The drain electrode of the fifth TFT T5 is connected to the second switch circuit SW, and the source electrode thereof is connected to the output node of the inverter INV.

The second switch circuit SW is between the first data line Col1 and the fifth TFT T5 of the inverter INV in the normal driving mode and the pre-MIP driving mode in response to the high potential voltage of the memory control signal Cmem. Shut off the current path. The second switch circuit SW applies the first data line Col1 to the current between the fifth TFT T5 of the inverter INV in response to the memory control signal Cmem inverted in one frame period in the MIP driving mode. Turn the path on and off. The second switch circuit SW may include a sixth TFT T6. The sixth TFT T6 may be implemented with a p-type MOSFET.

The sixth TFT T6 is turned on when the memory control signal Cmem is at a low potential voltage to connect the first data line Col1 to the drain electrode of the fifth TFT T5, while the memory control signal Cmem is turned on. Is turned off when the high potential voltage is opened to open the current path between the first data line Col1 and the drain electrode of the fifth TFT T5. The memory control signal Cmem is supplied to the gate electrode of the sixth TFT T6. The drain electrode of the sixth TFT T6 is connected to the first data line Col1, and the source electrode thereof is connected to the drain electrode of the fifth TFT T5.

The liquid crystal display of the present invention can be driven in frame inversion as the first embodiment of the MIP mode and in line inversion as the second embodiment of the MIP mode.

In order to drive the liquid crystal display in frame inversion in the MIP mode, the memory control signal supply line includes odd lines (LINE # 1, LINE # 3) and even lines (LINE # 1) of the liquid crystal display panel 100 as shown in FIG. Commonly connected to # 2 and LINE # 4, the same memory control signal Cmem is supplied to the odd lines LINE # 1 and LINE # 3 and the even lines LINE # 2 and LINE # 4. In the liquid crystal display driven by frame inversion, all of the pixels charge the voltage of the first polarity during the odd frame period and the electrode polarity is inverted by the inverter INV during the even frame period to charge the voltage of the second polarity. .

In order to drive the liquid crystal display in line inversion in the MIP mode, the memory control signal supply line may include a first memory control signal on the odd lines LINE # 1 and LINE # 3 of the liquid crystal display panel 100 as shown in FIG. 8. First memory control signal supply line 411 for supplying Cmem + and second memory control signal for supplying second memory control signal Cmem- to even lines LINE # 2 and LINE # 4. It is divided into supply line 412. In a liquid crystal display driven by line inversion, pixels of odd lines charge voltages of a first polarity during odd frame periods, while pixels of even lines charge voltages of a second polarity. In a liquid crystal display driven by line inversion, pixels of odd lines charge voltages of the second polarity while pixels of even lines charge voltages of the first polarity during the even frame period.

9 is a waveform diagram illustrating driving signals for driving a liquid crystal display in frame inversion in a MIP mode.

Referring to FIG. 9, the liquid crystal display of the present invention is driven in the pre-MIP driving mode for one frame period, and then in the MIP driving mode.

When driving the liquid crystal display in frame inversion in the pre-MIP driving mode, the common voltage Vcom is generated as a direct current voltage during the pre-MIP driving mode.

In the pre-MIP driving mode, the mode control signal MODE is generated with a low potential voltage and the memory control signal Cmem is generated with a high potential voltage. Therefore, the current path between the output channels of the MIP driving circuit 105 and the data lines D1 to Dm is opened. The memory driving circuit MC is disabled in the pre-MIP driving mode by the memory control signal Cmem having a high potential voltage.

The data driving circuit 102 supplies only the white gray voltage or the black gray data voltage having the same polarity to the first and second data lines Col1 and Col2 every horizontal period in the pre-MIP driving mode. In this case, data voltages of the same polarity are written in the pixels of all the lines as shown in FIG.

As another embodiment of the pre-MIP driving mode, the data driving circuit 102 supplies only the white gray voltage or the black gray data voltage having the first polarity to the first and second data lines Col1 and Col2 every odd period. Only the white gray voltage or the black gray data voltage having the second polarity may be supplied to the first and second data lines Col1 and Col2 during the even horizontal period. In this case, data voltages of a first polarity (positive or negative polarity) are written in pixels of odd lines, and data voltages of second polarity (negative or positive polarity) are written in pixels of even lines. Is written.

The polarity of the data voltage is positive when the data voltage is higher than the common voltage Vcom and negative when the data voltage is lower than the common voltage Vcom as shown in FIG. 13.

The reason why the white gray voltage or the black gray voltage is written to all the pixels in the pre-MIP driving mode is to prevent malfunction and increase in power consumption of the memory driving circuit MC driving digitally in the MIP driving mode. For example, when the gray scale voltage is written to the pixel in the pre-MIP driving mode, the gray scale voltage is applied to the input node of the inverter INV in the MIP driving mode, and in this case, the fifth and sixth TFTs T5 and T6 At the same time, it is turned on (or turned off) to malfunction and the leakage current is increased in the fifth and sixth TFTs T5 and T6.

In FIG. 9, 'Vck' is a voltage waveform of the gate shift clock GSC and 'Vst' is a voltage waveform of the gate start pulse GSP. The gate driving circuit 103 sequentially supplies gate pulses to the gate lines G1 to Gn in response to the gate timing control signal in the normal driving mode and the pre-MIP driving mode.

Meanwhile, the first and second data lines Col1 and Col2 serve as video data lines to which data voltages are input from the data driving circuit 102 in the normal driving mode and the pre-MIP driving mode. This serves as a power line to be input.

An operation description for driving the liquid crystal display with frame inversion in the MIP driving mode will be described in detail with reference to FIG. 14.

FIG. 10 is a waveform diagram illustrating driving signals for driving a liquid crystal display in line inversion in a MIP mode.

Referring to FIG. 10, the liquid crystal display of the present invention is driven in the pre-MIP driving mode for one frame period, and then in the MIP driving mode.

When driving the liquid crystal display in line inversion in the pre-MIP driving mode, the common voltage Vcom is generated as an AC voltage whose potential is reversed every one horizontal period during the pre-MIP driving mode.

In the pre-MIP driving mode, the mode control signal MODE is generated at a low potential voltage, and the first and second memory control signals Cmem + and Cmem− are generated at a high potential voltage. Therefore, the current path between the output channels of the MIP driving circuit 105 and the data lines D1 to Dm is opened. The memory driving circuit MC is inactivated in the pre-MIP driving mode by the first and second memory control signals Cmem + and Cmem− of the high potential voltage.

The data driving circuit 102 supplies only the white gray voltage or the black gray data voltage having the same polarity to the first and second data lines Col1 and Col2 every horizontal period in the pre-MIP driving mode. In this case, data voltages of the same polarity are written in the pixels of all the lines as shown in FIG.

As another embodiment of the pre-MIP driving mode, the data driving circuit 102 supplies only the white gray voltage or the black gray data voltage having the first polarity to the first and second data lines Col1 and Col2 every odd period. Only the white gray voltage or the black gray data voltage having the second polarity may be supplied to the first and second data lines Col1 and Col2 during the even horizontal period. In this case, data voltages of a first polarity (positive or negative polarity) are written in pixels of odd lines, and data voltages of second polarity (negative or positive polarity) are written in pixels of even lines. Is written.

An operation description for driving the liquid crystal display with the line inversion in the MIP driving mode will be described in detail with reference to FIG. 15.

14 is a waveform diagram illustrating driving signals for driving a liquid crystal display in frame inversion in a MIP driving mode.

Referring to FIG. 14, the common voltage Vcom is swinged every two frame periods in the MIP driving mode. In the MIP driving mode, the memory control signal Cmem is swinged in one frame period period, and the mode signal MODE is generated at a high potential voltage. Therefore, the MIP driving circuit 105 supplies the power voltages Vdh and Vdl to the first and second data lines Col1 and Col2 in response to the mode signal MODE of the high potential voltage.

The memory driving circuit MC writes a white gray voltage or a black gray voltage at the node N1 in response to the memory control signal Cmem of the low potential voltage (Writing operation) and in response to the memory control signal Cmem of the high potential voltage. The voltage of the N1 node is supplied to the input node of the inverter INV (reading operation).

The data driving circuit 102 floats all of the output channels under the control of the timing controller 101 to block the current path between the output channels and the data lines Col1 and Col2. The gate driving circuit 103 supplies only the gate low voltage VGL to the gate lines under the control of the timing controller 101. Therefore, the first TFTs T1 of the pixel array remain in the off state in the MIP driving mode.

At the beginning of time t11, the memory control signal Cmem is inverted to the low potential voltage Vdl- (Vch-Vcl), and the pixel voltage Vpxl is connected to the first and second data lines Col1 and Col2. The voltage is inverted to the low potential power supply voltage Vdl or the high potential power supply voltage Vdh. The common voltage Vcom changes from the low potential voltage Vcl to the high potential voltage Vch within the t11 and t12 times. During t11 and t12 hours, the memory driving circuit MC turns on the third and sixth TFTs T3 and T6 in response to the memory control signal Cmem of the low potential voltage Vdl- (Vch-Vcl). The pixel voltage Vpxl output from the inverter INV is written to the node N1.

The gray level of the pixel voltage Vpxl is determined according to the power supply voltages Vdh and Vdl supplied from the first and second data lines Col1 and Col2. When the common voltage Vcom is the high potential voltage Vch and the output voltage of the inverter INV is the low potential voltage Vdl, the pixel voltage Vpxl charged to the N1 node is a white gray voltage. When the common voltage Vcom is the low potential voltage Vch and the output voltage of the inverter INV is the high potential voltage Vdh, the pixel voltage Vpxl charged to the N1 node is a white gray voltage. When the common voltage Vcom is the high potential voltage Vch and the output voltage of the inverter INV is the high potential voltage Vdh, the pixel voltage Vpxl charged to the N1 node is the black gray voltage. When the common voltage Vcom is the low potential voltage Vch and the output voltage of the inverter INV is the low potential voltage Vdl, the pixel voltage Vpxl charged to the N1 node is a black gray voltage.

The transition point of the common voltage Vcom should exist within a data writing section in which the memory control signal Cmem maintains the low potential voltage Vdl- (Vch-Vcl). When the memory control signal Cmem is the high potential voltage Vdh + α, the second TFT T2 is turned on, so the input node voltage of the inverter INV is changed due to the coupling effect with the common voltage Vcom. This is because the inverter INV may malfunction.

The times t11 and t12 during which the memory control signal Cmem maintains the low potential voltage Vdl- (Vch-Vcl) should be minimized. This is because when the t11 and t12 times are long, the input node voltage of the inverter INV is changed by the off current, that is, the leakage current of the second TFT T2, and the inverter INV may malfunction. Of memory control signal (Cmem)

During the t13 time, the memory control signal Cmem maintains the high potential voltage Vdh + α, and the common voltage Vcom maintains the high potential voltage Vch. During the t13 time, the memory driving circuit MC turns on the second TFT T2 in response to the memory control signal Cmem of the high potential voltage Vch to convert the pixel voltage Vpxl of the N1 node into the inverter INV. To the input node.

At the beginning of time t14, the memory control signal Cmem is inverted to the low potential voltage Vdl- (Vch-Vcl), and the pixel voltage Vpxl is inverted to the output voltage of the inverter INV. The common voltage Vcom is inverted to the low potential voltage Vcl within the times t14 and t15. During t14 and t15 hours, the memory driving circuit MC turns on the third and sixth TFTs T2 and T6 in response to the memory control signal Cmem of the low potential voltage Vdl- (Vch-Vcl). The pixel voltage Vpxl inverted by the inverter INV is written to the node N1.

The low potential voltage of the memory control signal Cmem is set at the level of Vdl- (Vch-Vcl). This is because when the common voltage Vcom is lowered to the low potential voltage Vcl, the pixel voltage Vpxl of the N1 node is lowered due to the coupling with the common voltage Vcom, thereby turning on the second TFT T2. This is to prevent.

FIG. 15 is a waveform diagram illustrating driving signals for driving a liquid crystal display in line inversion in a MIP driving mode.

Referring to FIG. 15, in the MIP driving mode, the common voltage Vcom is swinged every two frame periods. In the MIP driving mode, the first and second memory control signals Cmem + and Cmem− are swinged in one frame period, and the mode signal MODE is generated at a high potential voltage. Therefore, the MIP driving circuit 105 supplies the power voltages Vdh and Vdl to the first and second data lines Col1 and Col2 in response to the mode signal MODE of the high potential voltage.

The memory driving circuit MC writes a white gray voltage or a black gray voltage to the node N1 in response to the first and second memory control signals Cmem + and Cmem− having a low potential voltage (Writing operation), and In response to the first and second memory control signals Cmem + and Cmem−, the voltage of the N1 node is supplied to an input node of the inverter INV (reading operation).

The data driving circuit 102 floats all of the output channels under the control of the timing controller 101 to block the current path between the output channels and the data lines Col1 and Col2. The gate driving circuit 103 supplies only the gate low voltage VGL to the gate lines under the control of the timing controller 101. Therefore, the first TFTs T1 of the pixel array remain in the off state in the MIP driving mode.

During the initial periods t21 to t25 of the MIP driving mode, the common voltage Vcom is generated as a high potential voltage for a predetermined time t21 to t23, and then inverted to a low potential voltage for a predetermined time t24 to t25. The second memory control signal Cmem− changes from a high potential voltage to a low potential voltage within the times t21 to t23 when the common voltage Vcom maintains the high level voltage. The memory driving circuit MC of the odd-numbered line (or even-numbered line) that charges the negative data has the third and sixth TFTs T3 and T6 at the beginning of t23 time in response to the memory control signal Cmem of low potential voltage. ) Is turned on to write the negative pixel voltage Vpxl- output from the inverter INV to the N1 node. The first memory control signal Cmem + changes from the high level voltage to the low level voltage within the times t24 to t25 when the common voltage Vcom maintains the low level voltage. The memory driving circuit MC of the even line (or odd line) that charges the positive data has the third and sixth TFTs T3 and T6 at the beginning of time t25 in response to the memory control signal Cmem of low potential voltage. ) Is turned on to write the positive pixel voltage Vpxl + output from the inverter INV to the N1 node.

The positive pixel voltage Vpxl + should be written to node N1 when the common voltage Vcom is a low potential voltage, and the negative pixel voltage Vpxl- should be written to node N1 when the common voltage Vcom is a high potential voltage. Should be. If the negative pixel voltage Vpxl- is written to the N1 node when the common voltage Vcom is low potential, or the positive pixel voltage Vpxl + is written to the N1 node when the common voltage Vcom is high potential voltage. Upon writing, the initial data written to the pixels of the odd and even lines becomes the same.

During the t26 to t32 time periods, the voltages of the first and second memory control signals Cmem + and Cmem− are inverted, and the memory driving circuit MC inverts the polarity of the initially written pixel data voltage in units of one frame period. Repeat this.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

1 illustrates a normal mode operation of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a view illustrating a mode switching operation between a normal mode and a MIP mode in a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating an image display device according to an exemplary embodiment of the present invention.

4 is a circuit diagram illustrating in detail a pixel of the liquid crystal display panel illustrated in FIG. 3.

FIG. 5 is a circuit diagram showing a first embodiment of the memory circuit shown in FIG.

FIG. 6 is a circuit diagram illustrating a second embodiment of the memory circuit shown in FIG. 3.

7 is a view showing a first embodiment of a mode control signal supply line.

8 is a view showing a second embodiment of a mode control signal supply line.

9 is a waveform diagram illustrating driving signals for driving a liquid crystal display in frame inversion in a MIP mode.

FIG. 10 is a waveform diagram illustrating driving signals for driving a liquid crystal display in line inversion in a MIP mode.

FIG. 11 is a diagram illustrating an example in which data voltages of the same polarity are applied to pixels of all lines in the pre-MIP driving mode.

FIG. 12 is a diagram illustrating an example in which a data voltage of a first polarity is applied to pixels of odd lines and a data voltage of a second polarity is applied to pixels of even lines in a pre-MIP driving mode.

13 is a diagram illustrating polarity division of data voltages.

14 is a waveform diagram illustrating driving signals for driving a liquid crystal display in frame inversion in a MIP driving mode.

FIG. 15 is a waveform diagram illustrating driving signals for driving a liquid crystal display in line inversion in a MIP driving mode.

<Description of Symbols for Main Parts of Drawings>

100: liquid crystal display panel 101: timing controller

102: data driving circuit 103: gate driving circuit

104: system board 105: MIP drive circuit

106: power IC 107: common voltage controller

Claims (18)

A liquid crystal display panel including data lines, gate lines intersecting the data lines, and pixels in which a memory driving circuit is embedded and a pixel electrode and a common electrode are formed; A data driving circuit configured to float an output channel in a MIP driving mode after supplying one of a white gray voltage and a black gray voltage to the data lines in a pre-MIP driving mode; A gate driving circuit configured to sequentially supply a gate high voltage gate pulse to the gate lines in the pre-MIP driving mode, and then supply a gate low voltage lower than the gate high voltage to the gate lines in the MIP driving mode; A MIP driving circuit configured to supply a high potential power voltage and a low potential power voltage to the data lines in the MIP driving mode; A common voltage controller configured to invert the potential of the common voltage by a predetermined time unit in the MIP driving mode after supplying a common voltage having a predetermined voltage to the common electrode in the pre-MIP driving mode; And And a controller for controlling the data driving circuit, the gate driving circuit, the MIP driving circuit, and the common voltage controller. The method of claim 1, The controller, Generating a memory control signal having a different logic value in the pre-MIP driving mode and the MIP driving mode, And controlling the memory driving circuit with the memory control signal. The method of claim 1, The controller, Generating a mode signal having a different logic value in the pre-MIP driving mode and the MIP driving mode; And the MIP driving circuit is controlled by the mode signal. The method of claim 1, Each of the pixels, A liquid crystal cell formed between the pixel electrode and the common electrode; A storage capacitor connected to the liquid crystal cell and the memory driving circuit via an N1 node; And And a first TFT that is turned on in response to the gate high voltage to supply a data voltage from a first data line to the pixel electrode. The method of claim 4, wherein The memory driving circuit, An inverter for inverting the voltage of the N1 node; Interrupts a current path between the N1 node and an input node of the inverter in response to a first logic value of the memory control signal, and sends the N1 node to an input node of the inverter in response to a second logic value of the memory control signal. A second TFT connected to the; And Connect the N1 node to an output node of the inverter in response to a first logic value of the memory control signal, and a current path between the N1 node and an output node of the inverter in response to a second logic value of the memory control signal And a third TFT for blocking the light. The method of claim 5, The third TFT, A 3-1 TFT including a gate electrode to which the memory control signal is supplied, a drain electrode connected to an output node of the inverter, and a source electrode; And And a 3-2 TFT including a gate electrode to which the memory control signal is supplied, a source electrode connected to the N1 node, and a drain electrode connected to the source electrode of the 3-1 TFT. Device. The method of claim 5, The inverter, A fourth TFT including a gate electrode connected to an input node of the inverter, a drain electrode connected to a second data line, and a source electrode connected to an output node of the inverter; And And a fifth TFT including a gate electrode connected to the inverter input node, a source electrode connected to an output node of the inverter, and a drain electrode. The method of claim 6, The memory driving circuit, The first data line is connected to a drain electrode of the fifth TFT in response to a first logic value of the memory control signal, and the first data line and the fifth in response to a second logic value of the memory control signal. And a sixth TFT for blocking a current path between the drain electrodes of the TFT. The method of claim 1, The liquid crystal display panel, And a memory control signal supply line which is connected in common to memory driving circuits of odd lines and even lines to supply the memory control signal to the memory driving circuits of odd lines and even lines. Display. The method of claim 9, And a data voltage having the same polarity is written into the pixels of the odd lines and the pixels of the even lines in the pre-MIP driving mode. The method of claim 1, The memory control signal includes a first memory control signal and a second memory control signal, The liquid crystal display panel, A first memory control signal supply line commonly connected to the memory driving circuits of the odd lines to supply the first memory control signal to the memory driving circuits of the odd lines; And And a second memory control signal supply line which is commonly connected to the memory driving circuits of the even lines and supplies the second memory control signal to the memory driving circuits of the even lines. 11. The method of claim 10, And a data voltage of a first polarity is written in pixels of the odd lines and a data voltage of a second polarity is written in pixels of even lines in the pre-MIP driving mode. 11. The method of claim 10, In the MIP drive mode, The common voltage swings between a first high potential voltage and a first low potential voltage in two frame period periods. And the memory control signal swings between the second high potential voltage and the second low potential voltage in one frame period. The method of claim 13, In the MIP drive mode, And wherein the transition of the common voltage occurs within a time when the voltage of the memory control signal maintains the second low potential voltage. The method of claim 14, The second low potential voltage is, When the low potential power voltage supplied to the data lines in the MIP driving mode is "Vdl", the first high potential power voltage is "Vch", and the first low potential voltage is "Vcl", Vdl -(Vch-Vcl), the liquid crystal display device. The method of claim 15, The second high potential power voltage is, And a high potential power voltage supplied to the data lines in the MIP driving mode. 13. The method of claim 12, At the beginning of the MIP driving mode, the common voltage swings once between a first high potential voltage and a first low potential voltage within a predetermined time, and then swings every two frame periods. The first memory control signal includes a second high potential power voltage and the second low voltage at one frame period after the common voltage is changed to a second low potential voltage when the common low voltage maintains the first low potential voltage at an initial stage of the MIP driving mode. Swing between the potential voltages, The second memory control signal includes the second high potential power supply voltage and the second high potential power supply voltage at one frame period after the common voltage is changed to a second low potential voltage when the common high voltage is maintained at the first high potential voltage. A liquid crystal display device swinging between low potential voltages. A driving method of a liquid crystal display device comprising data lines, gate lines intersecting the data lines, and pixels in which a memory driving circuit is embedded and a pixel electrode and a common electrode are formed. Supplying one of a white gray voltage and a black gray voltage to the data lines through the output channels of the data driving circuit in the pre-MIP driving mode, and then plotting the output channel of the data driving circuit in the MIP driving mode; Sequentially supplying a gate high voltage gate pulse to the gate lines in the pre-MIP driving mode, and then supplying a gate low voltage lower than the gate high voltage to the gate lines in the MIP driving mode; Supplying a high potential power voltage and a low potential power voltage to the data lines by using a MIP driving circuit connected to the data lines in the MIP driving mode; And And inverting the potential of the common voltage by a predetermined time unit in the MIP driving mode after supplying a common voltage having a predetermined voltage to the common electrode in the pre-MIP driving mode. Way.

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