KR101653006B1 - Liquid crystal display and method of reducing power consumption thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which includes data lines, gate lines intersecting with the data lines, TFTs formed at intersections of the data lines and the gate lines, A liquid crystal display panel including the liquid crystal display panel; A timing controller for detecting a vertical blank period without input video data and generating an internal data enable signal and target digital data for a part of the time within the vertical blank period; A data driving circuit for converting the target digital data into a target voltage that is substantially equal to the common voltage, outputting the data to the data lines, and maintaining the target voltage for the vertical blank period; And a gate driving circuit which does not generate an output during the vertical blank period under the control of the timing controller. During the vertical blank period, the TFTs remain off.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,

The present invention relates to a liquid crystal display device and a power consumption reduction method thereof.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

Each of the pixels of the liquid crystal display device includes a TFT connected to the intersection of the data line 105 and the gate line 106 as shown in Fig. The TFT supplies the data voltage supplied through the data line 105 to the pixel electrode 1 of the liquid crystal cell Clc in response to the gate pulse from the gate line 106. [ The liquid crystal cell Clc is rotated by an electric field generated according to the voltage difference between the voltage of the pixel electrode 1 and the common voltage Vcom applied to the common electrode 2 to control the light flux passing through the polarizer. The storage capacitor Cst is connected to the pixel electrode of the liquid crystal cell Clc to hold the voltage of the liquid crystal cell Clc.

The common voltage Vcom applied to the common electrode 2 can be varied by electrical coupling with the pixel electrode 1. [ For example, when a DC voltage generated by a voltage difference of the common voltage Vcom is applied to the data line 105, coupling through the parasitic capacitance Cgs between the source electrode and the gate electrode of the TFT, (Vcom) may be changed.

The liquid crystal display operates on the basis of the timing signals Vsync, Hsync, and DE as shown in FIG. The data enable signal DE is a timing signal defining a period during which one line of valid digital video data is input. The vertical synchronization signal Vsync is a timing signal defining one frame period, and the horizontal synchronization signal Hsync is a timing signal defining one horizontal period. The timing signals (Vsync, Hsync, DE) and the digital video data are input from the external system board to the timing controller of the liquid crystal module. The timing controller samples the digital video data in a data enable (DE) period as a clock signal input from the system board, and transmits the sampled data to the source drive ICs (Integrated Circuit). The source driver IC outputs the digital video data input from the timing controller to the data lines of the liquid crystal display panel. In the active period ACT, the data enable signal DE and valid video data are continuously input from the external system board. During the active period ACT, the vertical synchronization signal Vsync maintains a high logic level. No data enable signal DE is input to the vertical blank period BL. During the vertical blank period BL, the vertical synchronization signal Vsync includes a low logic level period that separates the frame period.

The source drive ICs output the last data voltage of the N (N is a positive integer) frame to the data line 105 and then hold the last data voltage until the first data of the (N + 1) th frame is input. Therefore, during the blank period BL, the last data voltage of the Nth frame is applied to the data lines of the liquid crystal display panel, and the common voltage Vcom is applied to the data lines through the parasitic capacitance Cgs of the TFT Lt; / RTI >

In order to solve such a problem, it is known that during the vertical blank period BL, the timing controller supplies the source drive ICs with virtual data not inputted from the system board to stabilize the common voltage Vcom of the liquid crystal display panel have. However, since the AC voltage is applied to the data lines from the source driver IC, a relatively large power consumption occurs in the liquid crystal display panel due to the transition of the data voltage during the vertical period BL.

Portable information devices, such as mobile phones and notebook computers, must use battery power technology to increase battery life as much as possible. For this purpose, the power consumption of a liquid crystal display device used as a display device of a portable information device should be minimized. As a method for reducing the power consumption of the liquid crystal display device, the vertical blank period BL can be increased by lowering the frame frequency. In this case, when a large amount of power consumption is generated in the liquid crystal display panel during the vertical blank period BL as described above, the power consumption reduction effect becomes small.

The present invention provides a liquid crystal display device capable of minimizing the power consumption of a liquid crystal display panel generated during a vertical blank period, and a power consumption reduction method thereof.

A liquid crystal display device of the present invention is a liquid crystal display device including a liquid crystal cell including data lines, gate lines intersecting with the data lines, TFTs formed at intersections of the data lines and the gate lines, Display panel; A timing controller for detecting a vertical blank period without input video data and generating an internal data enable signal and target digital data for a part of the time within the vertical blank period; A data driving circuit for converting the target digital data into a target voltage that is substantially equal to the common voltage, outputting the data to the data lines, and maintaining the target voltage for the vertical blank period; And a gate driving circuit which does not generate an output during the vertical blank period under the control of the timing controller. During the vertical blank period, the TFTs remain off.

The timing controller detects the vertical blanking period based on a vertical synchronization signal and a data enable signal input from the outside.

The liquid crystal display device has a gate driving circuit which does not generate an output during the vertical blank period.

The timing controller transmits the input image data to the data driving circuit during an active period in which the input image data is input. The data driving circuit converts the input image data into positive / negative data voltages during the active period, and outputs the data voltages to the data lines. The gate driving circuit sequentially outputs gate pulses to the gate lines during the active period.

The target voltage is a DC voltage.

Wherein the timing controller generates a final data enable signal by performing an OR operation on the data enable signal input from the outside and the internal data enable signal and outputs the input data and the target data And transmits the sampled data to the data driving circuit.

The timing controller generates the internal data enable signal at least once and less than four times during the vertical blank period.

A method of reducing power consumption of a liquid crystal display device includes: detecting a vertical blank period in which no input image data is present; Generating an internal data enable signal and target digital data for a portion of time within the vertical blanking period; Converting the target digital data into a target voltage that is substantially equal to the common voltage, supplying the data to the data lines, and maintaining the target voltage for the vertical blank period; And not supplying gate pulses to the gate lines during the vertical blank period.

The present invention generates the internal data enable signal and the target digital data in the timing controller of the liquid crystal display device at the beginning of the vertical blank period. The source drive ICs convert the target digital data to a DC target voltage and supply the voltage to the data lines of the liquid crystal display panel, thereby maintaining the voltage of the data lines at a target voltage of a DC voltage which is substantially equal to the common voltage during the vertical blank period. Therefore, the liquid crystal display of the present invention can suppress the fluctuation of the common voltage during the vertical blank period, and can minimize the power consumption during the vertical blank period.

1 is an equivalent circuit diagram showing pixels of a liquid crystal display device.
2 is a waveform diagram showing timing signals input to the liquid crystal display device.
3 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
FIG. 4 is a circuit diagram showing the timing controller shown in FIG. 3 in detail.
5 is a waveform diagram showing an internal data enable signal according to an embodiment of the present invention.
FIG. 6 is a flowchart showing a control procedure of a power consumption reducing method of a liquid crystal display device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a data driving circuit 102, and a gate driving circuit 103. The data driving circuit 102 includes a plurality of source drive ICs. The gate drive circuit 103 includes a plurality of gate drive ICs.

The liquid crystal display panel 100 includes a TFT array substrate, a color filter array substrate opposed to the TFT array substrate, and a liquid crystal layer formed between the TFT array substrate and the color filter array substrate. In the liquid crystal layer between the TFT array substrate and the color filter array substrate, the liquid crystal cells Clc are arranged in a matrix form defined by the intersection structure of the data lines 105 and the gate lines 106. [

The TFT array substrate includes data lines 105 formed on a lower glass substrate, gate lines 106, TFTs formed at intersections of data lines 105 and gate lines 106, 1, a storage capacitor Cst, and the like. The color filter array substrate includes a black matrix, a color filter, and the like formed on the upper glass substrate. An alignment film is formed on each of the upper glass substrate and the lower glass substrate to attach a polarizing plate and set a pre-tilt angle of the liquid crystal.

The common electrode 2 facing the pixel electrode 1 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) And is formed on the lower glass substrate together with the pixel electrode 1 in a horizontal electric field driving method such as FFS (Fringe Field Switching) mode.

The liquid crystal display panel 100 applicable to the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 supplies digital video data RGB of the input image input from the system board 104 to the data driving circuit 102 during the active period ACT. The timing controller 101 inputs timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the system board 104 And generates control signals for controlling the operation timings of the data driving circuit 102 and the gate driving circuit 103. The control signals include a gate timing control signal for controlling the operation time of the gate drive circuit 103, a data timing control signal for controlling the operation timing of the data drive circuit 102 and the vertical polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the data sampling start timing of the data driving circuit 102. The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source drive ICs on the basis of the rising or falling edge. The polarity control signal POL controls the polarity inversion timing of the data voltages output from each of the source drive ICs. The source output enable signal SOE controls the output timing of the data driving circuit 102. The source start pulse SSP and the source sampling clock SSC may be omitted if the digital video data to be input to the data driving circuit 102 is transmitted in the mini LVDS (Low Voltage Differential Signaling) interface standard.

In order to suppress the variation of the common voltage Vcom supplied to the common electrode 1 during the vertical blank period BL and minimize the power consumption of the liquid crystal display panel 100, the timing controller 101 controls the vertical blank period BL ) And generates target digital data (TD) having a predetermined value during the pulse period of the internal data enable signal (IDE). In addition, the timing controller 101 does not output the gate timing control signals GSP, GSC, and GOE during the vertical blank period BL, and maintains the source output enable signal SOE at a low logic level.

Each of the source driver ICs of the data driving circuit 102 includes a shift register, a latch, a digital-analog converter, an output buffer, and the like. The source drive ICs are mounted on a source TCP (Tape Carrier Package), bonded to a TFT array substrate of a liquid crystal display panel by a TAB (Tape Automated Bonding) process, and connected to a source PCB (Printed Circuit Board). The source drive ICs may be bonded on the TFT array substrate of the liquid crystal display panel by a COG (Chip On Glass) process. The data output channels of each of the source drive ICs are connected in a 1: 1 manner to the data lines 105. The source drive ICs latch digital video data RGB input from the timing controller 101 during the active period ACT. The source driver ICs then convert the digital video data RGB to an analog positive / negative gamma compensation voltage in response to the polarity control signal POL to invert the polarity of the data voltage. The source drive ICs output the data voltages to the data lines 105 during the low logic level interval of the source output enable signal SOE.

The source drive ICs convert the target digital data TD input from the timing controller 10 into a positive / negative gamma compensation voltage during the vertical blank period BL to generate a target voltage, And outputs it to the data lines 105 in response to the source output enable signal SOE maintaining the level. The voltage of the data lines 105 during the vertical blank period BL is maintained at the target voltage. During the vertical blank period BL, the target voltage held in the data lines 105 is a DC voltage having substantially no potential difference from the common voltage Vcom. Therefore, during the vertical blank period BL, the common voltage Vcom is not changed since the target voltage substantially equal to the common voltage Vcom is held in the data lines 105. [ During the vertical blank period (BL), the source drive ICs and the liquid crystal display panel generate almost no current because the DC voltage without the transistor is maintained.

The gate driving circuit 103 responds to the gate timing control signals GSP, GSC and GOE inputted from the timing controller 101 during the active period ACT by using the shift register and the level shifter, (106). The gate driving circuit 103 is mounted on a gate TCP (not shown) and bonded to a TFT array substrate of a liquid crystal display panel by a TAB process, or is formed on a TFT array substrate by a GIP (Gate In Panel) Can be formed directly.

The gate drive circuit 103 does not output the gate pulse since the gate timing control signals GSP, GSC, and GOE are not generated during the vertical blank period BL. Therefore, the TFTs of the TFT array substrate maintain the OFF state, so that the target voltage is not supplied to the liquid crystal cells Clc.

FIG. 4 is a circuit diagram showing the timing controller 101 shown in FIG. 3 in detail. 5 is a waveform diagram showing an internal data enable signal according to an embodiment of the present invention.

4 and 5, the timing controller 101 includes an internal data enable signal generating unit 11, an OR gate 12, a data transfer unit 13, a timing control signal generating unit 14, do.

The internal data enable signal generator 11 counts the vertical synchronization signal Vsync and the data enable signal DE input from the external system board 104 and outputs a vertical blanking period (BL). The internal data enable signal generator 11 generates one or more internal data enable signals IDE within the initial 1/2 period of the vertical blank period BL. The pulse width of the internal data enable signal IDE is substantially the same as that of the data enable signal DE input from the outside. During the vertical blank period BL, the system board 104 does not generate the data enable signal DE and the vertical synchronization signal Vsync includes the low logic level interval.

The OR gate 12 performs an OR operation on the internal data enable signal IDE from the internal data enable signal generator 11 and the data enable signal DE from the system board 104, As a final data enable signal FDE.

The data transfer unit 13 samples and reorders the valid digital video data RGB input during the active period ACT with the final data enable signal FDE and the clock signal CLK and transmits them to the source drive ICs. During the vertical blank period BL, the data transfer unit 13 reads the target digital data stored in the built-in register and transfers it to the source drive ICs.

The timing control signal generating unit 14 generates the data timing control signals SSP and SSB so that the valid digital video data RGB can be addressed to the liquid crystal cells Clc of the liquid crystal display panel 100 during the active period ACT. SSC, SOE, POL) and gate timing control signals (GSP, GSC, GOE). The timing control signal generating section 14 does not output the gate start pulse GSP and maintains the source output enable signal SOE at a low logic level during the vertical blank period BL. During the vertical blank period BL, the gate shift clock GSC and the gate enable signal GOE can be output. During the vertical blank period BL, the gate driving circuit 103 generates an output (gate pulse) if the gate shift clock GSC and the gate enable signal GOE are input but the gate start pulse GSP is not input It is not. During the vertical blank period BL, when the source output enable signal SOE maintains the low logic, the other data timing control signals SSP, SSC, and POL can not have any influence on the liquid crystal display panel 100, May be generated with pulses of the same period as the period ACT.

FIG. 6 is a flowchart showing a control procedure of a power consumption reducing method of a liquid crystal display device according to an embodiment of the present invention.

6, the timing controller 101 receives input image data and timing signals (Vsync, Hsync, DE, CLK) from an external system board. (S1)

The timing controller 101 detects the vertical blanking period BL based on the vertical synchronization signal Vsync and the data enable signal DE. The timing controller 101 generates one or more internal data enable signals IDE at the beginning of the vertical blank period BL and generates and transmits target digital data TD to the source drive ICs S2 and S3 )

The source drive ICs output a target voltage that is substantially equal in potential to the common voltage Vcom in response to the source output enable signal that maintains a low logic level during the vertical blank period BL and supplies the target voltage to the vertical blank period BL. (S4).

The timing controller 101 detects the active period ACT based on the vertical synchronization signal Vsync and the data enable signal DE. The timing controller 101 samples and reorders the valid digital video data RGB during the active period ACT and transmits them to the source drive ICs.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: liquid crystal display panel 101: timing controller
102: Data driving circuit 103: Gate driving circuit

Claims (10)

A liquid crystal display panel including data lines, gate lines intersecting with the data lines, TFTs formed at intersections of the data lines and the gate lines, and liquid crystal cells supplied with a common voltage;
A timing controller for detecting a vertical blank period without input video data and generating an internal data enable signal and target digital data for a part of the time within the vertical blank period;
A data driving circuit for converting the target digital data into a target voltage that is substantially equal to the common voltage, outputting the data to the data lines, and maintaining the target voltage for the vertical blank period; And
And a gate driving circuit which does not generate an output during the vertical blank period under the control of the timing controller,
And the TFTs remain off during the vertical blank period. The method according to claim 1,
The timing controller includes:
Wherein the vertical blanking period is detected based on a vertical synchronization signal and a data enable signal input from the outside. delete The method according to claim 1,
The timing controller includes:
The input video data is transmitted to the data driving circuit during an active period in which the input video data is input,
The data driving circuit includes:
A data driver for converting the input image data into positive / negative data voltages and outputting the data to the data lines during the active period,
The gate drive circuit includes:
And sequentially outputs gate pulses to the gate lines during the active period. The method according to claim 1,
Wherein the target voltage is a DC voltage. 3. The method of claim 2,
The timing controller includes:
A data enable signal input from the outside and the internal data enable signal to generate a final data enable signal,
Sampling the input video data and the target digital data based on the final data enable signal, and transmitting the sampled input video data and the target digital data to the data driving circuit. The method according to claim 1,
The timing controller includes:
Wherein the internal data enable signal is generated at least once and less than four times during the vertical blank period. A liquid crystal display including a liquid crystal display panel including data lines, gate lines intersecting with the data lines, TFTs formed at intersections of the data lines and the gate lines, and liquid crystal cells supplied with a common voltage A method for reducing power consumption of a device,
Detecting a vertical blanking period without input video data;
Generating an internal data enable signal and target digital data for a portion of time within the vertical blanking period;
Converting the target digital data into a target voltage that is substantially equal to the common voltage, supplying the data to the data lines, and maintaining the target voltage for the vertical blank period; And
And not supplying gate pulses to the gate lines during the vertical blank period,
And the TFTs remain off during the vertical blank period. 9. The method of claim 8,
Wherein the step of detecting the vertical blank period comprises:
Wherein the vertical blanking period is detected based on a vertical synchronization signal and a data enable signal input from the outside. delete

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