KR102118928B1 - Display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device.
The liquid crystal display according to the present invention is a timing controller that outputs a gate-on-clock input signal including gate-on timing information and a gate-off clock input signal including gate-off timing information, and a start pulse of the gate-on clock input signal. And a signal divider for separating the gate off-clock into a start pulse and a gate off-clock, and in response to the start pulse, the gate on-clock and the gate off-clock. A level shifter for outputting a gate pulse driving the gate line is provided.

Description

Liquid crystal display device {DISPLAY DEVICE}

The present invention relates to a liquid crystal display device.

A liquid crystal display device forms a liquid crystal layer having an anisotropic dielectric constant between upper and lower transparent substrates, and adjusts the intensity of an electric field formed in the liquid crystal layer according to video data to change a molecular arrangement of liquid crystal materials to display a desired image. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), and is widely used in portable information devices, office equipment, computers, and televisions.

The timing controller of the liquid crystal display device receives and rearranges an image signal from an external system and generates various signals for controlling the timing of the gate driver. Among them, the timing controller 22 generates a start pulse (VST) indicating the start of an image frame and a gate on/off-clock for controlling the timing of the gate driver.

The timing controller includes output pins corresponding to each signal to output each signal. Therefore, in order to change the algorithm of the timing controller or to output a new signal, the pin of the timing controller must be newly added. That is, the conventional timing controller has a disadvantage of low flexibility in design change to perform a new function or operation due to the limitation of the output pin.

The present invention is to provide a liquid crystal display device that can increase the degree of freedom of design change of the timing controller.

The liquid crystal display according to the present invention is a timing controller that outputs a gate-on-clock input signal including gate-on timing information and a gate-off clock input signal including gate-off timing information, and a start pulse of the gate-on clock input signal. And a signal divider for separating the gate off-clock into a start pulse and a gate off-clock, and in response to the start pulse, the gate on-clock and the gate off-clock. A level shifter for outputting a gate pulse driving the gate line is provided.

Since the present invention can reduce the number of output pins used in the process of transmitting signals for controlling the timing of the gate driver of the timing controller, it is possible to secure an extra output pin compared to the prior art. Therefore, the present invention can facilitate the design change of the timing controller.

1 is a view showing a liquid crystal display device according to a first embodiment.
2 is a timing diagram of various control signals for driving the liquid crystal display device.
3 is a circuit diagram of a signal summing unit according to the present invention.
4 is a waveform diagram of input and output signals of a signal summing unit.
5 is a circuit diagram of a signal division unit according to the present invention.
6 is a waveform diagram of input and output signals of a signal division unit.
7 is a view showing a liquid crystal display device according to a second embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description is omitted.

The liquid crystal display device of the present invention may be implemented in any form, such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. A backlight unit is required in a transmissive liquid crystal display device and a transflective liquid crystal display device. The liquid crystal mode applicable in the present invention is a vertical electric field driving method such as a twisted nematic (TN) mode and a vertical alignment (VA) mode, or a horizontal electric field driving such as an in-plane switching (IPS) mode and a fringe field switching (FSF) mode. The method may be applied, and in addition, all currently known liquid crystal modes may be applied.

In addition, although the embodiment of the present invention is mainly described as a liquid crystal display device of the GIP type, it can also be applied to a liquid crystal display device to which a gate drive IC is applied.

1 is a view showing a liquid crystal display device in a first embodiment of the present invention, Figure 2 is a view showing the timing of various control signals for driving the liquid crystal display device.

1 and 2, the display device of the present invention includes a liquid crystal panel 10, a source driver IC 24, a GIP type gate driver, a timing controller 22, a signal divider 25, and a level shifter ( 26).

The liquid crystal panel 10 includes a pixel array displaying an input image. The pixel array may be divided into a TFT array formed on the lower substrate, a color filter array formed on the upper substrate, and liquid crystal cells Clc. The TFT array includes data lines 11, gate lines (or scan lines 12) intersecting the data lines 11, TFTs formed at each intersection of the data lines and the gate lines, and pixels connected to the TFT It includes an electrode 1, a storage capacitor (Cst). A color filter array including a black matrix and a color filter is formed on the upper substrate of the liquid crystal panel 10. The common electrode 2 may be formed on the lower substrate or the upper substrate. The liquid crystal cells Clc are driven by an electric field between the pixel electrode 1 to which the data voltage is supplied and the common electrode 2 to which the common voltage Vcom is supplied.

The timing controller 22 supplies digital video data (RGB) received from the outside to the source driver IC 24. In addition, the timing controller 22 receives a data enable (DE), a horizontal sync signal (Hsync), and a vertical sync signal (Vsync) to start pulse (VST), gate on-clock (ON_CLK) and gate off- The clock (OFF_CLK) is generated. In particular, the timing controller 22 outputs a gate on-clock input signal ON_CLK_I including gate on timing information and a gate off-clock input signal OFF_CLK_I including gate off timing information. To this end, the timing controller 22 sums the start pulse VST and the gate on-clock ON_CLK to generate the gate on-clock input signal ON_CLK_I, and the start pulse VST and the gate off-clock OFF_CLK ), and a signal summing unit 23 for generating a gate off-clock input signal OFF_CLK_I.

The source drive ICs 24 receive digital video data RGB from the timing controller 22. The source drive ICs 24 convert digital video data RGB into a positive/negative analog data voltage in response to a source timing control signal from the timing controller 22, and then synchronize the data voltage to the gate pulse. It is supplied to the data lines of the liquid crystal panel 10 whenever possible. The source drive ICs 24 may be connected to data lines 11 of the liquid crystal panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process. The source drive ICs 24 in FIG. 2 show an example mounted on a tape carrier package (TCP). The printed circuit board (hereinafter referred to as PCB) 20 is connected to the lower substrate of the liquid crystal panel 10 via TCP.

The GIP type gate driver includes a level shifter 26 mounted on the PCB 20 and a shift register 30 formed on the lower substrate of the liquid crystal panel 10.

The signal splitter 25 separates the gate on-clock input signal ON_CLK_I provided from the timing controller 22 into a start pulse and a gate on-clock ON_CLK, and starts the gate off-clock input signal OFF_CLK_I. It is separated by pulse VST and gate off-clock (OFF_CLK).

The level shifter 26 receives a start pulse VST, a gate on-clock (ON_CLK), and a gate off-clock (OFF_CLK) from the signal division unit 22, a gate high voltage (VGH), and a gate low voltage (VGL) ) And output a gate pulse. The start pulse VST, the gate on-clock (ON_CLK), the gate off-clock (OFF_CLK), and the flicker signal FLK are signals swinging between 0V and 3.3V. The gate on-clock ON_CLK and the gate off-clock OFF_CLK are n-phase clocks having a predetermined phase difference, and control the output timing of the gate pulses G1 to G4.

The level shifter 26 converts the start pulse (VST), gate on-clock (ON_CLK), and gate off-clock (OFF_CLK) input from the timing controller 22 into a gate high voltage (VGH) and a gate low voltage (VGL). Level shifting. Accordingly, the start pulse VST output from the level shifter 26 and the gate on-clock ON_CLK and gate off-clock OFF_CLK swing between the gate high voltage VGH and the gate low voltage VGL.

The level shifter 26 may be any known GIP type level shifter, so detailed circuit configuration and operation waveforms thereof will be omitted.

The output signals of the level shifter 26 are wires formed on the TCP of the first source drive IC 24a disposed on the upper left of the liquid crystal panel 10, and LOG wires formed on the lower substrate of the liquid crystal panel 10 ( 32) can be supplied to the shift register 30. The shift register 30 is formed directly on the lower substrate of the liquid crystal panel 10 by a GIP process.

The shift register 30 shifts the start pulse VST input from the level shifter 26 according to the gate on-clock/gate off-clock (ON_CLK, OFF_CLK), thereby causing the gate high voltage VGH and the gate low voltage VGL. ) To sequentially shift the gate pulse swinging between. Any of the known GIP type shift registers may be applied to the shift register 30, so a detailed description thereof will be omitted.

Signals swinging between the gate high voltage VGH and the gate low voltage VGL are supplied to the LOG wirings 32.

3 is a circuit diagram showing the signal summing section 23 of the timing controller 22, and FIG. 4 is a diagram showing the input and output waveforms of the signal summing section 23.

3 and 4, the signal summing unit 23 generates a gate-on-clock input signal by summing the start pulse VST and the gate on-clock ON_CLK, and the start pulse VST and gate off -The clock (OFF_CLK) is summed to generate a composite gate-off clock. To this end, the signal summing unit 23 includes a first OR operator 310 and a second OR operator 320.

The first OR operator 310 receives the start pulse VST and the gate on-clock ON_CLK to perform the OR operation, thereby generating the gate on-clock input signal ON_CLK_I. Accordingly, the gate on-clock input signal ON_CLK_I maintains high logic for a section in which any one of the start pulse VST or the gate on-clock ON_CLK is high logic.

The second OR operator 320 receives the start pulse VST and the gate off-clock OFF_CLK to perform the OR operation, thereby generating a gate off-clock input signal OFF_CLK_I. Therefore, the gate off-clock input signal OFF_CLK_I maintains high logic for a section in which any one of the start pulse VST or the gate off-clock OFF_CLK is high logic.

5 is a circuit diagram showing the signal division unit 25, and FIG. 6 is a waveform diagram showing the input and output signals of the signal division unit 25.

The signal division unit 25 receives the gate on-clock input signal ON_CLK_I and the gate off-clock input signal OFF_CLK_I output from the signal summing unit 23 and starts pulse VST and gate on-clock ON_CLK ) And gate off-clock (OFF_CLK). To this end, the signal division unit 25 includes first to third logical product operators 410,420,4300 and an inverter 440.

The first logical product operator 410 receives the gate on-clock input signal ON_CLK_I and the gate off-clock input signal OFF_CLK_I and performs a logical product operation to output a start pulse VST. The gate on-clock input signal ON_CLK_I and the gate off-clock input signal OFF_CLK_I are the same as the high logic period of the start pulse VST in which the overlapping high logic period is input to the signal summing unit 23. Therefore, the first logical product operator 410 may perform a logical product operation to extract the start pulse VST from the gate on-clock input signal ON_CLK_I and the gate off-clock input signal OFF_CLK_I.

The inverter 440 inverts the phase of the start pulse VST of the first logical product operator 410 and outputs a phase inverted start pulse VST.

The second logical multiplication operator 420 receives the gate on-clock input signal ON_CLK_I and the phase inversion start pulse VST and performs a logical multiplication operation to output the gate on-clock ON_CLK.

The third logical multiplication operator 430 receives the gate off-clock input signal OFF_CLK_I and the phase inversion start pulse VST and performs a logical multiplication operation to output the gate off-clock OFF_CLK.

As described above, the timing controller 22 according to the present invention sums the start pulse VST, the gate on-clock (ON_CLK), and the gate off-clock (OFF_CLK) using the signal summing unit 23 to turn on the gate. -The clock input signal (ON_CLK_I) and the gate off-clock input signal (OFF_CLK_I) are output. In addition, the signal division unit 25 separates the gate on-clock input signal ON_CLK_I and the gate off-clock input signal OFF_CLK_I to start pulse VST, gate on-clock ON_CLK and gate off-clock OFF_CLK ).

As a result, the timing controller 22 may transmit the start pulse VST, the gate on-clock (ON_CLK), and the gate off-clock (OFF_CLK) using two pins. Therefore, the redundancy of the pins of the timing controller 22 can be secured, so that it is not necessary to design new pins even when additional functions are added.

7 is a view showing a liquid crystal display device according to a second embodiment.

The same reference numerals are used for components that are functionally identical to the above-described embodiment in FIG. 7, and detailed descriptions thereof will be omitted.

The liquid crystal display according to the second embodiment includes a power IC 40 including a signal summing unit 23 and a level shifter 26. The power IC 40 generates voltage levels such as VGH, VGL, VCC, VDD, HVDD, and RST. VCC may be a voltage of 3.3V as a logic power supply voltage for driving the timing controller 22, the source drive ICs 24, and the like. VDD and HVDD are the high-potential power supply voltage and 1/2 the high-potential power supply voltage to be supplied to the voltage divider circuit of the gamma reference voltage generating circuit that generates positive/negative gamma reference voltages. Positive/negative gamma reference voltages are supplied to the source drive ICs 24. RST is a reset signal for resetting the timing controller 22, and may be 3.3V. VGH and VGL are the high-level and low-level voltages of the gate pulse. The power IC 40 generates VGH and VGL and provides it to the level shifter 26, and the level shifter 26 provides gate on/off-clock (ON_CLK/OFF_CLK) transmitted by the signal splitter 25 with VGH. Level shift to swing between VGLs.

The first and second embodiments describe an example applied to a liquid crystal display device having a GIP structure. In addition to this, the present invention may be used in a liquid crystal display device using a gate drive IC. That is, the start pulse VST, the gate on-clock ON_CLK, and the gate off-clock OFF_CLK output from the signal division unit 25 may be transmitted to the level shifter of the gate drive IC. Alternatively, the signal division unit 25 may be implemented in a configuration included in the gate drive IC.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

10: liquid crystal panel 20: PCB
22: timing controller 23: signal summing section
24: source drive IC 26: level shifter
30: shift register 32: LOG wiring

Claims (5)

The start pulse and the gate on-clock are summed to output a gate on-clock input signal including gate on timing information, and the start pulse and the gate off-clock are summed to gate off-clock input signal including gate off timing information. Timing controller for outputting;
A signal divider for separating the gate on clock input signal into the start pulse and the gate on-clock, and separating the gate off-clock input signal into the start pulse and the gate off-clock; And
And a level shifter outputting a gate pulse driving the gate line of the liquid crystal panel in response to the start pulse, the gate on-clock and the gate off-clock,
The signal division unit
A first logical product operator that receives the gate on-clock input signal and the gate off-clock input signal and performs a logical product operation to output the start pulse;
An inverter that inverts the phase of the start pulse, which is the output of the first logical multiplier, and outputs a phase inverted start pulse;
A second logical product operator that receives the gate on-clock input signal and the phase inverted start pulse and performs a logical product operation to output the gate on-clock; And
And a third logical product operator for outputting the gate off-clock by performing a logical product operation by receiving the gate off-clock input signal and the phase inversion start pulse.
delete According to claim 1,
The timing controller
A first OR operator that receives the start pulse and the gate on-clock and performs the OR operation, thereby outputting the gate on-clock input signal; And
And a second OR operator outputting the gate off-clock input signal by performing the OR operation by receiving the start pulse and the gate off-clock.
delete According to claim 1,
The signal divider and the level shifter is a liquid crystal display device, characterized in that included in the power IC.

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