KR102277714B1 - Gate Driver and Display Device having thereof - Google Patents

Abstract

The present invention discloses a gate driver and a display device having the same. The disclosed gate driver of the present invention is a gate driver that generates a sensing signal and a scan signal for supplying to a display panel, comprising a receiver receiving a packet signal and a clock signal supplied to the gate driver, and recovering from the receiver a memory storing the gate timing control signals, a shift register receiving gate timing control signals output by a start signal supplied to the memory, and outputting a sensing signal and a scan signal generated by the shift register By including the output unit, the number of signal lines disposed on the display panel is reduced and the bezel area is reduced.

Description

Gate driver and display device having same

The present invention relates to a display device, and more particularly, to a gate driver having a reduced bezel area by reducing signal lines by simplifying signals supplied to a display panel, and a display device having the same.

Recently, various flat panel displays (FPDs) capable of reducing weight and volume, which are disadvantages of cathode ray tubes, have been developed. Such flat panel displays include a liquid crystal display, a field emission display (FED), a plasma display panel (hereinafter referred to as "PDP"), an electroluminescence device, and the like. There is this.

1 is a block diagram illustrating a conventional display device, and FIG. 2 is a block diagram in which a bezel area and corresponding signal lines are divided in a non-display unit.

1 and 2 , a conventional display device 10 includes a display panel including a display unit 20 for displaying an image and a non-display unit 30 disposed along the periphery of the display unit 20 , and the display panel The gate driver 12 and the data driver 13 disposed in the non-display portion 30 area of the printed circuit board 50 (Flexible) supplying a plurality of control signals to the gate driver 12 and the data driver 13 printed circuit).

The printed circuit board 50 includes a timing controller (not shown) that generates signals supplied to the gate driver 12 and the data driver 13 .

As the display device 10 has recently increased in size and high resolution, a signal line is used to supply signals supplied to the gate driver 12 and the data driver 13 to the gate lines and data lines of the display unit 20 . A line on glass (LOG) display device in which the elements 40 are directly formed on a display panel has been proposed.

In addition, although not directly shown in the drawings, there is a Chip On Glass (COG) display device that directly mounts a gate driver integrated circuit (“IC”) 12a or a data driver IC on a display panel. has been proposed

The line-on-glass or chip-on-glass display devices as described above have a common feature in that a plurality of signal lines are formed on a display panel.

Referring to FIG. 2 , a plurality of gate driver ICs 12a are disposed in the gate driver 12 , and a plurality of gate timing control signals are supplied to the gate driver 12 .

For example, the input signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and a vertical output enable signal. signals (Vertical Output Enabel, VOE), Vertical Start Pulse (VSP), and the like.

In addition, a power signal of a gate high voltage VGH and a gate low voltage VGL supplied to a level shift in the gate driver 12 is included.

In addition, voltages (VCC, GVCC) supplied to the transistors inside the IC and, when the display panel is for a TV, option signals (SHL, Mode), etc. are included.

Since the signals are supplied to the gate driver 12 through the signal lines 40 formed on the display panel, there is a problem in that the area of the non-display unit 30 is increased.

Accordingly, in the case of the line-on-glass display device, there is a problem in that the width D1 of the bezel region increases by the number of the input signal, gate high/low voltage, transistor supply voltage, and option signals.

Also, as described above, when the number of signal lines in the display panel increases, the number of connector pins formed on the gate driver IC 12a, the data driver IC (not shown), and the printed circuit board 50 connected thereto increases. do.

In addition, since the printed circuit board 50 must arrange an output buffer corresponding to the signal lines 40 formed on the display panel, there is a limit in reducing the size of the printed circuit board 50 .

The present invention provides a gate driver that reduces the number of signal lines disposed on a display panel and reduces a bezel area by converting input signals and option signals supplied to the gate driver into packet-type differential signals and supplying them It is an object to provide a display device equipped with.

Another aspect of the present invention is to provide a gate driver in which the number of signal lines connected to the gate driver is reduced by arranging a receiver capable of receiving a differential signal and a memory in the gate driver IC of the gate driver, and a display device having the same. There is a purpose.

In order to solve the problems of the prior art as described above, the gate driver of the present invention provides a packet signal and a clock signal supplied to the gate driver in the gate driver for generating a sensing signal and a scan signal to be supplied to a display panel. a receiving unit including a receiving unit, including a memory storing the gate timing control signals restored by the receiving unit, and a shift register receiving gate timing control signals output by a start signal supplied to the memory, the shift register By including an output unit for outputting the sensing signal and the scan signal generated by the , the number of signal lines disposed on the display panel is reduced and the bezel area is reduced.

In addition, the display device of the present invention includes a display panel having a display unit and a non-display unit, and a gate driver that generates a sensing signal and a scan signal supplied to the display panel, wherein the gate driver includes a packet signal and a clock signal. A receiving unit receiving a signal, a memory storing the gate timing control signals restored by the receiving unit, a shift register receiving gate timing control signals output by a start signal supplied to the memory, and the shift register being generated By including an output unit for outputting a sensing signal and a scan signal, the number of signal lines connected to the gate driver is reduced.

A gate driver and a display device having the same according to the present invention convert input signals and option signals supplied to the gate driver into differential signals in the form of packets and supply them, thereby reducing the number of signal lines arranged on a display panel. It has the effect of reducing the bezel area.

In addition, the gate driver and the display device having the same according to the present invention have the effect of reducing the number of signal lines connected to the gate driver by arranging a receiving unit and a memory capable of receiving a differential signal in the gate driver IC of the gate driver. have.

1 is a block diagram illustrating a conventional display device.
2 is a block diagram in which a bezel area and corresponding signal lines are divided in a non-display unit.
3 is a diagram illustrating a display device according to an embodiment of the present invention.
4 is a block diagram showing the structure of a gate driver IC disposed in a gate driver according to the present invention.
5 is a detailed circuit diagram of a gate driver IC according to the present invention.
6 is a diagram illustrating a width of a bezel area of a display device according to the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, when a temporal relationship is described as 'after', 'following', 'after', 'before', etc., 'immediately' or 'directly' Unless ' is used, cases that are not continuous may be included.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. And in the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals refer to like elements throughout.

3 is a diagram illustrating a display device according to an embodiment of the present invention, FIG. 4 is a block diagram illustrating a structure of a gate driver IC disposed in a gate driver according to the present invention, and FIG. 5 is a gate according to the present invention. It is a detailed circuit diagram of the driver IC.

3 to 5 , the display device 100 according to an embodiment of the present invention includes a display panel 120 , a timing controller 121 , a source driver 122 , and a gate driver 123 . The source driver 122 and the gate driver 123 are directly disposed on the substrate of the display panel 120 .

In addition, the gate driver 123 includes a plurality of gate driver ICs, and each gate driver IC 200 includes a receiver 101 for receiving a differential signal in the form of a packet, and a receiver 101 . A memory 102 for storing the received differential signal, a shift register 103 operating by receiving signals stored in the memory 102, and a scan signal output from the shift register 103 and sensing and an output unit 104 for outputting a signal (Sensing Signal).

The display device 100 according to the embodiment of the present invention includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode display (PDP). It may be implemented as a flat panel display device such as an organic light emitting display (OLED) or an electrophoresis display (EPD). In the following embodiments, the display device will be described with a focus on the liquid crystal display, but it should be noted that the display device of the present invention is not limited to the liquid crystal display.

The display panel 120 includes liquid crystal molecules disposed between two glass substrates. In the display panel 120 , m×n (m, n is a positive integer) liquid crystal cells Clc in a matrix form by an intersecting structure of the data lines D1 to Dm and the gate lines G1 to Gn. ) is placed.

Pixel electrodes of the liquid crystal cell Clc respectively connected to m data lines D1 to Dm, n gate lines G1 to Gn, TFTs, and TFTs are provided on the lower glass substrate of the display panel 120 . (1), and a pixel array including storage capacitors Cst and the like is formed.

A black matrix, a color filter, and a common electrode 2 are formed on the upper glass substrate of the display panel 120 . The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode and It is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving method.

A polarizing plate having an optical axis orthogonal to each other is attached to the upper glass substrate and the lower glass substrate of the display panel 120 , and an alignment layer for setting a pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

The source driver 122 latches digital video data RGB under the control of the timing controller 121 and converts the digital video data into analog positive/negative gamma compensation voltages to generate positive/negative data voltages. and the data voltage is supplied to the data lines D1 to Dm.

The source driver 122 may be mounted on a tape carrier package (TCP) and bonded to the lower glass substrate of the display panel 120 by a tape automated bonding (TAB) process.

The shift register 103 disposed in the gate driver IC 200 of the gate driver 123 corresponds to odd-numbered and even-numbered gate lines to the gate lines G1 to Gn disposed on the display panel 120 . and at least one or more shift registers (Shift Registers: 103).

Accordingly, if the display device 100 is a liquid crystal display device, the sensing signal and the scan signal output from the shift register 103 may be an odd-numbered gate signal and an even-numbered gate signal, respectively.

However, when the display device 100 is an organic light emitting display device, signals supplied to the switching elements of each pixel may be referred to as a scan signal and a sensing signal.

The shift register 103 of the gate driver IC 200 includes a plurality of stages 103_1, 103_2, 103_3, 103_4, 103_5, 103_6, 103_7, 103_8, .. .

In addition, the output unit 104 of the gate driver IC 200 includes a plurality of first logic devices 200_1, 200_2, 200_3, 200_4, 200_5, 200_6, 200_7, 200_8, ..), and a plurality of level shifts (Level). Shift: 210_1, 210_2, 210_3, 210_4, 210_5, 210_6, 210_7, 210_8,...) and multiple buffers (buffers: 220_1, 220_2, 220_3, 220_4, 220_1, 220_2, 220_3, 220_4,...) include

In addition, the output unit 104 controls the output of the gate signal by gate output enable signals (Gate Output Enable, GOE, GOE_AO, GOE_BO, GOE_AE, GOE_BE). The second logic elements 160_1 , 160_2 , 160_3 , and 160_4 may be disposed between the signals GOE.

The gate driver 123 sequentially supplies a sensing signal and scan signals (gate signals) having a pulse width of approximately one horizontal period to the gate lines G1 to Gn under the control of the timing controller 121 . The gate driver 123 is mounted on the TCP and bonded to the lower glass substrate of the display panel 120 by the TAB process, or is directly formed on the lower glass substrate simultaneously with the pixel array by the GIP (Gate In Panel) process. can

The timing controller 121 rearranges digital video data RGB input from a system board (not shown) to fit the display panel 120 and supplies it to the source driver 122 .

The timing controller 121 receives timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync), data enable, and clock signals (including main clock signals such as CLK and MCLK) from the system board. Control signals for controlling operation timings of the source driver 122 and the gate driver 123 are generated.

The data timing control signal for controlling the source driver 122 includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output in It includes an enable signal (Source Output Enable, SOE) and the like. The source start pulse SSP controls the data sampling start timing of the source driver 122 . The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source driver 122 based on a rising or falling edge. The source output enable signal SOE controls the output timing of the source driver 122 . The polarity control signal POL controls the horizontal polarity inversion timing of the data voltage output from the source driver 122 .

A gate timing control signal (Input Signal) for controlling the gate driver 123 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output in the input signal. It includes an enable signal (Gate Output Enable, GOE), a vertical output enable signal (Vertical Output Enabel, VOE), a vertical start pulse (VSP), and the like.

In particular, in the present invention, the gate timing control signal (Input Signal) is converted into a differential signal and then supplied to the gate drive IC 200 in the form of a PACKET signal. Accordingly, two signal lines for supplying the gate timing control signal are sufficient.

Because the present invention receives a differential signal (packet signal) in the LVDS (Low-Voltage Differential Signaling) method, the receiver 101 of the gate driver IC 200 restores the gate timing control signals to the shift register 103. because they can supply it.

Accordingly, the receiver 101 may include a serial converter or a serial-to-parallel converter, and may process a signal in the form of a clock and a packet by restoring the signal as an interface.

The LVDS has a fast bit rate, lower power consumption, and excellent noise performance.

Accordingly, in the prior art, each signal corresponding to the gate timing control signal and the number of signal lines formed on the display panel 120 were matched 1:1, but in the present invention, a plurality of gate timing control signals are applied to two signal lines. By supplying it to the gate driver IC 200 through the gate driver IC 200, the number of signal lines and the width of the bezel region can be reduced.

That is, the receiving unit 101 disposed in the gate driver IC 200 receives a packet signal (differential signal) and a clock signal CLK obtained by packetizing the gate timing control signals, and then transmits them to a plurality of gate timing control signals. is restored and supplied to the memory 102 .

The memory 102 receives a plurality of gate timing control signals GOE AO, GOE BO, GOE AE, GOE BE, GSP A, and GSC in response to a start signal (ST) and a clock signal supplied from an external system. , GSP B) is supplied to the shift register 103 .

Accordingly, the gate timing control signals supplied to the shift register 103 are the same as the control signals directly supplied from the conventional timing controller 121 .

Accordingly, since the operation of the shift register 103 is the same as that of the prior art, a detailed description thereof will be omitted.

That is, in the present invention, since the gate timing control signals are converted into differential signals and supplied from the external system to the gate driver 123 region, the number of signal lines formed in the display panel 120 can be reduced.

However, in the gate driver IC 200, the operation of the gate driver IC 200 is implemented in the same manner as in the prior art because the data is supplied to the shift register 103 after being restored by the receiver 101 and the memory 102.

As described above, in the gate driver and the display device having the same according to the present invention, input signals and option signals supplied to the gate driver are converted into packet-type differential signals and supplied, thereby providing signal lines arranged on the display panel. It has the effect of reducing the number of devices and reducing the bezel area.

In addition, the gate driver and the display device having the same according to the present invention have the effect of reducing the number of signal lines connected to the gate driver by arranging a receiving unit and a memory capable of receiving a differential signal in the gate driver IC of the gate driver. have.

In addition, since the number of signal lines formed on the display panel 120 is reduced, the number of connector pins connecting the printed circuit board and the signal lines can be reduced, and the number of output buffers in the printed circuit board can also be reduced. .

In addition, when the number of output buffers of the printed circuit board is reduced, the size of the printed circuit board can be reduced, and the manufacturing process cost can be reduced.

6 is a diagram illustrating a width of a bezel area of a display device according to the present invention.

Referring to FIG. 6 , only input signal lines, power signal lines (VGH, VGL) and voltages (VCC, GVCC) in the form of a packet signal (PACKET) are formed on the display panel of the display device of the present invention, so that the bezel of the prior art The width D2 may be reduced by 30-40% compared to the width (D1 in FIG. 2 ).

The input signal line is two signal lines for supplying a differential signal, one clock signal line and a start pulse (ST) signal line.

In addition, since the packet signal may include the option signal SHL, Mode together with the gate control signals (gate input signals), the option signal lines, which are conventionally formed to supply the option signals, can also be removed.

In addition, in the present invention, although the signal can be supplied by the LVDS method, this is not fixed, so it can be implemented with a clock pin (PIN) or an embedded clock (Embedded CLK) method.

As described above, in the gate driver and the display device having the same according to the present invention, input signals and option signals supplied to the gate driver are converted into packet-type differential signals and supplied, thereby providing signal lines arranged on the display panel. It has the effect of reducing the number of devices and reducing the bezel area.

100: display device
121: timing controller
122: data driver
123: gate driver
200: gate driver IC
101: receiver
102: memory

Claims (7)

A gate driver for generating a sensing signal and a scan signal to be supplied to a display panel, the gate driver comprising:
a receiver configured to receive a packet signal and a clock signal obtained by packetizing gate timing control signals into differential signals, and restore the gate timing control signals from the packet signal using a serial or serial-to-parallel converter;
a memory storing the gate timing control signals restored by the receiver and outputting the restored gate timing control signals in response to a start signal and the clock signal inputted from an external system;
a shift register receiving the gate timing control signals output from the memory; and
and an output unit for outputting a sensing signal and a scan signal generated by the shift register.
The method of claim 1 , wherein the packet signal comprises a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and a vertical output enable signal. Gate driver with (Vertical Output Enabel, VOE) and Vertical Start Pulse (VSP).
The gate driver of claim 1 , wherein the packet signal is supplied in an LVDS method.
a display panel having a display unit and a non-display unit;
a timing controller for packetizing gate timing control signals into differential signals to output a packet signal and a clock signal; and
a gate driver for generating a sensing signal and a scan signal supplied to the display panel;
The gate driver is
a receiver configured to receive the packet signal and the clock signal packetized as the differential signal from the timing controller, and restore the gate timing control signals from the packet signal using a serial or serial-to-parallel converter;
a memory storing the gate timing control signals restored by the receiver and outputting the restored gate timing control signals in response to a start signal and the clock signal inputted from an external system;
a shift register receiving the gate timing control signals output from the memory; and
and an output unit for outputting a sensing signal and a scan signal generated by the shift register.
5. The method of claim 4, wherein the packet signal comprises a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and a vertical output enable signal. A display including a (Vertical Output Enabel, VOE) and a Vertical Start Pulse (VSP).
The display device of claim 4 , wherein the packet signal is supplied in an LVDS method.
The display device of claim 4 , wherein two signal lines are disposed on the non-display portion of the display panel to supply the packet signal.

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