KR101777869B1 - Liquid crystal display device and drving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display and a driving method thereof. The liquid crystal display of the present invention includes: a liquid crystal display panel including a transistor formed for each pixel defined by intersection of data lines and gate lines and switching a data voltage supplied to the pixel electrode; A data driver for supplying a data voltage to the data lines; A gate driver including a plurality of gate drive ICs sequentially supplying a gate pulse synchronized with the data voltage to the gate lines; And a timing controller for controlling operation timings of the gate driver and the data driver, wherein each of the gate driver ICs receives a gate start pulse and a gate shift clock from the timing controller, A shift register sequentially shifting according to a gate shift clock; Logic gates for performing an AND operation between the output signal of the shift register and the gate shift clock; And a level shifter for shifting the swing width of the output voltage of the AND gates to a swing width capable of operating the transistor.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

The present invention relates to a liquid crystal display and a driving method thereof.

BACKGROUND ART [0002] Liquid crystal display devices are becoming increasingly widespread due to features such as light weight, thinness, and low power consumption driving. The liquid crystal display device is used as a portable computer such as a notebook PC, an office automation device, an audio / video device, and an indoor / outdoor advertisement display device. A liquid crystal display controls an electric field applied to liquid crystal cells to modulate light incident from a backlight unit to display an image.

The active matrix type liquid crystal display device includes a liquid crystal display panel including a TFT (Thin Film Transistor) formed for each pixel and switching a data voltage supplied to the pixel electrode, a data voltage supply line for supplying data voltages to the data lines D of the liquid crystal display panel A gate driving circuit for sequentially supplying gate pulses (or scan pulses) to the gate lines G of the liquid crystal display panel, and a timing controller for controlling the operation timing of the driving circuits, and the like .

The gate drive circuit supplies a gate start pulse (GST), a gate shift clock (GSC), a gate shift clock (GSC), and a gate signal from the timing controller in order to sequentially supply gate pulses to the gate lines G of the liquid crystal display panel. And an output enable signal (Gate Output Enable, GOE). The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP and the gate output enable signal GOE is a clock signal for shifting the gate- And is a signal for controlling the output timing of the driving circuit.

1 is a diagram showing signal lines from a timing controller to a gate drive IC in the prior art. Referring to FIG. 1, the gate drive circuit includes a plurality of gate drive ICs. The gate start pulse GSP, the gate shift clock GSC and the gate output enable signal GOE of the gate start pulse GSP, the gate shift clock GSC and the gate shift clock GSC_Lines, And the wiring GOE_Line of the gate output enable signal GOE from the timing controller 3 to the gate drive IC 1. [ Further, the gate drive IC 1 is connected to the voltage wirings of a power supply unit (not shown). A large number of wirings from the timing controller 3 and the power supply unit (not shown) mounted on the printed circuit board 2 are supplied to the gate drive IC 1 (not shown) through the bezel region B of the liquid crystal display panel, ). The bezel area B of the liquid crystal display panel becomes narrower due to the slimness of the display device, but it is difficult to reduce the bezel area B of the liquid crystal display panel.

The present invention provides a liquid crystal display device capable of reducing a bezel area of a liquid crystal display panel by eliminating a gate output enable signal (GOE) line and a driving method thereof.

The liquid crystal display of the present invention includes: a liquid crystal display panel including a transistor formed for each pixel defined by intersection of data lines and gate lines and switching a data voltage supplied to the pixel electrode; A data driver for supplying a data voltage to the data lines; A gate driver including a plurality of gate drive ICs sequentially supplying a gate pulse synchronized with the data voltage to the gate lines; And a timing controller for controlling operation timings of the gate driver and the data driver, wherein each of the gate driver ICs receives a gate start pulse and a gate shift clock from the timing controller, A shift register sequentially shifting according to a gate shift clock; Logic gates for performing an AND operation between the output signal of the shift register and the gate shift clock; And a level shifter for shifting the swing width of the output voltage of the AND gates to a swing width capable of operating the transistor.

A method of driving a liquid crystal display of the present invention includes: a liquid crystal display panel including a transistor which is formed for each pixel defined by intersection of data lines and gate lines and switches a data voltage supplied to the pixel electrode; A data driver for supplying a data voltage to the data lines; A gate driver including a plurality of gate drive ICs sequentially supplying a gate pulse synchronized with the data voltage to the gate lines; And a timing controller for controlling the operation timings of the gate driver and the data driver, the liquid crystal display comprising: a timing controller for receiving a gate start pulse and a gate shift clock from the timing controller, A first step of sequentially shifting according to the first step; A second step of ANDing the output signal of the first stage and the gate shift clock; And a third step of shifting the swing width of the output voltage of the second step to a swing width at which the transistor can operate.

The present invention sequentially supplies gate pulses to gate lines of a liquid crystal display panel without a gate output enable signal. As a result, the present invention can eliminate the GOE wiring in the bezel area of the liquid crystal display panel, thereby reducing the bezel area of the liquid crystal display panel.

1 is a diagram showing signal lines from a timing controller to a gate drive IC in the prior art.
2 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention.
3 is a circuit diagram showing the gate drive IC of FIG. 2 in detail.
4 is a waveform diagram showing an input / output waveform of the gate drive IC.
5 is a view showing signal lines from the timing controller to the gate drive IC in the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

2 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention. 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a gate driver 110, a data driver 120, a timing controller 130, a host system 140, .

The liquid crystal display panel 10 displays an image under the control of the timing controller 130. The liquid crystal display panel 10 includes a thin film transistor (hereinafter referred to as "TFT ") substrate and a color filter substrate. A liquid crystal layer is formed between the TFT substrate and the color filter substrate. On the TFT substrate, data lines D and gate lines G (or scan lines) are formed so as to intersect with each other on a lower glass substrate, and are defined by data lines D and gate lines G The liquid crystal cells are arranged in a matrix form in the cell regions. The TFT formed at the intersection of the data lines D and the gate line G applies the data voltage supplied via the data line D to the pixel electrode of the liquid crystal cell in response to the gate pulse from the gate line G . To this end, the gate electrode of the TFT is connected to the gate line G, and the source electrode thereof is connected to the data line D. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell and the storage capacitor. The storage capacitor maintains the data voltage transferred to the pixel electrode for a predetermined time until the next data voltage is received. A common voltage is supplied to the common electrode facing the pixel electrode.

The color filter substrate includes a black matrix and a color filter formed on the upper glass substrate. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode in the driving method.

An upper polarizer is attached to the upper glass substrate of the liquid crystal display panel 10, and a lower polarizer is attached to the lower glass substrate. The light transmission axis of the upper polarizer and the light transmission axis of the lower polarizer are orthogonal. An alignment film for setting a pre-tilt angle of the liquid crystal is formed on the upper glass substrate and the lower glass substrate. A spacer for maintaining a cell gap of the liquid crystal layer is formed between the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10. [ The liquid crystal mode of the liquid crystal display panel 10 may be realized in any liquid crystal mode as well as the TN mode, the VA mode, the IPS mode, and the FFS mode described above.

The backlight unit includes a light source, a light guide plate (or diffusion plate), and a plurality of optical sheets that are turned on in accordance with a driving current supplied from the backlight unit driving unit. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. The light sources of the backlight unit may include any one of a light source of HCFL (Cold Cathode Fluorescent Lamp), CCFL (Cold Cathode Fluorescent Lamp), EEFL (External Electrode Fluorescent Lamp), LED .

The backlight unit driving unit generates a driving current for lighting the light sources of the backlight unit. The backlight unit driving unit turns ON / OFF the driving current supplied to the light sources under the control of the timing controller 130. The timing controller 130 outputs the backlight control data in which the backlight luminance and the lighting timing adjusted in accordance with the global / local dimming signal (DIM) input from the host system 140, to the backlight unit driving unit in the SPI data format.

The data driver 120 includes a plurality of source driver integrated circuits (ICs). The source driver ICs convert the image data (RGB) input from the timing controller 130 into a positive / negative gamma compensation voltage to generate positive / negative analog data voltages. Positive / negative polarity analog data voltages output from the source drive ICs are supplied to the data lines of the liquid crystal display panel 10.

The gate driver 110 includes a plurality of gate driver ICs 111 each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, do. The gate driver 110 sequentially supplies a gate pulse synchronized with the data voltage to the gate lines G of the display panel 10 under the control of the timing controller.

The timing controller 130 controls the timing of the image data RGB output from the host system 140 and the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the clock signal CLK And outputs a gate driver control signal to the gate driver 110 and a data driver control signal to the data driver 120 based on the signals. The gate driver control signal includes a gate start pulse (GSP), a gate shift clock (GSC), and the like. The gate start pulse (GSP) controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP.

The data driver control signal includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) signal, a polarity control signal (POL) . The source start pulse SSP controls the data sampling start timing of the data driver 120. The source sampling clock is a clock signal that controls the sampling operation of the data driver 120 based on the rising or falling edge. The source start pulse SSP and the source sampling clock SSC may be omitted if the digital video data to be input to the data driver 120 is transmitted in accordance with the mini LVDS (Low Voltage Differential Signaling) interface standard. The polarity control signal POL inverts the polarity of the data voltage output from the data driver 120 to L (L is a natural number) horizontal period period. The source output enable signal SOE controls the output timing of the data driver 120.

The host system 140 supplies the image data RGB to the timing controller 130 through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. In addition, the host system 140 supplies the timing signals Vsync, Hsync, DE, and CLK to the timing controller 130.

3 is a circuit diagram showing the gate drive IC of FIG. 2 in detail. 3, each of the gate drive ICs 111 includes a shift register 301, a level shifter 303, and a plurality of AND gates (hereinafter referred to as " gate ") 301 connected between a shift register 301 and a level shifter 303 , "AND gate") 302.

The shift register 301 shifts the gate start pulse GSP sequentially in accordance with the gate shift clock GSC using a plurality of D flip-flops connected in a dependent manner. Each of the AND gates 302 logically multiplies the output signal of the shift register 301 and the gate shift clock GSC to generate an output.

The level shifter 303 shifts the output voltage swing width of the AND gate 302 to a swing width capable of operating the TFT formed in the TFT array of the liquid crystal display panel. The output signal of the level shifter 303 is sequentially supplied to the gate lines G. [

The shift register 301 may be formed directly on the lower glass substrate of the liquid crystal display panel 10 together with the TFT array in the GIP (Gate In Panel) process. In this case, the level shifter 303 is formed on the control board or the printed circuit board (PCB) together with the timing controller 130, and supplies the gate shift clock GSC, whose swing width is adjusted to be as large as the driving voltage of the TFT, (301).

4 is a waveform diagram showing an input / output waveform of the gate drive IC. The operation of the gate drive IC 111 will be described with reference to Figs. 3 and 4. Fig.

3 and 4, a gate start pulse GSP and a gate shift clock GSC are input to the shift register 301 of the gate drive IC 111. [ The gate start pulse (GSP) controls the timing of the first gate pulse. Only the first clock of the gate shift clock GSC overlaps with the gate start pulse GSP as shown in FIG. The output (SR_out (n)) of the nth (n is a natural number) shift register is increased to the rising point of the nth clock of the gate shift clock GSC and polled at the rising point of the (n + 1) th clock. For example, as shown in FIG. 4, the output (SR_out (1)) of the first shift register is increased to the rising timing of the first clock of the gate shift clock GSC and polled at the rising timing of the second clock. One period of the output (SR_out (n)) of the nth shift register is synchronized with one period of the gate shift clock GSC.

The gate drive IC 111 includes AND gates 302. Each of the AND gates 302 receives the output of the shift register. In addition, a gate shift clock GSC is input to each of the AND gates 302. The n < th > AND gate 302 ANDs the output (SR_out (n)) of the nth shift register and the gate shift clock GSC. For example, the first AND gate 302 performs an AND operation on the output (SR_out (1)) of the first shift register and the gate shift clock (GSC). The output of the nth AND gate 302 is synchronized with the nth clock of the gate shift clock GSC so that the nth gate pulse GPn output from the gate drive IC 111 is synchronized with the gate shift clock GSC).

The output of each of the AND gates 302 is input to the level shift 303 to shift the output voltage swing width to a swing width capable of operating the TFT formed in the TFT array of the liquid crystal display panel. The first to k-th (k is a natural number) gate pulses GP1 to GPk output from the level shifter 303 have a swing width of the gate high voltage VGH and the gate low voltage VGL. The gate high voltage VGH may be set between 20V and 30V, and the gate low voltage VGL may be set between -5V and 0V.

5 is a view showing signal lines from the timing controller to the gate drive IC in the present invention. Referring to FIG. 5, a timing controller 130 and a power supply unit (not shown) are mounted on a printed circuit board (PCB) 200. Each of the gate drive IC 111 and the source drive IC 121 may be mounted on a Tape Carrier Package (TCP) The tape carrier package (TCP) 210 is connected to the liquid crystal display panel 10 and the printed circuit board (PCB) 200 by a TAB (Tape Automated Bonding) method. Each of the gate drive IC 111 and the source drive IC 121 may be mounted on a base film connected to the liquid crystal display panel 10 and the printed circuit board (PCB) 200 by a chip on film (COF) have.

The gate start pulse GSP, the gate shift clock GSC and the gate output enable signal GOE are supplied to the wiring GSP_Line of the gate start pulse GSP and the wirings GSC_Lines of the gate shift clock GSC, To the gate drive IC 111 through the timing controller 130. [ The wiring GSP_Line of the gate start pulse GSP and the wirings GSC_Lines of the gate shift clock GSC are supplied from the timing controller 130 to the printed circuit board 200 and the tape carrier package TCP 210 (Or COF (Chip On Film)) and the bezel region B of the liquid crystal display panel 10. The gate driver IC 111 is connected to the liquid crystal display panel 10 through the bezel region B of the liquid crystal display panel 10. The power supply lines of the power supply unit (not shown) of the printed circuit board (PCB) 200 are connected to the printed circuit board (PCB) 200, the tape carrier package (TCP) 210 (or COF (Chip On Film) And the bezel region B of the liquid crystal display panel 10 to the gate drive IC 111. [

The liquid crystal display of the present invention sequentially supplies the gate pulses to the gate lines G of the liquid crystal display panel without the gate output enable signal GOE so that the line GOE_Line of the gate output enable signal GOE is required none. 5, only the wiring GSP_Line of the gate start pulse GSP and the wiring lines GSC_Lines of the gate shift clock GSC from the timing controller 130 are applied to the gate drive IC 111 ). As a result, the liquid crystal display of the present invention can eliminate the line GOE_Line of the gate output enable signal GOE shown in FIG. 1, thereby reducing the bezel area B. The bezel region B refers to a rim portion of the liquid crystal display panel 10, not an active region.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 110: gate driver
111: Gate drive IC 120: Data driver
130: timing controller 140: host system
200: printed circuit board 210: tape carrier package
301: Shift register 302: AND gate
303: Level shifter

Claims (6)

A liquid crystal display panel including a transistor which is formed for each pixel defined by intersection of data lines and gate lines and switches a data voltage supplied to the pixel electrodes;
A data driver for supplying a data voltage to the data lines;
A gate driver including a plurality of gate drive ICs sequentially supplying a gate pulse synchronized with the data voltage to the gate lines; And
And a timing controller for controlling an operation timing of the gate driver and the data driver,
Each of the gate drive ICs includes:
A shift register receiving a gate start pulse and a gate shift clock from the timing controller and sequentially shifting the gate start pulse according to the gate shift clock;
Logic gates for performing an AND operation between the output signal of the shift register and the gate shift clock; And
And a level shifter for shifting a swing width of the output voltage of the AND gates to a swing width at which the transistor can operate. The method according to claim 1,
And one cycle of the output signal of the shift register is synchronized with one cycle of the gate shift clock. The method according to claim 1,
And a first clock of the gate shift clock is superimposed on the gate start pulse. The method of claim 3,
The output signal of the n-th (n is a natural number) shift register is raised to the rising time of the n-th clock of the gate shift clock and polled at the rising time of the (n + 1) -th clock of the gate shift clock. Device. The method of claim 3,
And the n-th gate pulse is synchronized with the n-th clock of the gate shift clock. A liquid crystal display panel including a transistor which is formed for each pixel defined by intersection of data lines and gate lines and switches a data voltage supplied to the pixel electrodes; A data driver for supplying a data voltage to the data lines; A gate driver including a plurality of gate drive ICs sequentially supplying a gate pulse synchronized with the data voltage to the gate lines; And a timing controller for controlling an operation timing of the gate driver and the data driver, the liquid crystal display comprising:
A first step of receiving a gate start pulse and a gate shift clock from the timing controller and successively shifting the gate start pulse according to the gate shift clock;
A second step of ANDing the output signal of the first stage and the gate shift clock; And
And a third step of shifting a swing width of the output voltage of the second step by a swing width capable of operating the transistor.

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