KR101868606B1 - Shift register and display device including the same - Google Patents

Abstract

The present invention relates to a shift register and a display device including the shift register. A shift register according to an embodiment of the present invention includes a clock pulse modulation circuit for modulating a voltage of a falling edge of i (i is a natural number equal to or greater than 3) phase clocks sequentially delayed in phase to a voltage lower than a gate high voltage; And a plurality of stages for outputting a gate pulse having the same pulse as a clock modulated from the clock pulse modulation circuit input through a clock terminal in response to a start voltage or a carry signal inputted through a start terminal. In the gate pulse modulation circuit, the gate electrode is connected to the output line of the m-th (m is a natural number) stage, the source electrode is connected to the gate low voltage line, and the drain electrode is connected to the output line of the (m + A first TFT; And the gate electrode is connected to the output line of the (m + 2) th stage, the source electrode is connected to the gate low voltage line, and the drain electrode is connected to the output line of the (m + . The gate pulse modulation circuit adjusts the magnitude of the falling edge voltage of the gate pulse based on the voltage level applied to the gate low voltage line.

Description

[0001] SHIFT REGISTER AND DISPLAY DEVICE INCLUDING THE SAME [0002]

The present invention relates to a shift register and a display device including the shift register.

BACKGROUND ART [0002] Liquid crystal display devices are becoming increasingly widespread due to features such as light weight, thinness, and low power consumption driving. The liquid crystal display device is used as a portable computer such as a notebook PC, an office automation device, an audio / video device, and an indoor / outdoor advertisement display device. A liquid crystal display controls an electric field applied to liquid crystal cells to modulate light incident from a backlight unit to display an image.

The active matrix type liquid crystal display device includes a liquid crystal display panel including a TFT (Thin Film Transistor) formed for each pixel and switching a data voltage supplied to the pixel electrode, a data driving circuit for supplying a data voltage to the data lines of the liquid crystal display panel A gate driving circuit for sequentially supplying gate pulses (or scan pulses) GP to the gate lines of the liquid crystal display panel, and a timing controller for controlling the operation timing of the driving circuits.

In an active matrix type liquid crystal display device, the voltage charged in the liquid crystal cell is affected by a kickback voltage (or a feed-through voltage, DELTA Vp) caused by the parasitic capacitance of the TFT. The kickback voltage (Vp) is expressed by Equation (1).

Here, 'Clc' denotes the capacitance of the liquid crystal cell, 'Cst' denotes the capacitance of the storage capacitor, and 'Cgd' denotes the gate terminal of the TFT connected to the gate line and the drain terminal of the TFT connected to the pixel electrode of the liquid crystal cell 'VGH-VGL' is a difference voltage between the gate high voltage VGH and the gate low voltage VGL of the gate pulse GP as shown in FIG.

The voltage applied to the pixel electrode of the liquid crystal cell varies due to the kickback voltage Vp, and flicker, afterimage, color deviation, and the like can be seen in the display image. A gate pulse modulation method of modulating the gate high voltage VGH at the polling edge of the gate pulse GP is applied to reduce the kickback voltage Vp.

On the other hand, the gate drive circuit of the liquid crystal display device can be formed by mounting a gate drive integrated circuit on a PCB (Printed Circuit Board) and attaching the gate drive integrated circuit to a display panel by TAB (Tape Automated Bonding) And a gate drive IC in panel (GIP) method. In the case of forming the gate driving circuit by the GIP method, the liquid crystal display device can be made slimmer as compared with the case where the gate driving circuit is formed by the TAB method, so that the external appearance can be increased and the cost can be reduced. Can be directly designed by a display panel maker.

The present invention provides a shift register capable of reducing a kickback voltage and a display device including the gate driver circuit in a GIP scheme.

A shift register according to an embodiment of the present invention includes: a clock pulse modulation circuit for modulating a voltage of a falling edge of i (i is a natural number equal to or greater than 3) phase clocks sequentially delayed in phase to a voltage lower than a gate high voltage; And a plurality of stages for outputting a gate pulse having the same pulse as a clock modulated from the clock pulse modulation circuit input through a clock terminal in response to a start voltage or a carry signal inputted through a start terminal. In the gate pulse modulation circuit, the gate electrode is connected to the output line of the m-th (m is a natural number) stage, the source electrode is connected to the gate low voltage line, and the drain electrode is connected to the output line of the (m + A first TFT; And the gate electrode is connected to the output line of the (m + 2) th stage, the source electrode is connected to the gate low voltage line, and the drain electrode is connected to the output line of the (m + . The gate pulse modulation circuit adjusts the magnitude of the falling edge voltage of the gate pulse based on the voltage level applied to the gate low voltage line.

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A display device according to an embodiment of the present invention includes: a display panel having data lines and gate lines; A data driving circuit for converting input digital video data into analog data voltages and supplying the analog data voltages to the data lines; And a gate driving circuit for sequentially outputting a gate pulse synchronized with the data lines to the gate lines, wherein the gate driving circuit is connected to the output line of the m-th (m is a natural number) stage, A first TFT having a source electrode connected to a gate low voltage line and a drain electrode connected to an output line of the (m + 1) th stage; And the gate electrode is connected to the output line of the (m + 2) th stage, the source electrode is connected to the gate low voltage line, and the drain electrode is connected to the output line of the (m + . The gate drive circuit adjusts the magnitude of the falling edge voltage of the gate pulse based on the voltage level applied to the gate low voltage line.

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The present invention modulates the voltage of the falling edge of the clock input to the clock terminal of each of the stages using a clock pulse modulation circuit. As a result, since the present invention can reduce the difference voltage between the gate high voltage and the gate low voltage of the gate pulse, the kickback voltage can be reduced. The present invention also forms a clock pulse modulation circuit in a shift register rather than a printed circuit board. As a result, the present invention can design a shift register including a clock pulse modulation circuit by the GIP method, thereby reducing cost.

The present invention modulates the voltage of the falling edge of the gate pulse output from the output terminal of each of the stages using a gate pulse modulation circuit. As a result, since the present invention can reduce the difference voltage between the gate high voltage and the gate low voltage of the gate pulse, the kickback voltage can be reduced. In addition, the present invention forms a gate pulse modulation circuit in a shift register rather than a printed circuit board. As a result, the present invention can design a shift register including a gate pulse modulation circuit by the GIP method, thereby reducing cost.

1 is a view showing an example of a gate pulse output from a gate drive circuit;
2 is a block diagram schematically showing a display device according to an embodiment of the present invention;
3 is a block diagram showing a shift register according to a first embodiment of the present invention;
4 is a waveform diagram showing a clock pulse modulation signal according to the first embodiment of the present invention, clocks input to a shift register, clocks modulated from a clock pulse modulation circuit, and gate pulses output from a shift register.
Figs. 5A to 5C are simulation results showing a clock input to a shift register, a clock modulated by a clock pulse modulation circuit, and a gate pulse output from a k-th stage.
6 is a block diagram showing a shift register according to a second embodiment of the present invention;
7 is a waveform diagram showing clocks input to a shift register, outputs of respective stages, and gate pulses output from a gate pulse modulation circuit according to a second embodiment of the present invention;
8 is a simulation result showing a gate pulse output from a shift register;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

2 is a block diagram schematically showing a display device according to an embodiment of the present invention. Referring to FIG. 2, a display device according to an embodiment of the present invention includes a display panel 10, a data driving circuit, a gate driving circuit, and a timing controller 11.

A display device according to an embodiment of the present invention includes any display device that sequentially supplies gate pulses (or scan pulses) to gate lines to write digital video data to pixels by line sequential scanning. For example, a display device according to an embodiment of the present invention may include a liquid crystal display (LCD), an organic light emitting diode (OLED), a field emission display (FED) , And an electrophoresis display (EPD). While the present invention has been described with reference to the case where a display device is implemented by a liquid crystal display device in the following embodiments, it should be noted that the display device of the present invention is not limited to a liquid crystal display device. The liquid crystal display device can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device.

In the display panel 10, a liquid crystal layer is formed between two substrates. A TFT (Thin Film Transistor) formed at each intersection of the data lines, the gate lines crossing the data lines, the data lines and the gate lines is connected to the lower substrate of the display panel 10, A liquid crystal cell driven by an electric field between the electrodes, and a storage capacitor. On the upper substrate of the display panel 10, a color filter array including a black matrix and a color filter is formed. The liquid crystal display according to the exemplary embodiment of the present invention may be implemented in a liquid crystal mode such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode or FFS (Fringe Field Switching) mode. The common electrode may be formed on the upper substrate in a vertical electric field driving mode such as a TN mode and a VA mode, and may be formed on a lower substrate together with the pixel electrode in a horizontal electric field driving mode such as an IPS mode and an FFS mode. On the upper substrate and the lower substrate of the display panel 10, a polarizing plate whose optical axis is orthogonal is attached, and an alignment film for setting a pre-tilt angle of liquid crystal is formed at an interface with the liquid crystal layer.

The data drive circuit includes a plurality of source drive ICs 12. [ The source drive ICs 12 receive digital video data (DATA) from the timing controller 11. [ Each of the source drive ICs 12 converts the digital video data DATA into a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, To the data lines of the display panel 10. The source drive ICs 12 may be connected to the data lines of the display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate drive circuit includes a level shifter 13 and a shift register 14. The level shifter 13 level shifts the TTL (Logic-Transistor-Logic) logic level voltage of the clocks CLKs input from the timing controller 11 to the gate high voltage VGH and the gate low voltage VGL. The level-shifted clocks (CLKs) are input to the shift register (14). The shift register 14 is connected to the gate lines of the display panel 10 to sequentially output gate pulses to the gate lines. The shift register 14 is formed directly on the lower substrate of the display panel 10 by a GIP (Gate Drive-IC In Panel) method. In the GIP scheme, the level shifter 13 is mounted on a printed circuit board 15.

The timing controller 11 receives digital video data RGB from an external host system through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 11 transmits the digital video data (DATA) input from the host system to the source drive ICs 12. The timing controller 11 receives a timing signal such as a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, and a main clock from the host system through the LVDS or TMDS interface receiving circuit. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host system. The timing control signals include a gate timing control signal for controlling the operation timing of the gate drive circuit, a data timing control signal DCS for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes clocks (CLKs) that are sequentially generated on the start voltage and i (i is a natural number of 3 or more). The start voltage is input to the shift register 14 to control the shift start timing of the shift register 14. The clocks CLKs are input to the level shifter 13 and level-shifted, then input to the shift register 14, and used as a clock signal for shifting the start voltage.

The data timing control signal DCS includes a source start pulse, a source sampling clock, a polarity control signal, and a source output enable signal. The source start pulse controls the shift start timing of the source drive ICs 12. [ The source sampling clock is a clock signal that controls the sampling timing of data within the source drive ICs 12 based on the rising or falling edge. The polarity control signals control the polarity of the data voltages output from the source drive ICs 12. [ If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

3 is a block diagram showing a shift register according to a first embodiment of the present invention. Referring to FIG. 3, the shift register 14 according to the first embodiment of the present invention includes a plurality of stages ST (1) to ST (n) And a clock pulse modulation circuit (CPM). In Fig. 3, convenience of explanation is exemplified only from k (1 <k <n, k is a natural number of 2 or more) to (k + 3) stages ST (k) to ST (k + 3).

In the following description, the term "front stage" means that the stage is located above the reference stage. For example, on the basis of the k-th stage ST (k), the front stage indicates any one of the first stage ST (1) to the (k-1) th stage ST (k-1). Quot; rear stage "refers to a stage located at the bottom of the reference stage. For example, on the basis of the k-th stage ST (k), the trailing stage indicates any one of the (k + 1) th stages ST (k + 1) to k (n).

A start voltage is applied to a start voltage line (not shown), a clock pulse modulation signal Vcpm is applied to a clock pulse modulation signal supply line Vcpm Line, a gate low voltage VGL Is applied. The first clock CL1 is applied to the first clock line CL1, the second clock CLK2 is applied to the second clock line CL2, and the third clock CL2 is applied to the third clock line CL3. And a fourth clock CLK4 is applied to the fourth clock line CL4.

Each of the stages ST (1) to ST (n) has a start terminal START, a clock terminal CLK, a reset terminal RESET, and an output terminal OUT. Each of the stages ST (1) to ST (n) is pulled up in response to a start voltage or a preceding carry signal input via a start terminal START, Lt; / RTI &gt; Each of the stages ST (1) to ST (n) outputs a gate pulse having the same pulse as the clock inputted through the clock terminal CLK through the output terminal OUT.

A start voltage or a carry signal of the previous stage is input to the start terminal START of each of the stages ST (1) to ST (n). For example, as shown in Fig. 3, the output of the k-th stage ST (k), which is the carry signal of the front stage, is input to the start terminal (START) of the (k + 2) th stage ST (k + 2). The carry signal of the subsequent stage is inputted to the reset terminal RESET of each of the stages ST (1) to ST (n). For example, the output of the (k + 2) -th stage ST (k + 2), which is the carry signal of the subsequent stage, is input to the reset terminal RESET of the k-th stage ST (k) as shown in Fig.

Any clock modulated by the clock pulse modulation circuit CPM among the i-phase clocks whose phases are sequentially delayed is input to the clock terminal CLK of each of the stages ST (1) to ST (n) . In order to secure a sufficient charge time at a high-speed operation of 120 Hz or more, the i-phase clocks are desirably implemented in four or more phases. For example, the i-phase clocks may be implemented with four-phase clocks CLK1, CLK2, CLK3, and CLK4 as shown in FIG. In the first embodiment of the present invention, the i-phase clocks are implemented as four-phase clocks (CLK1, CLK2, CLK3, CLK4) for convenience of description. However, the present invention is not limited thereto. The four-phase clocks CLK1, CLK2, CLK3, and CLK4 may be sequentially delayed in phase for a predetermined first period as shown in FIG. The predetermined first period may be suitably implemented within approximately one horizontal period to two horizontal periods. One horizontal period means one line scanning time at which data is written to pixels of one line of the display panel. Further, the four-phase clocks CLK1, CLK2, CLK3, and CLK4 are level-shifted from the level shifter 13 to the TTL logic level, and thus swing between the gate high voltage VGH and the gate low voltage VGL. The four-phase clocks (CLK1, CLK2, CLK3, CLK4) are pulsed with the gate high voltage (VGH). The gate low voltage VGL may be set to approximately -7V to -15V and the gate high voltage VGH may be set to approximately 15V to 30V. The jth (j is a natural number) clock CLKj and the (j + 1) th clock CLKj + 1 are overlapped for a predetermined second period as shown in FIG. The predetermined second period may be implemented as 1/4 to 1/3 of the pulse width of the j-th clock CLKj.

Each of the stages ST (1) to ST (n) has one output terminal OUT. The outputs ST (1) _out to ST (n) _out of the stages ST (1) to ST (n) are applied to the gate lines of the display panel 10 by gate pulses GP (1) to GP n), and is input as a carry signal to the start terminal (START) of the subsequent stage. Since the stages ST (1) to ST (n) are connected in a dependent manner, only when the start voltage is supplied to the first stage ST (1) (ST (n)).

The clock pulse modulation circuit CPM modulates the gate high voltage VGH at the polling edge of each of the i phase clocks and then outputs the modulated clock to the clock terminal of each of the stages ST (1) to ST (n) Output. The clock pulse modulation circuit CPM includes a first TFT T1 and a second TFT T2. The first TFT T1 connects the jth clock line CLj to the gate low voltage line VGL Line in response to the (j + 1) th clock CLKj + 1. The gate electrode of the first TFT T1 is connected to the source electrode of the second TFT T2, the source electrode thereof is connected to the gate low voltage line VGL Line and the drain electrode thereof is connected to the jth clock line CLj do. The second TFT T2 supplies the (j + 1) th clock (CLKj + 1) to the gate electrode of the first TFT (T1) in response to the clock pulse modulation signal (Vcpm). The gate electrode of the second TFT T2 is connected to the clock pulse modulation signal supply line Vcpm Line, the source electrode thereof is connected to the gate electrode of the first TFT T1, and the drain electrode thereof is connected to the (j + 1) CLj + 1.

4 is a waveform diagram showing a clock pulse modulation signal, clocks input to a shift register, clocks modulated from a clock pulse modulation circuit, and gate pulses output from a shift register. 4 shows the relationship between the clock pulse modulation signal Vcpm, the four-phase clocks CLK1, CLK2, CLK3 and CLK4, the clocks MCLK1, MCLK2, MCLK3 and MCLK4 modulated from the clock pulse modulation circuit CPM, (K), GP (k), and GP (k) output from the (k + 1) th to (k + 3) th stages ST (k), ST 1), GP (k + 2) and GP (k + 3). 4 shows a first rising period t1, a first polling period t2, and a second polling period t3. The first rising period t1 is a period in which the pulse of the j-th clock CLKj is generated but the pulse of the (j + 1) -th clock CLKj + 1 is not generated. The first polling period t2 is a period during which the pulse of the j-th clock CLKj and the pulse of the j + 1-th clock CLKj + 1 are generated, +1) are overlapped with each other. The second polling period t3 is a period during which no pulse of the j-th clock CLKj is generated.

Hereinafter, the operation of the shift register 14 according to the first embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4. FIG.

The first clock CLK1 of the clock pulse modulation circuit CPM is first referenced with reference to the clock pulse modulation signal Vcpm, the first clock CLK1, the second clock CLK2 and the modulated first clock MCLK1, Will be described in detail. The clock pulse modulation signal Vcpm may be set to a DC voltage capable of turning on the first TFT T1 in consideration of the threshold voltage of the first TFT T1. For example, the clock pulse modulation signal (Vcpm) may be set to the gate high voltage (VGH) as shown in FIG. 4, or a voltage capable of turning on the first TFT (T1) Lt; / RTI &gt;

During the first rising period t1, the clock pulse modulation signal Vcpm is generated at the gate high voltage VGH, the first clock CLK1 is generated at the gate high voltage VGH, and the second clock CLK2 is generated at the gate high voltage VGH. Lt; / RTI &gt; occurs at the gate-low voltage (VGL). The second TFT T2 is turned on by the clock pulse modulation signal Vcpm of the gate high voltage VGH while the first TFT T1 is turned on by the second clock CLK2 of the gate low voltage VGL Turn off. Therefore, the modulated first clock MCLK1 output from the clock pulse modulation circuit CPM during the first rising period t1 is output as it is to the gate high voltage VGH.

The clock pulse modulation signal Vcpm is generated at the gate high voltage VGH during the first polling period t2 and the first clock CLK1 is generated at the gate high voltage VGH and the second clock CLK2 is generated at the gate high voltage VGH, Gate high voltage (VGH). The second TFT T2 is turned on by the clock pulse modulation signal Vcpm of the gate high voltage VGH and the first TFT T1 is turned on by the second clock CLK2 of the gate high voltage VGH Turn on. The first clock CLK1 is connected to the gate high voltage VGH because the first clock line CL1 and the gate low voltage line VGL Line are connected due to the turn-on of the first and second TFTs T1 and T2, And falls to a voltage level between the gate low voltage VGL and the gate high voltage VGH. Thus, the modulated first clock MCLK1 output from the clock pulse modulation circuit CPM during the first polling period t2 falls to a voltage lower than the gate high voltage VGH at the falling edge.

During the second polling period t3 the clock pulse modulation signal Vcpm is generated at the gate high voltage VGH and the first clock CLK1 is generated at the gate low voltage VGL and the second clock CLK2 is at the Gate high voltage (VGH). The second TFT T2 is turned on by the clock pulse modulation signal Vcpm of the gate high voltage VGH and the first TFT T1 is turned on by the second clock CLK2 of the gate high voltage VGH Turn on. However, since the first clock CLK1 falls to the gate-low voltage VGL irrespective of the turn-on of the first and second TFTs T1 and T2, the clock pulse modulation circuit The modulated first clock MCLK1 output from the CPM is lowered to the gate low voltage VGL.

On the other hand, how low the voltage of the polling edge of the j-th clock CLKj is modulated depends on how low the voltage is applied to the gate low voltage line VGL line. Although the first embodiment of the present invention has been described mainly on the low modulation of the voltage at the falling edge of the j-th clock CLKj using the gate low voltage line VGL for supplying the gate low voltage VGL, It should be noted. That is, in the first embodiment of the present invention, the voltage of the polling edge of the j-th clock CLKj can be modulated with a voltage line that supplies a predetermined voltage lower than the gate high voltage VGH.

As a result, the clock pulse modulation circuit CPM changes the voltage of the falling edge of the j-th clock CLKj, which is the overlapping of the j-th clock CLKj and the (j + 1) -th clock CLKj + 1, Modulate with voltage. That is, the j-th clock (MCLKj) modulated from the clock pulse modulation circuit (CPM) is substantially equal to the j-th clock (CLKj) input to the shift register (14) in terms of pulse width and phase delay. However, the voltage of the falling edge of the j-th clock CLKj, in which the j-th clock CLKj and the (j + 1) -th clock CLKj + 1 overlap, is modulated to a voltage lower than the gate high voltage VGH.

Second, each of the stages ST (1) to ST (n) outputs a gate pulse having the same pulse as the clock input to the clock terminal CLK through the output terminal OUT. Since the clocks modulated from the clock pulse modulation circuit CPM are input to the clock terminals CLK of the stages ST (1) to ST (n), the stages ST (1) to ST (n) The voltage of the falling edge of the gate pulse output through the output terminal OUT of the gate high voltage VGH is lower than the gate high voltage VGH.

5A, the voltage of the falling edge of the clock input to the clock terminal CLK of each of the stages ST (1) to ST (n) is supplied to the clock pulse modulation circuit CPM As shown in FIG. 5B, to be lower than the gate high voltage VGH. As a result, the first embodiment of the present invention can reduce the difference voltage between the gate high voltage VGH and the gate low voltage VGL of the gate pulse GP in Equation (1) as shown in FIG. 5C. As a result, the first embodiment of the present invention can reduce the kickback voltage.

In addition, the first embodiment of the present invention forms a clock pulse modulation circuit (CPM) in the shift register 14 rather than a printed circuit board. As a result, the present invention can design the shift register 14 including the clock pulse modulation circuit (CPM) by the GIP method, thereby reducing the cost.

6 is a block diagram illustrating a shift register according to a second embodiment of the present invention. Referring to FIG. 6, the shift register 14 according to the second embodiment of the present invention includes a plurality of stages ST (1) to ST (n), n being the number of stages, And a gate pulse modulation circuit (GPM). In FIG. 6, only the k-th (k <1) and the (k + 3) stages ST (k) to ST (k + 3) are illustrated.

The stages ST (1) to ST (n) of the shift register 14 according to the second embodiment of the present invention are the same as those of the shift register 14 according to the first embodiment of the present invention Is substantially the same as the stages ST (1) to ST (n). Therefore, the detailed description of the stages ST (1) to ST (n) of the shift register 14 according to the second embodiment of the present invention will be omitted.

However, in the shift register 14 according to the second embodiment of the present invention, a clock pulse modulation signal supply line (Vcpm Line) is not formed and each of the stages ST (1) to ST (n) (I is a natural number of 4 or more) clocks sequentially delayed in phase through the clock signal CLK.

The gate pulse modulation circuit GPM modulates the gate high voltage VGH at the falling edge of the gate pulse output from each of the stages ST (1) to ST (n), and then outputs the modulated gate pulse to the display panel 10). The gate pulse modulation circuit GPM includes a first TFT T1 and a second TFT T2. The first TFT T1 is connected to the output line of the (m + 1) th stage ST (m + 1) in response to the output ST (m) _out of the m (m is a natural number) stage ST Connect the gate low voltage line (VGL Line). The gate electrode of the first TFT T1 is connected to the output line of the mth stage m (m is a natural number), the source electrode thereof is connected to the gate low voltage line VGL Line, is connected to the output line of the (m + 1) th stage ST (m + 1). The second TFT T2 is turned on in response to the output ST (m + 2) _out of the (m + 2) th stage ST (m + And a gate low voltage line (VGL Line). The gate electrode of the second TFT T2 is connected to the output line of the (m + 2) th stage ST (m + 2), the source electrode thereof is connected to the gate low voltage line VGL Line, And is connected to the output line of the +1 stage ST (m + 1).

7 is a waveform diagram showing clocks input to the shift register, outputs of respective stages, and gate pulses output from the gate pulse modulation circuit according to the second embodiment of the present invention. (K + 3) -th stage ST k + 1, ST k + 1, ST k + 2, ST k + (K + 3) _out, ST (k + 3) _out) and the gate pulse modulation circuit GPM output from the respective outputs ST (k) _out, ST Modulated gate pulses GP (k), GP (k + 1), GP (k + 2), and GP (k + 3) are shown. 7 shows a first rising period t1, a second rising period t2, a first polling period t3, and a second polling period t4. The first rising period t1 is a period in which the gate pulse output from the m-th stage ST (m) and the gate pulse output from the (m + 1) th stage ST (m + 1) overlap. The second rising period t2 is a period during which the gate pulse output from the m-th stage ST (m), the gate pulse output from the (m + 1) (m + 2)) are not overlapped with each other. The first polling period t3 is a period in which the gate pulse output from the (m + 1) th stage ST (m + 1) and the gate pulse output from the (m + 2) th stage ST . The second polling period t4 is a period during which the gate pulse is polled from the (m + 1) th stage ST (m + 1).

Hereinafter, the operation of the shift register 14 according to the second embodiment of the present invention will be described in detail with reference to FIGS. 6 and 7. FIG.

First, each of the stages ST (1) to ST (n) outputs a gate pulse having the same pulse as the clock input to the clock terminal CLK through the output terminal OUT. CLK1, CLK2, CLK3, and CLK4 from the clock lines CL1, CL2, CL3, and CL4 to the clock terminals CLK of the stages ST (1) to ST . Each of the stages ST (1) to ST (n) outputs a gate pulse having the same pulse as the input clock through the output terminal OUT.

Second, the output (ST (k + 1) _out) of the kth stage ST (k) (ST (k) _out), the output of the (k + 1) th stage ST 1 stage (ST (k + 1)) of the gate pulse modulation circuit GPM with reference to the output (ST (k + 2) _out) of the (k + 2) ((ST (k + 1) _out) modulation is described in detail.

The output (ST (k) _out) of the k-th stage ST (k) is generated at the gate high voltage VGH during the first rising period t1, (ST (k + 1) _out) of the (k + 2) th stage ST (k + 2) is generated at the gate high voltage VGH, The first TFT T1 is turned on by the output ST (k) _out of the k-th stage ST (k) of the gate high voltage VGH, The second TFT T2 is turned off by the output ST (k + 2) _out of the (k + 2) th stage of the gate low voltage VGL. 1 stage ST (k + 1) is connected to the gate low voltage line (VGL Line) due to the turn-on of the (k + 1) 1) of the (k + 1) -th stage ST (k + 1) is discharged to the gate low voltage VGL, Output from the pulse modulation circuit GPM The (k + 1) -th gate pulse GP (k + 1) output from the gate pulse modulation circuit GPM during the first rising period t1 does not rise to the gate high voltage VGH. The gate pulse GP (k + 1) has a voltage level between the gate low voltage VGL and the gate high voltage VGH.

The output (ST (k) _out) of the k-th stage ST (k) is generated as the gate-low voltage VGL during the second rising period t2, (ST (k + 1) _out) of the (k + 2) th stage ST (k + 2) is generated at the gate high voltage VGH, The first TFT T1 is turned off by the output ST (k) _out of the k-th stage ST (k) of the gate low voltage VGL, The second TFT T2 is turned off by the output ST (k + 2) _out of the (k + 2) th stage of the gate low voltage VGL. The output line of the (k + 1) th stage ST (k + 1) is not connected to the gate low voltage line (VGL Line) due to the turn-off of the two TFTs T1 and T2. the (k + 1) -th gate pulse GP (k + 1) output from the gate pulse modulation circuit GPM during the period t2 has the voltage level of the gate high voltage VGH.

The output (ST (k) _out) of the k-th stage ST (k) is generated as the gate-low voltage VGL during the first polling period t3, (ST (k + 1) _out) of the (k + 2) th stage ST (k + 2) is generated at the gate high voltage VGH, Gate high voltage VGH. The first TFT T1 is turned off by the output ST (k) _out of the k-th stage ST (k) of the gate low voltage VGL, The second TFT T2 is turned on by the output (ST (k + 2) _out) of the (k + 2) th stage of the gate high voltage VGH. 1 stage ST (k + 1) is connected to the gate low voltage line (VGL Line) due to the turn-on of the (k + 1) 1) of the (k + 1) -th stage ST (k + 1) is discharged to the gate low voltage VGL, The output from the pulse modulation circuit (GPM) The (k + 1) -th gate pulse GP (k + 1) output from the gate pulse modulation circuit GPM during the first polling period t3 does not rise to the gate high voltage VGH. The gate pulse GP (k + 1) has a voltage level between the gate low voltage VGL and the gate high voltage VGH.

The output (ST (k) _out) of the k-th stage ST (k) is generated as the gate-low voltage VGL during the second polling period t4, (ST (k + 1) _out) of the (k + 2) th stage ST (k + 2) is generated as the gate low voltage VGL, Gate high voltage VGH or gate low voltage VGL. The first TFT T1 is connected to the output (ST (k) _out) of the kth stage ST (k) of the gate low voltage VGH, And the second TFT T2 is turned off by the output ST (k + 2) _out of the (k + 2) -th stage ST (k + 2) of the gate high voltage VGH. The output of the (k + 1) th stage ST (k + 1) is generated at the gate low voltage VGL regardless of the turn-on of the second TFT T2, 1) th gate pulse GP (k + 1) output from the gate pulse modulation circuit GPM during the period t3 has a voltage level of the gate low voltage VGL.

On the other hand, how low the voltage of the poling edge of the m-th gate pulse GPm is modulated depends on how low the voltage is applied to the gate low voltage line VGL line. Although the second embodiment of the present invention has been described mainly on the low modulation of the voltage of the polling edge of the m-th gate pulse GPm using the gate low voltage line VGL for supplying the gate low voltage VGL, It should be noted that it is not limited. That is, in the second embodiment of the present invention, the voltage of the poling edge of the m-th gate pulse GPm can be modulated with a voltage line that supplies a predetermined voltage lower than the gate high voltage VGH.

As a result, in the second embodiment of the present invention, the voltage of the falling edge of the gate pulse outputted from the output terminal of each of the stages ST (1) to ST (n) The gate-high voltage VGH and the gate-low voltage VGL of the gate pulse GP in the equation (1) can be reduced. As a result, the second embodiment of the present invention can reduce the kickback voltage.

Further, the second embodiment of the present invention forms a gate pulse modulation circuit (GPM) in the shift register 14 rather than the printed circuit board. As a result, the present invention can design the shift register 14 including the gate pulse modulation circuit (GPM) by the GIP method, thereby reducing the cost.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source drive IC 13: Level shifter
14: shift register 15: printed circuit board

Claims (12)

delete delete delete delete delete A gate pulse having the same pulse as any one of i (i is a natural number equal to or greater than 3) phase clocks sequentially input through a clock terminal in response to a start voltage or a carry signal inputted through a start terminal is output A plurality of stages; And
And a gate pulse modulation circuit for modulating the voltage of the falling edge of the gate pulse to a voltage lower than the gate high voltage,
Wherein the gate pulse modulation circuit comprises:
A first TFT having a gate electrode connected to an output line of an mth (m is a natural number) stage, a source electrode connected to a gate low voltage line, and a drain electrode connected to an output line of the (m + 1) th stage; And the gate electrode is connected to the output line of the (m + 2) th stage, the source electrode is connected to the gate low voltage line, and the drain electrode is connected to the output line of the (m +
And adjusts the magnitude of the falling edge voltage of the gate pulse based on a voltage level applied to the gate low voltage line. delete delete delete The method according to claim 6,
The gate pulse includes
During the first rising period, to a voltage lower than the gate high voltage at the gate low voltage, to the gate high voltage during the second rising period, to a voltage lower than the gate high voltage during the first polling period, 2 &lt; / RTI &gt; polling period. delete A display panel on which data lines and gate lines are formed;
A data driving circuit for converting input digital video data into analog data voltages and supplying the analog data voltages to the data lines; And
And a gate driving circuit for sequentially outputting gate pulses synchronized with the data lines to the gate lines,
The gate drive circuit includes:
A first TFT having a gate electrode connected to an output line of an mth (m is a natural number) stage, a source electrode connected to a gate low voltage line, and a drain electrode connected to an output line of the (m + 1) th stage; And the gate electrode is connected to the output line of the (m + 2) th stage, the source electrode is connected to the gate low voltage line, and the drain electrode is connected to the output line of the (m +
And adjusts a magnitude of a falling edge voltage of the gate pulse based on a voltage level applied to the gate low voltage line.

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