KR102081137B1 - Organic light emtting diode display device including gate pulse moduration unit and dirving method thereof - Google Patents

Abstract

The present invention discloses an organic light emitting display device. More particularly, the present invention relates to an organic light emitting display device and a method of driving the same, including a gate driver which improves a problem of deterioration in image quality due to a luminance deviation caused by an RC delay on a display panel.
According to an exemplary embodiment of the present invention, the control signal applied to the gate driver is fed back to determine a signal delay degree for each position of the driving IC, and the gate pulse modulation signal is adjusted to minimize the gate electrode charge variation of the driving thin film transistor, thereby displaying the display. There is an effect that can improve the driving reliability and image quality degradation problem of the device.

Description

FIELD OF THE INVENTION An organic light emitting display device including a gate modulator and a driving method thereof.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display device, and more particularly, to an organic light emitting display device and a method of driving the organic light emitting display device including a gate driver which improves a problem of deterioration in image quality due to a luminance deviation caused by an RC delay on a display panel.

The flat panel display device proposed to replace the existing cathode ray tube display device is a liquid crystal display, a field emission display, a plasma display device. (Plasma Display Panel) and Organic Light-Emitting Diode Display (OLED Display).

1 is a view showing an outline structure of a conventional flat panel display.

Referring to FIG. 1, in the conventional flat panel display, a plurality of gate lines GL and data lines DL are formed to cross each other, and a plurality of pixels PX are defined at the intersections thereof. The gate line GL is connected to the gate electrode of the switching element included in the pixel to control the conduction of the switching element, and the data line DL supplies a data signal according to the gray level of each pixel PX to display an image. do.

In the flat panel display having such a structure, a signal applied to each pixel PX is influenced by a kickback voltage ΔVp due to the parasitic capacitance of the thin film transistor included in the pixel PX. Such kickback voltage is a cause of flicker, afterimage, and color deviation in the display image.

In order to minimize the image degradation problem caused by the kickback voltage, a gate pulse modulation (GPM) method for modulating the gate high voltage VGH at the polling edge of the scan signal has been proposed. According to the gate pulse modulation method, the output of the gate high voltage VGH is lowered to a predetermined level, thereby lowering the voltage in two stages, thereby minimizing the kickback voltage by preventing a sudden voltage change.

However, unlike a liquid crystal display device in which one thin film transistor is provided in one pixel PX with a voltage driving method, a current driving type organic light emitting display device serves as a switching element and a driving element in one pixel PX. Since two or more thin film transistors are provided, the level of the voltage charged to the gate electrode of the driving device through the switching device is changed even though the input waveform of the scan signal is the same. In addition, the charge variation occurs in the gate wiring GL according to the RC delay due to the resistance of the wiring itself and the parasitic capacitance.

In particular, the scan signal is generated by the gate driver including a plurality of driving ICs connected in parallel and sequentially output through the gate line GL, so that the signal varies according to the position of the driving IC.

2 is a view comparing signal waveforms with and without signal delay in a conventional organic light emitting display device.

Referring to FIG. 2, when the signal delay does not occur in the conventional organic light emitting display device (a) and the gate driving signal in the case where (b) occurs, the middle voltage VGM at the gate high voltage VGH is compared. And the width of the section which fluctuates to the low voltage VGL is delayed, and eventually the time to reach the low voltage VGL is delayed. Since the switching transistor is turned on until the low voltage VGL is reached, the voltage charged to the gate electrode of the final driving TFT is therefore lower than that in the case where a signal delay occurs (a) or not (b). The voltage level becomes high (V3 < V3 '), and eventually a predetermined voltage difference g occurs.

Therefore, it is difficult to solve the problem of deterioration in image quality due to signal delay only with the conventional gate pulse modulation method.

This causes a reduction in driving reliability and image quality of the flat panel display.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to improve a signal deviation according to a position of a gate driving IC of an organic light emitting display device having a plurality of thin film transistors in a pixel, particularly a flat panel display. Therefore, the problem of driving reliability and image quality deterioration of a display device is improved.

An organic light emitting display device according to an embodiment of the present invention includes a display panel in which a plurality of gate lines and data lines are cross-formed and pixels are defined at intersections thereof; A gate driver connected to the gate line to sequentially output a scan signal; A data driver connected to the data line to output a data signal; A timing controller configured to control the gate driver and the data driver through a control signal; And a gate modulator configured to determine a signal delay between the gate lines using a control signal applied to the gate driver, and adjust a gate pulse modulation signal output to the timing controller according to a determination result and output the signal to the timing controller. do.

A method of driving an organic light emitting display device according to an embodiment of the present invention includes generating a gate control signal in a timing controller and outputting the gate control signal to a gate driver; Determining the signal delay between the gate wirings using any one of the gate control signal output from the gate modulator to the gate driver and the signal output from the gate driver, and adjusts the gate pulse modulation signal according to the determination result to the timing controller. Outputting.

The organic light emitting display device according to an exemplary embodiment of the present invention receives a control signal applied to a gate driver to determine a signal delay degree for each position of a driving IC, and adjusts a gate pulse modulation signal to cause variation of gate electrode charge of a driving thin film transistor. By minimizing the above, driving reliability and image quality deterioration problems of the display device can be improved.

1 is a view showing an outline structure of a conventional flat panel display.
2 is a view comparing signal waveforms with and without signal delay in a conventional organic light emitting display device.
3A illustrates a structure of an organic light emitting display device including a gate modulator according to an exemplary embodiment of the present invention.
3B is a diagram illustrating an example of an equivalent circuit for one pixel of the organic light emitting display device of FIG. 3A.
3C is a diagram illustrating an example of a gate driver included in the organic light emitting display device of the present invention.
4 is a diagram illustrating a structure of a timing controller and a gate modulation according to an embodiment of the present invention.
5A and 5B are diagrams illustrating signal waveforms of a general gate pulse modulation signal GPM and signal delays inside a display panel. 6 is a diagram illustrating a method of driving an organic light emitting display device including a gate modulator according to an exemplary embodiment of the present invention.
7 is a view illustrating signal waveforms when the organic light emitting display device of FIG. 6 is driven.
FIG. 8 is a view comparing signal waveforms according to a delay of driving an organic light emitting display device according to an exemplary embodiment of the present invention.
FIG. 9 is a view illustrating signal waveforms when driven by a method of driving an organic light emitting display device including a gate modulator according to another exemplary embodiment of the present invention.

Hereinafter, an organic light emitting display device including a gate modulator and a driving method thereof will be described with reference to the accompanying drawings.

3A illustrates a structure of an organic light emitting display device including a gate modulator according to an exemplary embodiment of the present invention, and FIG. 3B illustrates an example of an equivalent circuit for one pixel of the organic light emitting display device of FIG. 3A. Drawing. 3C is a diagram illustrating an example of a gate driver included in the organic light emitting display device of the present invention.

3A to 3C, an organic light emitting display device according to an exemplary embodiment of the present invention includes a display panel in which a plurality of gate lines GL and data lines DL are formed to cross each other, and pixels PX are defined at intersections thereof. 100, a gate driver 110 connected to the gate line GL to sequentially output a scan signal Vscan, and a data driver connected to the data line DL to output a data signal Vdata ( 120, any one of a timing controller 130 controlling the gate driver 110 and the data driver 120 through control signals GCS and DCS, and a control signal applied to the gate driver 110. Determining the signal delay degree between the gate wiring (GL) by using, and the gate to adjust the gate pulse modulation signal (GPM) output to the gate driver 120 according to the determination result and outputs to the timing controller 130 Modulator 150 is included.

In the display panel 100, a plurality of gate lines GL and data lines DL are formed on the organic substrate or the plastic substrate so as to intersect with each other, and the gate lines GL and the data lines DL cross each other. Pixels PX that display gradations corresponding to red, green, and blue are defined. In addition, each pixel PX includes a sensing wiring SL and a reference voltage for external compensation or internal compensation of the threshold voltage Vth and electron mobility (μ) of the driving thin film transistor provided in the pixel PX. It is connected to a wiring (not shown). Although not shown, various wirings for supplying the power voltage ELVDD and the ground voltage ELVSS may be further formed in the display panel 100.

The gate line GL is formed on the outside of the display panel 100 and connected to the scan driver 120 that outputs the scan signal Vscan. The data line DL outputs the data signal. Connected with

In addition, the sensing wiring SL formed on the display panel 100 is connected to the sensing driver 140 that sinks a predetermined current into the pixel PX. The sensing driver 140 sinks a current flowing in the pixel PX to determine a threshold voltage Vth variation value of the driving thin film transistor of the pixel PX to compensate for the data signal Vdata. It may further include (not shown).

In addition, although not shown, the organic light emitting display device is connected to a power supply unit (not shown) for supplying not only a power supply voltage ELVDD but also a voltage for driving a display device such as a ground voltage ELVSS. The driving voltages are supplied to each pixel PX through a power supply voltage and a ground voltage wiring (not shown) formed in the display panel 100.

The pixels PX include at least one organic light emitting diode EL, a capacitor CAP, a switching thin film transistor SWT, a driving thin film transistor DRT, and a sensing thin film transistor SST. The organic light emitting diode EL may include a first electrode (hole injection electrode), an organic compound layer, and a second electrode (electron injection electrode).

Referring to FIG. 3B, the pixel PX structure included in the organic light emitting display device according to the present invention will be described in more detail. The pixels PX include an organic light emitting diode EL displaying an image gray level, and an organic light emitting diode. And a plurality of thin film transistors SWT, DRT, and SST for supplying a current for driving to EL and sensing a threshold voltage characteristic.

Here, the plurality of thin film transistors SWT, DRT, and SST may form an active layer, and may include amorphous silicon (a-si), low temperature polysilicon (LTPS), an oxide semiconductor, or the like.

The anode electrode of the organic light emitting diode EL is connected to the driving thin film transistor DRT, and the ground voltage ELVSS is applied to the cathode electrode. Therefore, the organic light emitting diode EL generates light having a predetermined luminance in response to a current supplied through the driving thin film transistor DRT.

The organic light emitting diode EL may include an organic compound layer, and the organic compound layer may further include various organic layers for efficiently transferring a carrier of holes or electrons to the light emitting layer in addition to the light emitting layer in which actual light is emitted. The organic layers may include a hole injection layer and a hole transport layer positioned between the first electrode and the light emitting layer, and an electron injection layer and an electron transport layer positioned between the second electrode and the light emitting layer.

The gate electrode and the drain electrode of the switching thin film transistor SWT are connected to the gate wiring GL and the data wiring DL, respectively, and the source electrode is connected to the gate electrode of the driving thin film transistor DRT, and is connected to the scan signal Vscan. Accordingly, the data signal Vdata is charged to the gate electrode of the driving thin film transistor DRT.

The pixel shows an example in which each of the thin film transistors SWT, DRT, and SST is configured by using an N-type MOSFET, but is not limited thereto. The pixel may also be replaced by a P-type MOSFET thin film transistor. When the P-type MOSFET thin film transistor is used, the circuit configuration is the same and there is a difference in that the scan signal Vscan and the sensing signal Vsense are output in an inverted form.

In particular, in the switching thin film transistor SWT, the scan signal Vscan applied by the parasitic capacitance PC between the gate electrode and the gate wiring GL and the resistance component of the gate wiring GL itself is positioned at the position of the gate wiring. As a result, a deviation occurs, which affects the gate-source voltage Vgs of the driving thin film transistor DRT, which causes deterioration in image quality. In order to solve this problem, the present invention applies the gate pulse modulation signal GPM to the scan signal Vscan, but adjusts the gate high voltage VGH of the gate pulse modulation signal GPM according to the signal delay. It is done. This gate pulse modulation signal (GPM) adjustment will be described in detail later.

In the driving thin film transistor DRT, a gate electrode is connected to the switching thin film transistor SWT, and a power supply voltage ELVDD is applied to the drain electrode. The source is connected to the anode electrode of the organic light emitting diode EL. According to this structure, when the data signal Vdata is applied through the switching thin film transistor SWT, the driving thin film transistor DRT is charged with a voltage corresponding to the data signal Vdata to the gate electrode, thereby providing a gate-source voltage Vgs. The drain-source current Ids flows through the organic light emitting diode EL to emit light.

The driving thin film transistor DRT is connected to the switching thin film transistor SWT, the sensing thin film transistor SST, and the capacitor CPT around the source electrode.

In the sensing thin film transistor SST, a gate electrode is connected to the sensing wiring, a drain electrode is connected to the source electrode of the driving thin film transistor SST, and is connected to the source electrode reference voltage wiring. Here, the sensing signal Vsense supplied through the sensing wiring may be supplied in a sensing period in which the threshold voltage and mobility information of the driving thin film transistor DRT are extracted, and the driving thin film transistor DRT may be provided according to the reference voltage Vref. Sink the current flowing through).

The capacitor CAP is provided between the gate electrode and the source electrode of the driving thin film transistor DRT to charge the voltage between the gate and the source Vgs and maintain the voltage level during the light emitting period of the organic light emitting diode EL. Play a role.

In the pixel PX having such a structure, signal delay is improved by controlling the following driving units 110 to 150 to display an image of uniform luminance.

The gate driver 110 may be implemented as a plurality of driving ICs connected in parallel, and each driving IC may include a shift register having a plurality of stages. The gate driver 110 sequentially applies the scan signal Vscan to each pixel PX by one horizontal line corresponding to the gate control signal GCS output from the timing controller 130, thereby switching thin film transistors. Turn on (SWT). Here, the scan signal Vscan has a voltage level determined by the gate modulated signal GPM generated by the gate modulator 150, and the gate modulated signal GPM is determined by the position of each gate line GL. The signal delay is considered and reflected in the gate control signal GCS through the timing controller 130.

The gate control signal GCS provided to the gate driver 110 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE). Etc.

The gate start pulse GSP described above is a signal for determining when to output a gate driving signal to the gate wiring GL for each driving IC. The gate shift clock GSC is a clock signal commonly applied to the shift register of the gate driver 110, and the next shift register is activated in synchronization with the gate shift clock GSC. The gate output enable signal GOE is a signal for controlling the output of the shift register.

In particular, referring to FIG. 3C, the gate start pulse GSP is applied to the first stage st1 of the shift register to determine an output time point of the scan signals Vscan1 to Vscan n, and each stage st1 to st. n) uses the previous stage output as a gate start pulse. Therefore, in the present invention, a signal input as a gate start pulse to the gate start pulse GSP and the last stage st n initially output from the timing controller 130, that is, the output of the n-1 stage st n-1 The waveform of the n-th scan signal Vscan n-1, which is a signal, is compared and the degree of signal delay is determined according to the difference.

Referring back to FIG. 3A, the data driver 120 receives an aligned image signal aRGB of a digital waveform applied from the timing controller 130, and has an analog voltage having a gray value that the pixel PX can process. The data signal Vdata is converted into a form data signal Vdata, and the data signal Vdata is supplied to each pixel PX through the data line DL in response to the input data control signal DCS.

The data control signal DCS includes a source start pulse SSP, a source shift clock SSC, and a source output enable SOE.

The source start pulse SSP is a signal that determines the sampling start timing of the image data of the data driver 120. The source shift clock SSC is a clock signal that controls the data sampling operation in the data driver 120. In addition, the source output enable signal SOE is a signal for controlling the output of the data driver 120.

In addition, the timing controller 130 receives timing data such as image data, clock signals, vertical and horizontal synchronization signals, etc., which are applied from the outside, and includes a gate control signal GCS, a data control signal DCS, and a sensing driving control signal ( Various control signals including SCS) are generated.

The timing controller 130 is connected to an external system through a predetermined interface to receive image-related signals and timing signals output therefrom at high speed without noise.

The sensing controller 140 turns on the sensing thin film transistor SST provided in each pixel PX in the sensing section in response to the sensing control signal SCS applied from the timing controller 130. ) Is applied. The sensing signal Vsense may be applied by one horizontal line unit like the scan signal Vscan, but the period is not fixed.

In addition, the sensing controller 140 compensates for the deviation of the threshold voltage and the electron mobility of the driving thin film transistor DRT by using an external voltage compensation method or an internal voltage compensation method. According to the external voltage compensation method, the current flowing through the pixel PX through the reference voltage wiring is sinked, and the threshold voltage Vth of the driving thin film transistor DRT of each pixel PX according to the sinked current. And electron mobility μ. The threshold voltage compensator 150 compares the current flowing through the driving thin film transistor DRT with the sinked current value in a steady state, thereby changing the threshold voltage and electron mobility of the driving thin film transistor DRT of each pixel PX. The degree is calculated and the data signal Vdata is compensated accordingly.

In addition, according to the internal voltage compensation method, a specific voltage is applied to the gate electrode of the driving thin film transistor DRT to store a predetermined voltage in which the threshold voltage Vth of the driving thin film transistor is reflected on the capacitor CAP, and the reference voltage ( Vref) is applied so that only the voltage from which the threshold voltage Vth is removed from the voltage stored in the capacitor CAP is stored, and the drain-source current of the driving thin film transistor DRT flows through the voltage through the voltage. The threshold voltage deviation is compensated for.

 The gate modulator 150 has a gate high voltage VGH within an output period of the scan signal Vscan in order to minimize kickback voltage according to the parasitic capacitance PC between the gate line GL and the switching thin film transistor SWT. Is first converted to the gate middle voltage VGM, and then the gate pulse modulated signal GPM is modulated to be gradually switched to the gate low voltage VGL, and then supplied to the timing controller 130.

The timing controller 130 includes a predetermined control signal generator for controlling the driving units 110, 120, and 140, and generates and outputs each control signal GCS, DCS, or SCS.

In particular, among the control signals, the gate control signal GCS includes a gate start pulse GSP that defines a start point of the gate driving IC forming the gate driver 110, and is input to the last stage of the gate driver 130. The scan signal Vscan is input to the gate modulator 150 as the gate start pulse GSP 'reflecting the signal delay, and the gate modulator 150 generates the gate pulse modulated signal GPM.

According to the above structure, the organic light emitting display device of the present invention can efficiently improve the gate-source voltage deviation of the driving thin film transistor according to the kickback voltage and the signal delay, thereby improving driving reliability and improving image quality.

Hereinafter, a timing controller and a gate modulator included in an organic light emitting display device according to an exemplary embodiment of the present invention will be described with reference to the drawings.

4 is a diagram illustrating a structure of a timing controller and a gate modulation according to an embodiment of the present invention.

Referring to FIG. 4, the timing controller 130 of the present invention includes an image data processor 132 for arranging and correcting image data input from the outside and supplying the image data to the data driver, and for controlling the gate, data, and the sensing driver. And a power supply unit 136 for outputting voltages VGH, VGM, and VGL for driving the gate driver.

The image data processor 132 receives the image data RGB and arranges and corrects the image data RGB in a form that the data driver can process, and outputs the corrected image data aRGB to the data driver.

The control signal processor 134 may include a gate, data, and sensing driver in response to timing signals such as the vertical and horizontal synchronization signals Vsync and Hsync, the data enable signal DE, and the clock signal DCLK. It generates a gate control signal GCS, a data control signal DCS, and a sensing control signal SCS for controlling each of them, and outputs them to each driver.

The power supply unit 136 generates gate high voltages, middle voltages, and low voltages VGH, VGM, and VGL that determine voltage levels of scan signals of the gate driver, and outputs the gate voltages to the gate driver. In particular, the output period of the voltages supplied to the gate driver is determined by the gate pulse modulation signal GPM. The power supply unit 136 may include a predetermined level shifter to stably output the voltages VGH, VGM, and VGL according to a required voltage level.

The gate modulator 150 receives a control signal from the liquid crystal panel and calculates a signal delay degree of the scan signal. The gate modulator 150 modulates a gate pulse according to the calculated result. It includes.

The signal delay calculator 152 receives the gate start pulse GSP ′ input to the last stage of the gate driver, determines whether the signal is delayed by comparing with the preset gate start pulse, and calculates the signal delay degree. The GPM timing adjusting unit 154 outputs the result.

The GPM timing controller 154 adjusts the signal interval width of the gate high voltage VGH to be narrower than the normal state within one period of the gate pulse modulated signal according to the calculated signal delay degree. The scan signal transitions to the gate high voltage (VGH) and the gate middle voltage (VGM) for one horizontal period (1H) after the on point of the gate wiring in the gate low voltage (VGL) state, and then the gate low voltage (VGL). It is a signal to maintain state. Therefore, when it is determined that there is almost no signal delay, the periods of the gate high voltage VGH and the gate middle voltage VGM are substantially the same for one horizontal period.

However, as the signal delay increases, the switching transistor remains turned on for more than one horizontal period, causing malfunction. In addition, when the gate pulse modulation signal (GPM) is applied, not only does the turn-on time of the switching transistor increase, but also the signal waveform rapidly changes in the panel edge region, that is, the signal input terminal of the gate driver. The deviation of the kickback voltage (field through effect) from the region is weighted.

5A and 5 are diagrams illustrating signal waveforms of a general gate pulse modulation signal GPM and signal delays inside a display panel.

5A and 5B, the gate pulse modulated signal GPM is formed when a gate start pulse GPS is applied and a stage of the gate driver is shifted by the gate shift clock GSC. Accordingly, the gate pulse modulation signal GPM is output in synchronization with the time point at which the scan signals Vscan n and Vscan n + 1 are output, and the voltages Vn and Vn + applied to the gate electrode of the driving thin film transistor of each pixel. 1) is changed from the gate high voltage VGH to the gate low voltage VGL via the gate middle voltage VGM.

In contrast, when a signal delay occurs, the gate pulse modulation (GPM) signal is not affected by the signal delay as it is externally generated and output, but the gate start pulse (GSP) and the gate output enable signal (GOE). ) Is delayed in a gentle form, increasing the transition period to the low level. Accordingly, the scan signals Vscan n and Vscan n + 1 are also delayed and overlapped with each other. In particular, the voltages Vn and Vn + 1 applied to the gate electrode are delayed, causing malfunction.

Therefore, in the present invention, the switching transistor is controlled to be turned off at the normal time by narrowing the width of the gate high voltage VGH and advancing the start time of the gate middle voltage VGM.

That is, when the signal delay occurs, the GPM timing adjusting unit 154 narrowly controls the period of the gate high voltage VGH within one period of the gate pulse modulated signal GPM.

Hereinafter, a method of driving an organic light emitting display device including a gate modulator according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

6 is a view illustrating a method of driving an organic light emitting display device including a gate modulator according to an exemplary embodiment of the present invention, and FIG. 7 is a view illustrating a signal waveform when driving the organic light emitting display device of FIG. 6.

Referring to FIG. 6, in the method of driving an organic light emitting display device according to the present invention, generating a gate control signal (S100), any one of the gate control signal, and a control signal applied from the gate driver is used. Determining a signal delay between gate wirings (S110), adjusting the gate pulse modulation signals according to the determination result (S120 to S130), and outputting the gate pulse modulation signal (S140). .

The generating of the gate control signal (S100) is a step in which the timing controller generates a gate start pulse GSP, a gate shift clock GSC, and a gate enable signal GOE for controlling the gate driver.

Determining the signal delay between the gate wiring using any one of the gate control signal and the control signal applied from the gate driver (S110) is the gate modulating gate start pulse (GSP) of the gate control signal And determining whether the signal is delayed by comparing the gate start pulse GSP 'input to the last stage of the gate driver. Here, the gate start pulse GSP 'becomes the scan signal Vscan n-1 input to the last stage among the scan signals Vscan1 to Vscan n. That is, the degree of signal delay is determined by comparing a and b of FIG. 6 and comparing the widths of the high sections. Here, the waveform comparison is not to compare voltage levels but to determine the width of the high section.

In step S120 to S130, according to the determination result, if it is determined that the signal delay does not occur in step S110, the setting of the gate pulse modulation signal is maintained as it is (S120). If it is determined that the width of the gate high voltage VGH is narrowed in one cycle of the gate pulse modulation signal GPM, the gate pulse modulation signal is adjusted. Here, the gate pulse modulation signal GPM is a signal defining a period in which the scan signal is modulated into three states of the gate high voltage VGH, the gate low voltage VGL, and the gate middle voltage VGM.

The number of gate lines is fixed, and the period of the gate high voltage VGH supplied for each gate line is adjusted according to the degree of signal delay and then output.

The step of outputting the gate pulse modulation signal (S140) is a step of outputting the gate pulse modulation signal (GPM) adjusted in step S130 to the timing controller, the timing controller adjusts the output period of the voltages input to the gate driver accordingly. Will print.

FIG. 8 is a view comparing signal waveforms according to a delay of driving an organic light emitting display device according to an exemplary embodiment of the present invention.

First, when there is almost no signal delay as the initial output of the scan signal (a), when the organic light emitting display device is driven, the scan signal is gate high voltage (VGH) and gate middle voltage (VGM) for one horizontal period (1H). When the gate low voltage VGL is sequentially changed, the voltage charged in the gate electrode of the driving thin film transistor is changed from V1 to V3.

In contrast, when a signal delay occurs as an output terminal of the scan signal (b), the scan signal is gate high voltage VGH, gate middle voltage VGM, and gate low voltage VGL during one horizontal period 1H. When sequentially changing, the transition period from the gate high voltage VGH to the gate middle voltage VGM is delayed, and the transition period from the gate middle voltage VGM to the gate low voltage VGL is delayed. As the switching thin film transistor is turned off when the voltage level reaches the gate low voltage VGL, the switching thin film transistor is charged with the gate electrode voltage over one horizontal period in the related art, causing a deviation.

However, in the present invention, when the signal delay occurs, the section of the gate high voltage VGH is narrower than the case where there is no signal delay (t1> t2), so that the gate middle voltage VGM and the gate low voltage VGL are set. The change point of the voltage is accelerated so that the voltage level at the end of charging of the gate electrode voltage is matched to the same voltage V3.

Here, depending on the width of the gate high voltage VGH, the charging start point of each gate electrode may be delayed by t3, and the voltage level may be different at the maximum charging of each gate electrode (V2> V2 '). Finally, the voltage charged to the gate electrode is the same (V3), and the variation of the gate-source voltage Vgs of the driving thin film transistor for each horizontal line can be minimized.

Meanwhile, in the above-described embodiment, the signal delay degree is determined by using the gate control signal, and the output of the scan signal is compensated through this. However, the signal delay degree is determined through the feedback of the scan signal, and the offset of the gate pulse modulation signal is obtained. Signal delay compensation can also be performed by adjusting.

FIG. 9 is a view illustrating signal waveforms when driven by a method of driving an organic light emitting display device including a gate modulator according to another exemplary embodiment of the present invention.

Referring to FIG. 9, the gate start pulse GPS is applied to the gate driver, and the gate pulse modulated signal GPM is output at the time when the stage of the gate driver is shifted by the gate shift clock GSC. The scan signals Vscan n and Vscan n + 1 are output. In the normal case, the scan signals Vscan n and Vscan n + 1 are output at a high level in synchronization with the gate output enable signal GOE. The transition time to the low level is also delayed.

In another exemplary embodiment of the present invention, the scan signals Vscan n and Vscan n + 1 are received to detect a delay time d, and correspondingly, a normal shape is obtained through an offset of the gate pulse modulation signal GPM. The voltage level of the low scan signals Vscan n and Vscan n + 1 is controlled to be shifted. The offset of the gate pulse modulated signal GPM is a method of delaying the high level transition time of the gate pulse modulated signal GPM by the delay time d.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

100: display panel 110: gate driver
120: data driver 130: timing controller
140: sensing driver 150: gate modulator
GL: Gate wiring DL: Data wiring
SL: Sensing Wiring PX: Pixel

Claims (13)

A display panel in which a plurality of gate lines and data lines cross each other and pixels are defined at intersections;
A gate driver connected to the gate line to sequentially output a scan signal;
A data driver connected to the data line to output a data signal;
A timing controller configured to control the gate driver and the data driver through a control signal; And
A gate modulator for determining a signal delay between the gate lines using a control signal applied to the gate driver, and adjusting and outputting a gate pulse modulation signal output to the timing controller according to a determination result
An organic light emitting display device comprising a. The method of claim 1,
The gate driver,
And a plurality of stages for sequentially outputting the scan signals. The method of claim 2,
The control signal used for the signal delay determination is a gate start pulse (GSP),
The gate modulator,
Calculating a signal delay degree by comparing waveforms of the gate start pulse applied to the first stage among the plurality of stages and the waveform of the scan signal applied as the gate start pulse to the last stage;
An organic light emitting display device, characterized in that. The method of claim 3, wherein
The gate pulse modulated signal,
And a signal defining a period in which the scan signal is modulated into three states of a gate high voltage VGH, a gate low voltage VGL, and a gate middle voltage VGM. The method of claim 4, wherein
The gate modulator,
A signal delay calculator configured to calculate a signal delay degree using the gate start pulse; And
A GPM timing adjusting unit for adjusting the signal interval width of the gate high voltage to be narrower than a normal state in one period of the gate pulse modulation signal in response to the calculated signal delay degree
An organic light emitting display device comprising a. The method of claim 1,
The pixel,
A switching thin film transistor having a gate electrode connected to the gate line and a drain electrode connected to the data line;
A driving thin film transistor having a gate electrode connected to the switching thin film transistor and a drain electrode connected to a power supply voltage terminal;
A capacitor connected between the switching thin film transistor and the source electrode of the driving thin film transistor; And
An organic light emitting diode having an anode connected to a source electrode of the driving thin film transistor and a cathode connected to a ground voltage terminal
An organic light emitting display device comprising a. The method of claim 6,
The pixel,
And a sensing thin film transistor having a gate electrode connected to a wiring for supplying a sensing signal, a source electrode connected to a reference voltage wiring, and a drain electrode connected to a source electrode of the driving thin film transistor. In the driving method of an organic light emitting display device comprising a gate modulator,
Generating a gate control signal from the timing controller and outputting the gate control signal to the gate driver;
The signal delay between the gate lines is determined by using any one of the gate control signals output from the gate modulator to the gate driver and the signal output from the gate driver, and the gate pulse modulation signal is adjusted according to the determination result. Outputting the timing control unit to the timing controller. The method of claim 8,
Determining the signal delay between the gate wirings
Calculating a degree of signal delay by comparing a waveform of a gate start pulse (GSP) applied to an initial stage among the plurality of stages of the gate driver and a waveform of a scan signal input to the last stage as a gate start pulse; A method of driving an organic light emitting display device. The method of claim 9,
The gate pulse modulated signal,
And a signal defining a period in which the scan signal is modulated into three states of a gate high voltage (VGH), a gate low voltage (VGL), and a gate middle voltage (VGM). The method of claim 10,
The gate pulse modulated signal is
And a signal interval width of the gate high voltage is narrower than a normal state within one period of the gate pulse modulation signal in response to the calculated signal delay degree. The method of claim 8,
And the gate modulating unit adjusts the gate pulse modulated signal by setting an offset of the gate pulse modulated signal according to the signal delay degree. The method of claim 12,
And an offset of the gate pulse modulation signal is set such that a time point at which the transition from the low level to the high level of the scan signal output from the gate driver is delayed according to the signal delay degree.

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