KR20130072909A - Shift register and display device including the same - Google Patents

Abstract

PURPOSE: A shift register and a display device including the same are provided to reduce kick back voltage by reducing the gate high voltage and gate low voltage of a gate pulse. CONSTITUTION: A clock pulse modulation circuit (CPM) modulates voltage of a falling edge of i phase (i is a natural number over 3) clocks in which phase is gradually delayed into low voltage which is lower than gate high voltage. Multiple stages outputs a gate pulse which has a same pulse with a clock modulated from the clock pulse modulation circuit inputted from a clock terminal by responding start voltage which is inputted through a start terminal or a shear carry signal. The clock pulse modulation circuit comprises a first thin film transistor (TFT) (T1) and a second TFT (T2).

Description

SHIFT REGISTER AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a shift register and a display device including the same.

BACKGROUND ART [0002] Liquid crystal display devices are becoming increasingly widespread due to features such as light weight, thinness, and low power consumption driving. The liquid crystal display device is used as a portable computer such as a notebook PC, an office automation device, an audio / video device, and an indoor / outdoor advertisement display device. The liquid crystal display displays an image by controlling an electric field applied to the liquid crystal cells to modulate the light incident from the backlight unit.

An active matrix type liquid crystal display device includes a liquid crystal display panel including a thin film transistor (TFT) that is formed for each pixel and switches a data voltage supplied to the pixel electrode, and a data driving circuit for supplying data voltage to data lines of the liquid crystal display panel. A gate driving circuit for sequentially supplying a gate pulse (or scan pulse) GP to gate lines of a liquid crystal display panel, and a timing controller for controlling the operation timing of the driving circuits.

In an active matrix type liquid crystal display device, the voltage charged in the liquid crystal cell is influenced by a kickback voltage or a feed through voltage ΔVp generated by the parasitic capacitance of the TFT. The kickback voltage (Vp) is expressed by Equation (1).

Here, 'Clc' is the capacitance of the liquid crystal cell, 'Cst' is the capacitance of the storage capacitor, and 'Cgd' is the drain terminal of the TFT connected to the gate terminal of the TFT connected to the gate line and the pixel electrode of the liquid crystal cell. The parasitic capacitance formed therebetween, and 'VGH-VGL' is a difference voltage between the gate high voltage VGH and the gate low voltage VGL of the gate pulse GP as shown in FIG. 1.

Due to the kickback voltage DELTA Vp, the voltage applied to the pixel electrode of the liquid crystal cell is changed, so that flicker, afterimage, color deviation, and the like may be seen in the display image. In order to reduce the kickback voltage DELTA Vp, a gate pulse modulation is applied to modulate the gate high voltage VGH at the falling edge of the gate pulse GP.

Meanwhile, the gate driving circuit of the liquid crystal display device may be formed by mounting a gate drive integrated circuit on a printed circuit board (PCB) and attaching it to a display panel by a tape automated bonding (TAB) method. It may be formed in the GIP (Gate Drive IC in Panel) method. When the gate driving circuit is formed by the GIP method, the liquid crystal display device can be made slimmer than the gate driving circuit is formed by the TAB method, so that the external aesthetics can be increased and the cost can be reduced. There is an advantage that the display panel maker can design directly.

The present invention provides a shift register and a display device including the same which form a gate driving circuit using a GIP method and simultaneously reduce a kickback voltage.

A shift register according to an embodiment of the present invention includes a clock pulse modulation circuit for modulating the voltage at the falling edge of i (i is a natural number of 3 or more) phase clocks of which phase is sequentially delayed to a voltage lower than a gate high voltage; And a plurality of stages for outputting a gate pulse having the same pulse as the clock modulated from the clock pulse modulation circuit input through the clock terminal in response to the start voltage or the front carry signal input through the start terminal.

The shift register according to another embodiment of the present invention includes i (i is a natural number of 3 or more) phase clocks whose phases are sequentially delayed through the clock terminal in response to a start voltage or a front carry signal input through the start terminal. A plurality of stages for outputting a gate pulse having the same pulse as any one of; And a gate pulse modulation circuit for modulating and outputting a voltage at the falling edge of the gate pulse to a voltage lower than a gate high voltage.

According to an exemplary embodiment of the present invention, a display device includes: a display panel on which data lines and gate lines are formed; A data driving circuit converting input digital video data into an analog data voltage and supplying the converted digital video data to the data lines; And a gate driving circuit which sequentially outputs gate pulses synchronized with the data lines to the gate lines, wherein the gate driving circuit is configured of clocks of i (i is a natural number of 3 or more) whose phases are sequentially delayed. A clock pulse modulation circuit for modulating the voltage at the falling edge to a voltage lower than the gate high voltage; And a shift register including a plurality of stages for outputting a gate pulse having the same pulse as the clock modulated from the clock pulse modulation circuit input through the clock terminal in response to the start voltage or the front carry signal input through the start terminal. It is characterized by including.

In accordance with still another aspect of the present invention, a display device includes: a display panel on which data lines and gate lines are formed; A data driving circuit converting input digital video data into an analog data voltage and supplying the converted digital video data to the data lines; And a gate driving circuit configured to sequentially output gate pulses synchronized with the data lines to the gate lines, wherein the gate driving circuit is configured to be a clock terminal in response to a start voltage or a front carry signal input through a start terminal. A plurality of stages for outputting a gate pulse having the same pulse as any one of i (i is a natural number of 3 or more) phase clocks sequentially inputted through i; And a shift register including a gate pulse modulation circuit for modulating and outputting a voltage at the falling edge of the gate pulse to a voltage lower than a gate high voltage.

The present invention modulates the voltage of the falling edge of the clock input to the clock terminal of each stage by using a clock pulse modulation circuit. As a result, the present invention can reduce the difference voltage between the gate high voltage and the gate low voltage of the gate pulse, thereby reducing the kickback voltage. In addition, the present invention forms a clock pulse modulation circuit in a shift register rather than a printed circuit board. As a result, the present invention can design the shift register including the clock pulse modulation circuit by the GIP method, it is possible to reduce the cost.

The present invention modulates the voltage at the falling edge of the gate pulse output from the output terminal of each of the stages using a gate pulse modulation circuit. As a result, the present invention can reduce the difference voltage between the gate high voltage and the gate low voltage of the gate pulse, thereby reducing the kickback voltage. In addition, the present invention forms a gate pulse modulation circuit in the shift register rather than the printed circuit board. As a result, the present invention can design the shift register including the gate pulse modulation circuit by the GIP method, it is possible to reduce the cost.

1 is a view showing an example of a gate pulse output from the gate driving circuit.
2 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.
3 is a block diagram showing a shift register according to a first embodiment of the present invention;
4 is a waveform diagram showing a clock pulse modulated signal, clocks input to a shift register, clocks modulated from a clock pulse modulation circuit, and a gate pulse output from a shift register according to a first embodiment of the present invention;
5A through 5C are simulation result diagrams showing a clock input to a shift register, a clock modulated by a clock pulse modulation circuit, and a gate pulse output from a kth stage.
6 is a block diagram showing a shift register according to a second embodiment of the present invention.
7 is a waveform diagram showing clocks input to a shift register, outputs of respective stages, and gate pulses output from a gate pulse modulation circuit according to a second embodiment of the present invention;
8 is a simulation result diagram showing a gate pulse output from a shift register.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

2 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention. Referring to FIG. 2, the display device according to the exemplary embodiment includes a display panel 10, a data driving circuit, a gate driving circuit, a timing controller 11, and the like.

The display device according to the embodiment of the present invention includes any display device that sequentially supplies gate pulses (or scan pulses) to the gate lines to write digital video data to the pixels by line sequential scanning. For example, a display device according to an embodiment of the present invention includes a liquid crystal display (LCD), an organic light emitting diode display (OLED), and a field emission display (FED). The electrophoretic display device may be implemented as one of electrophoresis (EPD). Although the present invention has been exemplified in the following embodiments with the display device implemented as a liquid crystal display device, it should be noted that the display device of the present invention is not limited to the liquid crystal display device. The liquid crystal display may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display.

In the display panel 10, a liquid crystal layer is formed between two substrates. The lower substrate of the display panel 10 includes data lines, gate lines intersecting the data lines, thin film transistors (TFTs) formed at intersections of the data lines and the gate lines, and connected to the pixel electrode and the common electrode. A TFT array including liquid crystal cells driven by an electric field between them, a storage capacitor, and the like is formed. A color filter array including a black matrix and a color filter is formed on the upper substrate of the display panel 10. The liquid crystal display according to the exemplary embodiment of the present invention may also be implemented in a liquid crystal mode such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, or fringe field switching (FFS). The common electrode may be formed on the upper substrate in the vertical electric field driving method such as the TN mode and the VA mode, and may be formed on the lower substrate together with the pixel electrode in the horizontal electric field driving method such as the IPS mode and the FFS mode. Polarizing plates having optical axes orthogonal to each other are attached to the upper substrate and the lower substrate of the display panel 10, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal layer.

The data drive circuit includes a plurality of source drive ICs 12. [ The source drive ICs 12 receive the digital video data DATA from the timing controller 11. Each of the source drive ICs 12 converts the digital video data DATA into a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, and synchronizes the data voltage with a gate pulse. The data lines of the display panel 10 are supplied to each other. The source drive ICs 12 may be connected to data lines of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driving circuit includes a level shifter 13 and a shift register 14. The level shifter 13 level shifts the TTL (Logic-Transistor-Logic) logic level voltage of the clocks CLKs input from the timing controller 11 to the gate high voltage VGH and the gate low voltage VGL. The level shifted clocks CLKs are input to the shift register 14. The shift register 14 is connected to the gate lines of the display panel 10 to sequentially output gate pulses to the gate lines. The shift register 14 is directly formed on the lower substrate of the display panel 10 by a gate drive-IC in panel (GIP) method. In the GIP method, the level shifter 13 is mounted on a printed circuit board 15.

The timing controller 11 receives digital video data RGB from an external host system through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 11 transmits digital video data DATA input from the host system to the source drive ICs 12. In addition, the timing controller 11 receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a main clock, and the like from the host system through an LVDS or TMDS interface receiving circuit. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host system. The timing control signals include a gate timing control signal for controlling the operation timing of the gate driving circuit, and a data timing control signal DCS for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes a start voltage and clocks CLKs sequentially generated on i (i is a natural number of 3 or more). The start voltage is input to the shift register 14 to control the shift start timing of the shift register 14. The clocks CLKs are input to the level shifter 13, level shifted, and then input to the shift register 14, and are used as clock signals for shifting the start voltage.

The data timing control signal DCS includes a source start pulse, a source sampling clock, a polarity control signal, a source output enable signal, and the like. The source start pulse controls the shift start timing of the source drive ICs 12. The source sampling clock is a clock signal that controls the sampling timing of data in the source drive ICs 12 based on the rising or falling edge. The polarity control signal controls the polarity of the data voltage output from the source drive ICs 12. If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

3 is a block diagram illustrating a shift register according to a first embodiment of the present invention. Referring to FIG. 3, the shift register 14 according to the first embodiment of the present invention includes a plurality of stages (ST (1) to ST (n) where n is a natural number of stages) that are connected in a cascade manner. A clock pulse modulation circuit (CPM) is provided. In FIG. 3, for convenience of explanation, only kth (1 <k <n, k is a natural number of 2 or more) to k + 3th stages ST (k) to ST (k + 3) are illustrated.

In the following description, the "shear stage" refers to being located on top of the stage to be a reference. For example, on the basis of the k-th stage ST (k), the front stage indicates any one of the first stage ST (1) to the (k-1) th stage ST (k-1). The "back stage" refers to being located at the lower part of the stage used as a reference. For example, on the basis of the k-th stage ST (k), the trailing stage indicates any one of the (k + 1) th stages ST (k + 1) to k (n).

The start voltage is applied to the start voltage line (not shown), the clock pulse modulation signal Vcpm is applied to the clock pulse modulation signal supply line Vcpm Line, and the gate low voltage VGL is applied to the gate low voltage line VGL Line. ) Is applied. In addition, a first clock CLK1 is applied to the first clock line CL1, a second clock CLK2 is applied to the second clock line CL2, and a third clock (CL3) is applied to the third clock line CL3. CLK3 is applied, and a fourth clock CLK4 is applied to the fourth clock line CL4.

Each of the stages ST (1) to ST (n) includes a start terminal START, a clock terminal CLK, a reset terminal RESET, and an output terminal OUT. Each of the stages ST (1) to ST (n) is pulled up in response to a start voltage or a front carry signal input through the start terminal START, and a rear carry signal input through the reset terminal RESET. It is pulled down in response. Each of the stages ST (1) to ST (n) outputs a gate pulse having the same pulse as the clock inputted through the clock terminal CLK through the output terminal OUT.

A start voltage or a carry signal of a previous stage is input to the start terminal START of each of the stages ST (1) to ST (n). For example, as shown in FIG. 3, the output of the k-th stage ST (k), which is the carry signal of the previous stage, is input to the start terminal START of the k + 2th stage ST (k + 2). The carry signal of the rear stage is input to the reset terminal RESET of each of the stages ST (1) to ST (n). For example, as shown in FIG. 3, the output of the k + 2th stage ST (k + 2), which is the carry signal of the rear stage, is input to the reset terminal RESET of the kth stage ST (k).

The clock terminal CLK of each of the stages ST (1) to ST (n) receives one of the clocks modulated by the clock pulse modulation circuit CPM among the i-phase clocks whose phases are sequentially delayed. . I-phase clocks are preferably implemented in four or more phases to ensure sufficient charging time during high-speed operation of 120 Hz or more. For example, the i-phase clocks may be implemented as four-phase clocks CLK1, CLK2, CLK3, and CLK4 as shown in FIG. 4. In the first embodiment of the present invention, for convenience of description, i-phase clocks have been described based on the four-phase clocks CLK1, CLK2, CLK3, and CLK4. However, the present invention is not limited thereto. The phases of the four-phase clocks CLK1, CLK2, CLK3, and CLK4 may be sequentially delayed every predetermined first period as shown in FIG. 3. The predetermined first period may be appropriately implemented within approximately one horizontal period to two horizontal periods. One horizontal period means one line scanning time in which data is written in one line of pixels of the display panel. In addition, since the four-phase clocks CLK1, CLK2, CLK3, and CLK4 are level shifted from the level shifter 13 to the TTL logic level, the four phase clocks CLK1, CLK2, CLK3, and CLK4 swing between the gate high voltage VGH and the gate low voltage VGL. The four-phase clocks CLK1, CLK2, CLK3, and CLK4 generate pulses at the gate high voltage VGH. The gate low voltage VGL may be set to approximately −7V to −15V, and the gate high voltage VGH may be set to approximately 15V to 30V. In addition, the j-th (j is a natural number) clock CLKj and the j + 1 th clock CLKj + 1 overlap pulses for a predetermined second period as shown in FIG. 4. The predetermined second period may be implemented as about 1/4 to 1/3 of the pulse width of the j th clock CLKj.

Each of the stages ST (1) to ST (n) has one output terminal OUT. The outputs ST (1) _out to ST (n) _out of each of the stages ST (1) to ST (n) have gate pulses GP (1) to GP () applied to gate lines of the display panel 10. n)) and is input as a carry signal to the start terminal START of the rear stage. Since each of the stages ST (1) to ST (n) is cascaded, the first stage ST (1) to the nth stage only when the start voltage is supplied to the first stage ST (1). The output occurs sequentially until (ST (n)).

The clock pulse modulation circuit CPM modulates the gate high voltage VGH at the falling edge of each of the i-phase clocks, and then modulates the modulated clock to a clock terminal of each of the stages ST (1) to ST (n). Output The clock pulse modulation circuit CPM includes a first TFT T1 and a second TFT T2. The first TFT T1 connects the j th clock line CLj to the gate low voltage line VGL Line in response to the j + 1 th clock CLKj + 1. The gate electrode of the first TFT T1 is connected to the source electrode of the second TFT T2, the source electrode is connected to the gate low voltage line VGL Line, and the drain electrode is connected to the j th clock line CLj. do. The second TFT T2 supplies the j + 1 th clock CLKj + 1 to the gate electrode of the first TFT T1 in response to the clock pulse modulation signal Vcpm. The gate electrode of the second TFT (T2) is connected to the clock pulse modulation signal supply line (Vcpm Line), the source electrode is connected to the gate electrode of the first TFT (T1), and the drain electrode is the j + 1 clock line ( CLj + 1).

4 is a waveform diagram showing a clock pulse modulated signal, clocks input to a shift register, clocks modulated from a clock pulse modulation circuit, and a gate pulse output from a shift register. 4 shows clock pulse modulated signal Vcpm, four-phase clocks CLK1, CLK2, CLK3, CLK4, clocks modulated from clock pulse modulation circuit CPM (MCLK1, MCLK2, MCLK3, MCLK4), and k-th. Gate pulses GP (k) and GP (k) output from each of the to k + 3th stages ST (k), ST (k + 1), ST (k + 2), and ST (k + 3). +1), GP (k + 2), GP (k + 3)). 4 shows a first rising period t1, a first polling period t2, and a second polling period t3. The first rising period t1 is a period in which a pulse of the j th clock CLKj is generated but no pulse of the j + 1 th clock CLKj + 1 is generated. The first polling period t2 is a period in which the pulse of the j th clock CLKj and the pulse of the j + 1 th clock CLKj + 1 occur, that is, the pulse of the j th clock CLKj and the j + 1 th clock CLKj. It is a period in which pulses of +1) overlap. The second polling period t3 is a period in which a pulse of the j-th clock CLKj does not occur.

3 and 4, the operation of the shift register 14 according to the first embodiment of the present invention will be described in detail.

First, the first clock CLK1 of the clock pulse modulation circuit CPM with reference to the clock pulse modulation signal Vcpm, the first clock CLK1, the second clock CLK2, and the modulated first clock MCLK1. The modulation of is explained in detail. The clock pulse modulated signal Vcpm may be set to a DC voltage capable of turning on the first TFT T1 in consideration of the threshold voltage of the first TFT T1. For example, the clock pulse modulated signal Vcpm is set to the gate high voltage VGH as shown in FIG. 4, or a voltage capable of turning on the first TFT T1 among voltages of 0V or more to reduce power consumption. Can be set.

The clock pulse modulation signal Vcpm is generated at the gate high voltage VGH, the first clock CLK1 is generated at the gate high voltage VGH, and the second clock CLK2 is generated during the first rising period t1. It occurs at the gate low voltage VGL. The second TFT T2 is turned on by the clock pulse modulation signal Vcpm of the gate high voltage VGH, but the first TFT T1 is turned on by the second clock CLK2 of the gate low voltage VGL. Turn off. Accordingly, the modulated first clock MCLK1 output from the clock pulse modulation circuit CPM during the first rising period t1 is output as it is at the gate high voltage VGH.

During the first polling period t2, the clock pulse modulated signal Vcpm is generated at the gate high voltage VGH, the first clock CLK1 is generated at the gate high voltage VGH, and the second clock CLK2 is generated. It occurs at the gate high voltage (VGH). The second TFT T2 is turned on by the clock pulse modulation signal Vcpm of the gate high voltage VGH, and the first TFT T1 is turned on by the second clock CLK2 of the gate high voltage VGH. Is turned on. Since the first clock line CL1 and the gate low voltage line VGL Line are connected due to the turn-on of the first and second TFTs T1 and T2, the first clock CLK1 is the gate high voltage VGH. It cannot be maintained and falls to the voltage level between the gate low voltage VGL and the gate high voltage VGH. Therefore, the modulated first clock MCLK1 output from the clock pulse modulation circuit CPM during the first polling period t2 drops to a voltage lower than the gate high voltage VGH at the falling edge.

During the second polling period t3, the clock pulse modulated signal Vcpm is generated with the gate high voltage VGH, the first clock CLK1 is generated with the gate low voltage VGL, and the second clock CLK2 is It occurs at the gate high voltage (VGH). The second TFT T2 is turned on by the clock pulse modulation signal Vcpm of the gate high voltage VGH, and the first TFT T1 is turned on by the second clock CLK2 of the gate high voltage VGH. Is turned on. However, since the first clock CLK1 falls to the gate low voltage VGL regardless of the turn-on of the first and second TFTs T1 and T2, the clock pulse modulation circuit (eg, The modulated first clock MCLK1 output from the CPM falls to the gate low voltage VGL.

On the other hand, how low the voltage on the falling edge of the j-th clock CLKj depends on how low a voltage is applied to the gate low voltage line VGL Line. In the first embodiment of the present invention, the low voltage of the falling edge of the j-th clock CLKj is modulated using the gate low voltage line VGL supplying the gate low voltage VGL. It should be noted that not. That is, in the first embodiment of the present invention, the voltage of the falling edge of the j th clock CLKj may be modulated low by using a voltage line supplying a predetermined voltage lower than the gate high voltage VGH.

As a result, the clock pulse modulation circuit CPM lowers the voltage at the falling edge of the j-th clock CLKj overlapping the j-th clock CLKj and the j-th + 1-th clock CLKj + 1, which is lower than the gate high voltage VGH. Modulate with voltage That is, the j th clock MCLKj modulated from the clock pulse modulation circuit CPM has substantially the same pulse width, phase delay, and the like as the j th clock CLKj input to the shift register 14. However, the voltage at the falling edge of the j-th clock CLKj overlapping the j-th clock CLKj and the j + 1 th clock CLKj + 1 is modulated to a voltage lower than the gate high voltage VGH.

Secondly, each of the stages ST (1) to ST (n) outputs a gate pulse having the same pulse as the clock input to the clock terminal CLK through the output terminal OUT. Since the clock modulated by the clock pulse modulation circuit CPM is input to the clock terminal CLK of each of the stages ST (1) to ST (n), each of the stages ST (1) to ST (n) is input. The voltage at the falling edge of the gate pulse output through the output terminal OUT of the voltage is lower than the gate high voltage VGH.

As a result, in the first embodiment of the present invention, as shown in FIG. 5A, the voltage of the falling edge of the clock input to the clock terminal CLK of each of the stages ST (1) to ST (n) is converted into a clock pulse modulation circuit CPM. ) Is modulated below the gate high voltage VGH as shown in FIG. 5B. As a result, the first embodiment of the present invention can reduce the difference voltage between the gate high voltage VGH and the gate low voltage VGL of the gate pulse GP in Equation 1 as shown in FIG. 5C. As a result, the first embodiment of the present invention can reduce the kickback voltage.

In addition, the first embodiment of the present invention forms a clock pulse modulation circuit (CPM) in the shift register 14 rather than the printed circuit board. As a result, the present invention can design the shift register 14 including the clock pulse modulation circuit (CPM) by the GIP method, thereby reducing the cost.

6 is a block diagram illustrating a shift register according to a second embodiment of the present invention. Referring to FIG. 6, the shift register 14 according to the second embodiment of the present invention may include a plurality of stages (ST (1) to ST (n) where n is a natural number of stages) that are connected in a cascade manner. A gate pulse modulation circuit GPM is provided. In FIG. 6, for convenience of explanation, only kth (1 <k <n, k is a natural number of 2 or more) to k + 3 stages (ST (k) to ST (k + 3)) are illustrated.

The stages ST (1) to ST (n) of the shift register 14 according to the second embodiment of the present invention are described with reference to FIG. 3 of the shift register 14 according to the first embodiment of the present invention. It is substantially the same as the stages ST (1) to ST (n). Therefore, detailed description of the stages ST (1) to ST (n) of the shift register 14 according to the second embodiment of the present invention will be omitted.

However, a clock pulse modulated signal supply line Vcpm line is not formed in the shift register 14 according to the second embodiment of the present invention, and each of the stages ST (1) to ST (n) has a clock terminal ( CLK) receives a clock of any one of phases i (i is a natural number of 4 or more) whose phase is sequentially delayed.

The gate pulse modulation circuit GPM modulates the gate high voltage VGH at the falling edge of the gate pulse output from each of the stages ST (1) to ST (n), and then modulates the modulated gate pulse to the display panel. Output to the gate lines of step 10). The gate pulse modulation circuit GPM includes a first TFT T1 and a second TFT T2. The first TFT T1 is connected to the output line of the m + 1th stage ST (m + 1) in response to the output ST (m) _out of the mth (m is a natural number) stage ST (m). Connect the gate low voltage line (VGL Line). The gate electrode of the first TFT T1 is connected to the output line of the m (m is a natural number) stage ST (m), the source electrode is connected to the gate low voltage line VGL Line, and the drain electrode is It is connected to the output line of the m + 1 stage ST (m + 1). The second TFT T2 outputs the output line of the m + 1th stage ST (m + 1) in response to the output ST (m + 2) _out of the m + 2th stage ST (m + 2). To the gate low voltage line (VGL Line). The gate electrode of the second TFT T2 is connected to the output line of the m + 2th stage ST (m + 2), the source electrode is connected to the gate low voltage line VGL Line, and the drain electrode is connected to the mth. It is connected to the output line of the +1 stage ST (m + 1).

7 is a waveform diagram illustrating clocks input to a shift register, outputs of respective stages, and gate pulses output from a gate pulse modulation circuit according to a second exemplary embodiment of the present invention. 7 shows four-phase clocks CLK1, CLK2, CLK3, and CLK4, k-th to k + 3 stages ST (k), ST (k + 1), ST (k + 2), and ST (k + 3) output from the respective outputs ST (k) _out, ST (k + 1) _out, ST (k + 2) _out, ST (k + 3) _out, and gate pulse modulation circuit (GPM). Modulated gate pulses GP (k), GP (k + 1), GP (k + 2), GP (k + 3) are shown. In addition, FIG. 7 illustrates a first rising period t1, a second rising period t2, a first polling period t3, and a second polling period t4. The first rising period t1 is a period in which the gate pulse output from the m th stage ST (m) and the gate pulse output from the m + 1 th stage ST (m + 1) overlap each other. The second rising period t2 is a gate pulse output from the mth stage ST (m), a gate pulse output from the m + 1th stage ST (m + 1), and an m + 2th stage ST. This is a period in which the gate pulses output from (m + 2) do not overlap each other. The first polling period t3 is a period in which the gate pulse output from the m + 1th stage ST (m + 1) and the gate pulse output from the m + 2th stage ST (m + 2) overlap each other. . The second polling period t4 is a period in which a gate pulse is polled from the m + 1th stage ST (m + 1).

Hereinafter, the operation of the shift register 14 according to the second embodiment of the present invention will be described in detail with reference to FIGS. 6 and 7.

First, each of the stages ST (1) to ST (n) outputs a gate pulse having the same pulse as the clock input to the clock terminal CLK through the output terminal OUT. The clock terminal CLK of each of the stages ST (1) to ST (n) has a clock of any one of the clocks CLK1, CLK2, CLK3, and CLK4 from the clock lines CL1, CL2, CL3, and CL4. Is input. Each of the stages ST (1) to ST (n) outputs a gate pulse having the same pulse as the input clock through the output terminal OUT.

Secondly, the output ((ST (k) _out) of the kth stage ST (k), the output ((ST (k + 1) _out), of the k + 1th stage ST (k + 1), And the k + 1th stage ST (k + 1) of the gate pulse modulation circuit GPM with reference to the output ((ST (k + 2) _out)) of the k + 2th stage ST (k + 2). The modulation of the output ((ST (k + 1) _out)) will be described in detail.

During the first rising period t1, the output (ST (k) _out) of the k-th stage ST (k) is generated as the gate high voltage VGH and the k + 1th stage ST (k + 1) Output ((ST (k + 1) _out) is generated by the gate high voltage VGH, and the output ((ST (k + 2) _out) of the k + 2th stage ST (k + 2) is The first TFT T1 is turned on by the output (ST (k) _out) of the k-th stage ST (k) of the gate high voltage VGH, and generates the gate low voltage VGL. The second TFT T2 is turned off by the output (ST (k + 2) _out) of the k + 2th stage ST (k + 2) of the gate low voltage VGL. Due to the turn-on of T1, the output line of the k + 1th stage ST (k + 1) is connected to the gate low voltage line VGL Line, thus, the k + 1th stage ST (k + 1). Output ST (k + 1) is discharged to the gate low voltage VGL, even though the output of the k + 1th stage ST (k + 1) is the gate high voltage VGH, Output from the pulse modulation circuit (GPM) The k + 1th gate pulse GP (k + 1) does not rise to the gate high voltage VGH, that is, the k + 1th output from the gate pulse modulation circuit GPM during the first rising period t1. The gate pulse GP (k + 1) has a voltage level between the gate low voltage VGL and the gate high voltage VGH.

During the second rising period t2, the output (ST (k) _out) of the kth stage ST (k) is generated as the gate low voltage VGL, and the k + 1th stage ST (k + 1) Output ((ST (k + 1) _out) is generated by the gate high voltage VGH, and the output ((ST (k + 2) _out) of the k + 2th stage ST (k + 2) is The first TFT T1 is turned off by the output (ST (k) _out) of the k-th stage ST (k) of the gate low voltage VGL, and generates the gate low voltage VGL. The second TFT T2 is turned off by the output (ST (k + 2) _out) of the k + 2th stage ST (k + 2) of the gate low voltage VGL. Due to the turn-off of the two TFTs T1 and T2, the output line of the k + 1th stage ST (k + 1) is not connected to the gate low voltage line VGL Line. The k + 1th gate pulse GP (k + 1) output from the gate pulse modulation circuit GPM during t2 has a voltage level of the gate high voltage VGH.

During the first polling period t3, the output (ST (k) _out) of the kth stage ST (k) is generated as the gate low voltage VGL, and the k + 1th stage ST (k + 1) Output ((ST (k + 1) _out) is generated by the gate high voltage VGH, and the output ((ST (k + 2) _out) of the k + 2th stage ST (k + 2) is The first TFT T1 is turned off by the output (ST (k) _out) of the k-th stage ST (k) of the gate low voltage VGL, and generates the gate high voltage VGH. The second TFT T2 is turned on by the output (ST (k + 2) _out) of the k + 2th stage ST (k + 2) of the gate high voltage VGH. Due to the turn-on of T2, the output line of the k + 1th stage ST (k + 1) is connected to the gate low voltage line VGL Line, thus, the k + 1th stage ST (k + 1). Output ST (k + 1) is discharged to the gate low voltage VGL, even though the output of the k + 1th stage ST (k + 1) is the gate high voltage VGH, Output from the pulse modulation circuit (GPM) The k + 1th gate pulse GP (k + 1) does not rise to the gate high voltage VGH, that is, the k + 1th output from the gate pulse modulation circuit GPM during the first polling period t3. The gate pulse GP (k + 1) has a voltage level between the gate low voltage VGL and the gate high voltage VGH.

During the second polling period t4, the output (ST (k) _out) of the kth stage ST (k) is generated as the gate low voltage VGL, and the k + 1th stage ST (k + 1) ) Output ((ST (k + 1) _out) is generated by the gate low voltage VGL, and the output ((ST (k + 2) _out) of the k + 2th stage ST (k + 2) is The first TFT T1 is outputted from the k-th stage ST (k) of the gate low voltage VGH (ST (k) _out). Is turned off by the second TFT (T2) by the output ((ST (k + 2) _out)) of the k + 2th stage ST (k + 2) of the gate high voltage VGH. However, since the output of the k + 1th stage ST (k + 1) occurs at the gate low voltage VGL regardless of the turn-on of the second TFT T2, the first polling period ( The k + 1th gate pulse GP (k + 1) output from the gate pulse modulation circuit GPM during t3 has a voltage level of the gate low voltage VGL.

On the other hand, how low the voltage of the falling edge of the m-th gate pulse GPm is modulated depends on how low the voltage is applied to the gate low voltage line VGL Line. In the second exemplary embodiment of the present invention, the low voltage of the falling edge of the mth gate pulse GPm is modulated by using the gate low voltage line VGL supplying the gate low voltage VGL. Note that it is not limited. That is, in the second embodiment of the present invention, the voltage of the falling edge of the mth gate pulse GPm may be modulated low by using a voltage line supplying a predetermined voltage lower than the gate high voltage VGH.

As a result, the second embodiment of the present invention uses the gate pulse modulation circuit GPM to calculate the voltage of the falling edge of the gate pulse output from the output terminal of each of the stages ST (1) to ST (n). By modulating lower than the gate high voltage VGH, the difference between the gate high voltage VGH and the gate low voltage VGL of the gate pulse GP may be reduced. As a result, the second embodiment of the present invention can reduce the kickback voltage.

Further, the second embodiment of the present invention forms a gate pulse modulation circuit (GPM) in the shift register 14 rather than the printed circuit board. As a result, the present invention can design the shift register 14 including the gate pulse modulation circuit (GPM) by the GIP method, thereby reducing the cost.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source drive IC 13: Level shifter
14: shift register 15: printed circuit board

Claims (12)

A clock pulse modulation circuit for modulating the voltage at the falling edge of i-phase clocks whose phases are sequentially delayed (i is a natural number of 3 or more) to a voltage lower than a gate high voltage; And
And a plurality of stages for outputting a gate pulse having a pulse equal to a clock modulated from the clock pulse modulation circuit input through a clock terminal in response to a start voltage or a front carry signal input through the start terminal. The method of claim 1,
The clock pulse modulation circuit,
A first TFT configured to connect a j th clock line and a line supplying a predetermined voltage lower than the gate high voltage in response to a j + 1 th clock signal of a j th +1 (j is a natural number less than i) clock line; And
And a second TFT connecting the gate electrode of the first TFT and the j + 1 th clock line in response to a clock pulse modulation signal of a clock pulse modulation signal supply line. 3. The method of claim 2,
And the predetermined voltage is a gate low voltage. 3. The method of claim 2,
A gate electrode of the first TFT is connected to a source electrode of the second TFT, a source electrode is connected to a line for supplying the predetermined voltage, a drain electrode is connected to the j-th clock line,
A gate electrode of the second TFT is connected to the clock pulse modulation signal supply line, a source electrode is connected to a gate electrode of the first TFT, and a drain electrode is connected to the j + 1 clock line Shift register. 3. The method of claim 2,
The gate pulse,
A shift characterized by rising from a gate low voltage to the gate high voltage during a first rising period, falling to a voltage lower than the gate high voltage during a first falling period, and falling to the gate low voltage during a second falling period; register. Outputs a gate pulse having the same pulse as any one of i (i is a natural number of three or more) phase delays sequentially inputted through the clock terminal in response to a start voltage or a front carry signal input through the start terminal. Multiple stages; And
And a gate pulse modulation circuit for modulating and outputting a voltage at the falling edge of the gate pulse to a voltage lower than a gate high voltage. The method according to claim 6,
The gate pulse modulation circuit,
A first TFT connecting an output line of the m + 1th stage and a line supplying a predetermined voltage lower than the gate high voltage in response to an output of the mth (m is a natural number) stage; And
And a second TFT which connects an output line of the m + 1th stage and a line for supplying the predetermined voltage in response to the output of the m + 2th stage. The method of claim 7, wherein
And the predetermined voltage is a gate low voltage. The method of claim 7, wherein
A gate electrode of the first TFT is connected to an output line of the mth stage, a source electrode is connected to a line supplying the predetermined voltage, a drain electrode is connected to an output line of the m + 1th stage,
A gate electrode of the second TFT is connected to an output line of the m + 2th stage, a source electrode is connected to a line supplying the predetermined voltage, and a drain electrode is connected to an output line of the m + 1th stage And a shift register. The method of claim 7, wherein
The gate pulse,
Rising from a gate low voltage to a voltage lower than the gate high voltage during a first rising period, rising to a gate high voltage during a second rising period, falling to a voltage lower than the gate high voltage during a first falling period, And shifting the gate low voltage during a two polling period. A display panel on which data lines and gate lines are formed;
A data driving circuit converting input digital video data into an analog data voltage and supplying the converted digital video data to the data lines; And
A gate driving circuit sequentially outputting gate pulses synchronized with the data lines to the gate lines,
The gate driving circuit,
A clock pulse modulation circuit for modulating the voltage at the falling edge of i-phase clocks whose phases are sequentially delayed (i is a natural number of 3 or more) to a voltage lower than a gate high voltage; And
A shift register including a plurality of stages for outputting a gate pulse having a pulse equal to a clock modulated from the clock pulse modulation circuit input through a clock terminal in response to a start voltage or a front carry signal input through the start terminal; Display device characterized in that. A display panel on which data lines and gate lines are formed;
A data driving circuit converting input digital video data into an analog data voltage and supplying the converted digital video data to the data lines; And
A gate driving circuit sequentially outputting gate pulses synchronized with the data lines to the gate lines,
The gate driving circuit,
Outputs a gate pulse having the same pulse as any one of i (i is a natural number of three or more) phase delays sequentially inputted through the clock terminal in response to a start voltage or a front carry signal input through the start terminal. Multiple stages; And
And a shift register including a gate pulse modulation circuit for modulating and outputting a voltage at the falling edge of the gate pulse to a voltage lower than a gate high voltage.

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