KR20130101760A - Shift register and display device using the same - Google Patents

Abstract

PURPOSE: A shift register and a display device using the same increase the reliability of the shift register by preventing the degradation of the device characteristics of a thin film transistor (TFT) and the shift of a threshold voltage. CONSTITUTION: A Q node voltage control unit (111) charges a Q node in response to a start signal or a front-end carry signal and discharges the Q node in response to a first logic level voltage of a QB node. A QB node voltage control unit (112) discharges the QB node in response to the start signal or the front-end carry signal and charges the QB node in response to a clock inputted through a reset terminal and a first logic level voltage of a first node. An output unit (114) connects an output node to one of the second logic level voltage terminals receiving a second logic level voltage according to the voltage of the Q node and the QB node.

Description

SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a shift register and a display device using the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, a variety of flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes. For example, various flat panel displays such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) display are utilized.

The display device displays an image using a gate drive circuit for supplying a scan signal to the gate lines of the display panel and a data drive circuit for supplying a data voltage to the data lines. The gate driving circuit directly forms a TAB (Tape Automated Bonding) method for attaching a printed circuit board on which a plurality of gate drive integrated circuits are mounted to a display panel or a gate drive integrated circuit directly on the display panel. The gate drive IC in panel (GIP) can be formed. Compared to the TAB method, the GIP method enables a slimmer display device, which not only increases external aesthetics, but also reduces costs, and provides a plurality of scan signals for compensating the threshold voltage of a driving TFT (thin film transistor) of a pixel. There is an advantage that the display panel maker (Maker) can directly design them. Therefore, recently, the gate drive circuit is formed by the GIP method rather than the TAB method.

In the GIP method, a shift register of a gate driving circuit includes stages that are cascade-connected to sequentially generate scan signals. Each of the stages generates a scan signal by controlling the pull-up TFT and the pull-down TFT. The pull-up TFT is turned on or turned off in accordance with the voltage of the Q node connected to the gate electrode, and the pull-down TFT is turned on or turned off in accordance with the voltage of the QB node connected to the gate electrode.

Meanwhile, in order for each of the stages to be driven with high reliability, the voltages of the Q node and the QB node must be stabilized. Each of the stages includes a plurality of TFTs for controlling the voltages of the Q node and the QB node, and some of the TFTs of the plurality of TFTs are connected to the DC voltage source to control the voltages of the Q node and the QB node. However, when a DC voltage is applied to the TFT for a long time, the TFT may have a problem of deterioration of device characteristics or shift of a threshold voltage due to DC stress. In particular, since the TFT controlling the voltage of the Q node has a direct relationship with the output of the stage, it is necessary to solve the DC stress of the TFT controlling the voltage of the Q node.

The present invention provides a shift register that can increase reliability and a display device using the same.

The shift register according to an embodiment of the present invention includes a plurality of stages that sequentially receive a phase (i is a natural number of two or more) phase clocks of which phase is sequentially delayed, and sequentially generate outputs. A Q node voltage controller configured to charge the Q node in response to an input start signal or a front carry signal and discharge the Q node in response to a first logic level voltage of the QB node; A QB node that discharges the QB node in response to a start signal or a front carry signal input through the start terminal, and charges the QB node in response to a clock input through a reset terminal and a first logic level voltage of a first node Node voltage controller; And an output unit configured to connect an output node to any one of a clock terminal and a second logic level voltage terminal supplied with a second logic level voltage according to the voltages of the Q node and the QB node. The Q node is discharged by connecting the Q node and the output node in response to the first logic level voltage of the QB node.

According to an exemplary embodiment of the present invention, a display device includes: a display panel on which data lines and gate lines are formed; A data driving circuit converting input digital video data into an analog data voltage and supplying the converted digital video data to the data lines; And a gate driving circuit including a shift register configured to sequentially output gate pulses synchronized with the data lines to the gate lines, wherein the shift register has an i (i is a natural number of two or more) in which the phase is sequentially delayed. A plurality of stages that receive clocks and sequentially generate outputs, wherein the stages charge the Q node in response to a start signal or a front carry signal input through a start terminal, and the first logic level of the QB node; A Q node voltage controller configured to discharge the Q node in response to a voltage; A QB node that discharges the QB node in response to a start signal or a front carry signal input through the start terminal, and charges the QB node in response to a clock input through a reset terminal and a first logic level voltage of a first node Node voltage controller; And an output unit configured to connect an output node to any one of a clock terminal and a second logic level voltage terminal supplied with a second logic level voltage according to the voltages of the Q node and the QB node. The Q node is discharged by connecting the Q node and the output node in response to the first logic level voltage of the QB node.

The present invention connects the TFT controlling the discharge of the Q node to the output node of the stage rather than the direct current voltage source. As a result, the present invention can allow the TFT controlling the discharge of the Q node to be freed from the direct current stress. For this reason, the present invention can solve the problem that the device characteristics of the TFTs controlling the discharge of the Q node are deteriorated or the threshold voltage is shifted, thereby increasing the reliability of the shift register. In addition, the present invention can reduce the voltage difference between the source electrode and the drain electrode of the TFT controlling the discharge of the Q node when the Q node is bootstrapping and rises to a voltage higher than the gate high voltage.

1 is a block diagram illustrating a shift register according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage of FIG. 1. FIG.
3 is a waveform diagram illustrating input and output signals of a k-th stage of FIG. 1;
4 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

1 is a block diagram illustrating a shift register according to an exemplary embodiment of the present invention. Referring to FIG. 1, the shift register 14 according to an exemplary embodiment of the present invention includes a plurality of stages ST (1) to ST (n) where n is a natural number of stages. In FIG. 1, for convenience of explanation, only the first to fourth stages ST (1) to ST (4) are illustrated.

In the following description, the "shear stage" refers to being located on top of the stage to be a reference. For example, based on the kth (1 <k <n, k is two or more natural numbers) stages ST (k), the front end stages are the first stage ST (1) to the k-1st stage (ST (k) -1)). The "back stage" refers to being located at the lower part of the stage used as a reference. For example, on the basis of the k-th stage ST (k), the trailing stage indicates any one of the (k + 1) th stages ST (k + 1) to k (n).

The initialization voltage is applied to the initialization voltage line INIL, and the start signal VST is applied to the start signal line VSTL. The start signal VST occurs once at the beginning of one frame period. In addition, the first clock CLK1 is applied to the first clock line CL1, and the second clock CLK2 is applied to the second clock line CL2. In addition, a second logic level voltage is applied to the second logic level voltage line (not shown).

Each of the stages ST (1) to ST (n) has an initialization terminal INI, a start terminal START, a clock terminal CLK, a reset terminal RESET, an output terminal OUT, and a second logic level. And a voltage terminal (not shown). Each of the stages ST (1) to ST (n) is pulled up in response to the start signal VST or the front carry signal input through the start terminal START, and is input through the reset terminal RESET. It pulls down in response to a clock. In particular, each of the stages ST (1) to ST (n) is initialized to enable pull-up in response to an initialization signal INIS input through the initialization terminal INI. Each of the stages ST (1) to ST (n) outputs a scan pulse having the same pulse as the clock inputted through the clock terminal CLK through the output terminal OUT.

The initialization signal INIS is input to the initialization terminal INI of each of the stages ST (1) to ST (n). The initialization signal INIS is generated at the first logic level voltage during the active period of one frame period and is generated at the second logic level voltage during the vertical blank interval. One frame period is divided into an active period and a vertical blank period. The active period is a period in which a valid data voltage is supplied to the pixels of the display panel 10, and the vertical blank period is a rest period.

The start signal VST or the carry signal of the previous stage is input to the start terminal START of each of the stages ST (1) to ST (n). For example, as shown in FIG. 3, the start signal VST of the start signal line VSTL is input to the start terminal START of the first stage ST (1). The output OUT (k-1) of the k-1st stage ST (k-1), which is a carry signal of the preceding stage, is input to the start terminal START of each of the kth stages ST (k).

The clock terminal CLK of each of the stages ST (1) to ST (n) receives a clock of any one of phase clocks of i (i is a natural number of two or more) whose phase is sequentially delayed. The i-phase clocks may be implemented as two-phase clocks CLK1 and CLK2 as shown in FIG. 3. In the embodiment of the present disclosure, for convenience of description, the i-phase clocks have been described as being implemented with the two-phase clocks CLK1 and CLK2, but the present invention is not limited thereto. As shown in FIG. 3, the two-phase clocks CLK1 and CLK2 may be sequentially delayed in every predetermined first period. The predetermined first period may be appropriately implemented within approximately one horizontal period to two horizontal periods. One horizontal period means one line scanning time in which data is written in one line of pixels of the display panel. In addition, the two-phase clocks CLK1 and CLK2 are level shifted from the level shifter 13 to the TTL logic level, thereby swinging between the first and second logic level voltages. In the following description, the first logic level voltage is the gate high voltage VGH and the second logic level voltage is the gate low voltage VGL. The gate low voltage VGL may be set to approximately −7V to −15V, and the gate high voltage VGH may be set to approximately 15V to 30V. In addition, the two-phase clocks CLK1 and CLK2 may be implemented to overlap each other for a predetermined second period.

One of a clock signal is input to the reset terminal RESET of each of the stages ST (1) to ST (n). The clock signal input to the reset terminal RESET of each of the stages ST (1) to ST (n) is input with one of the i-phase clocks. For example, as shown in FIG. 3, the second clock CLK2 is input to the reset terminal RESET of the first stage ST (1), and is reset to the reset terminal RESET of the second stage ST (2). The first clock CLK1 is input. Meanwhile, it should be noted that the clock inputted to the reset terminal RESET of each of the stages ST (1) to ST (n) is a clock whose phase is delayed by at least one phase or more than the clock input to the clock terminal CLK. do.

Each of the stages ST (1) to ST (n) has one output terminal OUT. The outputs OUT (1) to OUT (n) of each of the stages ST (1) to ST (n) have scan signals SP (1) applied to gate lines (or scan lines) of the display panel 10. The signal is outputted to ˜SP (n) and input as a carry signal to the start terminal START of the rear stage. Since each of the stages ST (1) to ST (n) is cascaded, the first stage ST (1) to the nth stage only when the start voltage is supplied to the first stage ST (1). The output occurs sequentially until (ST (n)).

FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage of FIG. 1. Referring to FIG. 2, the k-th stage ST (k) includes a Q node voltage controller 111 for controlling charge and discharge of the Q node Q, and a QB node voltage controller for controlling charge and discharge of the QB node QB. (112), a clock input through the clock terminal CLK according to the voltages of the first node voltage control unit 113, the Q node, and the QB nodes Q and QB, which control charging and discharging of the first node N1. The output unit 114 for outputting, the initialization unit 115 initialized for charging the Q node Q and discharging the QB node QB, and the first to fourth capacitors C1, C2, C3, and C4. Equipped.

The Q node voltage controller 111 charges the Q node Q in response to a signal input through the initialization terminal INI and the start terminal START, and Q in response to a signal input through the reset terminal RESET. The node Q is discharged. The Q node voltage controller 111 includes first and second thin film transistors (T1, T2).

The first TFT T1 serves to control the charging of the Q node Q. The first TFT T1 charges the Q node Q to the gate high voltage VGH in response to the start signal VST or the front carry signal input through the start terminal START. An eighth TFT T8 may be connected between the first TFT T1 and the Q node Q to initialize the charging of the Q node Q. FIG. The gate electrode and the drain electrode of the first TFT T1 are connected to the start terminal START, and the source electrode is connected to the drain electrode of the eighth TFT T8. The second TFT T2 serves to control the discharge of the Q node Q.

The second TFT T2 discharges the Q node Q in response to the gate high voltage VGH of the QB node QB. The gate electrode of the second TFT T2 is connected to the QB node QB, the source electrode is connected to the output node NO, and the drain electrode is connected to the Q node Q.

The QB node voltage controller 112 discharges the QB node QB in response to the signal input through the start terminal START and charges the QB node QB in response to the signal input through the reset terminal RESET. . The QB node voltage controller 112 includes third to fifth TFTs T3, T4, and T5.

The third TFT T3 serves to control the discharge of the QB node QB. The third TFT T3 connects the QB node QB to the gate low voltage terminal VGLT in response to the start signal VST or the front carry signal. As a result, the QB node QB is discharged to the gate low voltage VGL. A ninth TFT T9 may be connected between the third TFT T3 and the start terminal START to initialize the discharge of the QB node QB. The gate electrode of the third TFT T3 is connected to the source electrode of the ninth TFT T9, the source electrode is connected to the gate low voltage terminal VGLT, and the drain electrode is connected to the QB node QB.

The fourth and fifth TFTs T4 and T5 serve to control the discharge of the QB node QB. The fourth TFT T4 connects the QB node QB and the reset terminal RESET in response to one of the i-phase clocks input through the reset terminal RESET. When the clock of the gate high voltage VGH is applied through the reset terminal RESET, the QB node QB is charged to the gate high voltage VGH. The fifth TFT T5 may be connected between the gate electrode and the drain electrode of the fourth TFT T4. The gate electrode of the fourth TFT T4 is connected to the reset terminal RESET, the source electrode is connected to the QB node QB, and the drain electrode is connected to the source electrode of the fifth TFT T5. The fifth TFT T5 connects the gate electrode and the source electrode of the fourth TFT T4 in response to the gate high voltage VGH of the first node N1. The gate electrode of the fifth TFT T5 is connected to the first node N1, the source electrode is connected to the drain electrode of the fourth TFT T4, and the drain electrode is connected to the gate electrode of the fourth TFT T4. do. Therefore, the QB node QB is charged to the gate high voltage VGH only when the fourth and fifth TFTs T4 and T5 are turned on.

The first node N1 voltage controller 113 charges the first node N1 in response to a clock input through the clock terminal CLK, and starts the start signal VST or the input signal through the start terminal START. The first node N1 is discharged in response to the front carry signal. The first node voltage controller 113 includes sixth and seventh TFTs T6 and T7.

The sixth TFT T6 serves to control the charging of the first node N1. The sixth TFT T6 connects the first node N1 to the clock terminal CLK in response to a clock input through the clock terminal CLK. The gate electrode and the drain electrode of the sixth TFT T6 are connected to the clock terminal CLK, and the source electrode is connected to the first node N1.

The seventh TFT T7 serves to control the discharge of the first node N1. The seventh TFT T7 connects the first node N1 to the gate low voltage terminal VGLT in response to the start signal VST or the front carry signal. As a result, the first node N1 is discharged to the gate low voltage VGL. A ninth TFT T9 may be connected between the seventh TFT T7 and the start terminal START. The gate electrode of the seventh TFT T7 is connected to the source electrode of the ninth TFT T9, the source electrode is connected to the gate low voltage terminal VGLT, and the drain electrode is connected to the first node N1.

The output unit 114 connects the output terminal OUT to the clock terminal CLK or the gate low voltage terminal VGLT according to the voltages of the Q node Q and the QB node QB. The output section 114 includes a pull-up TFT (TU) and a pull-down TFT (TD).

The pull-up TFT TU connects the clock terminal CLK to the output node NO in response to the gate high voltage VGH of the Q node. For this reason, the clock input through the clock terminal CLK is output to the output terminal OUT. The gate electrode of the pull-up TFT TU is connected to the Q node Q, the source electrode is connected to the output node NO, and the drain electrode is connected to the clock terminal CLK.

The pull-down TFT TD connects the gate low voltage terminal VGLT to the output node NO in response to the gate high voltage VGH of the QB node QB. As a result, the gate low voltage VGL is output to the output terminal OUT. The gate electrode of the pull-down TFT TD is connected to the QB node QB, the source electrode is connected to the gate low voltage terminal VGLT, and the drain electrode is connected to the output node NO.

The initialization unit 115 turns on the eighth TFT T8 so that the Q node Q can be charged in response to the initialization signal INIS input through the initialization terminal INI, and the QB node QB. And the ninth TFT T9 are turned on so that the first node N1 can be discharged. The initialization unit 115 includes eighth and ninth TFTs T8 and T9.

The eighth TFT T8 controls the initialization for the Q node Q charging. The eighth TFT T8 supplies the start node VST or the front carry signal input through the start terminal START to the Q node Q in response to the initialization signal INIS input through the initialization terminal INI. do. The gate electrode of the eighth TFT T8 is connected to the initialization terminal INI, the source electrode is connected to the Q node Q, and the drain electrode is connected to the source electrode of the first TFT T1.

The ninth TFT T9 controls the initialization for discharging the QB node QB and the first node N1. The ninth TFT T9 receives the start signal VST or the front carry signal input through the start terminal START in response to the initialization signal INIS input through the initialization terminal INI. It supplies to the gate electrode of T3, T7. The gate electrode of the ninth TFT T9 is connected to the initialization terminal INI, the source electrode is connected to the gate electrodes of the third and seventh TFTs T3 and T7, and the drain electrode is connected to the start terminal START. do.

The first capacitor C1 is connected between the Q node Q and the output node NO. When the clock of the gate high voltage VGH is input to the output node NO through the clock terminal CLK, the first capacitor C1 further increases the voltage of the Q node Q by bootstrapping. . The second capacitor C2 is connected between the QB node QB and the gate low voltage terminal VGLT, and serves to keep the voltage of the QB node QB constant. The third capacitor C3 is connected between the Q node Q and the gate low voltage terminal VGLT, and serves to keep the voltage of the Q node Q constant. The fourth capacitor C4 is connected between the first node N1 and the gate low voltage terminal VGLT, and serves to keep the voltage of the first node N1 constant.

The semiconductor layers of the first through ninth TFTs (T1, T2, T3, T4, T5, T6, T7, T8, T9), pull-up TFT (TU), and pull-down TFT (TD) are a-Si. , Poly-Si, or oxide semiconductor. 2, the first through ninth TFTs (T1, T2, T3, T4, T5, T6, T7, T8, T9), pull-up TFT (TU), and pull-down TFT (TD) are N Although described with reference to the implementation of the type MOS-FET, the present invention is not limited thereto, and may also be implemented as a P-type MOS-FET. However, the first through ninth TFTs (T1, T2, T3, T4, T5, T6, T7, T8, T9), pull-up TFT (TU), and pull-down TFT (TD) are P-type MOS- If implemented in a FET, the signals of Figure 3 will have to be modified to suit the characteristics of the P-type MOS-FET.

3 is a waveform diagram illustrating input and output signals of a k-th stage of FIG. 1. 3 shows a carry signal of the start signal VST or the k-1st stage ST (k-1) input to the start terminal START of the kth stage ST (k). 3 shows the two-phase clocks CLK1 and CLK2 and the k-th output signal OUT (k) output from the k-th stage ST (k). 3 shows the voltage VQ of the Q node Q of the k-th stage ST (k) and the voltage VQB of the QB node QB.

Hereinafter, the operation of the k-th stage ST (k) during the first to fourth periods t1, t2, t3, and t4 in the forward mode will be described in detail with reference to FIGS. 2 and 3. The first clock CLK1 is input to the clock terminal CLK of the k-th stage ST (k), and the second clock CLK2 is input to the reset terminal RESET. In addition, a description will be given based on the input of the initialization signal INIS of the gate high voltage VGH to the initialization terminal INI during the first to fourth periods t1, t2, t3, and t4. As described with reference to FIG. 1, the initialization signal INIS is generated at the gate high voltage VGH during the active period and is generated at the gate low voltage VGL during the vertical blank period.

First, during the first period t1, the start terminal START outputs the start signal VST of the gate high voltage VGH or the output OUT (k-1) of the k-1 stage, which is a front carry signal. The first clock CLK1 of the gate low voltage VGL is input to the clock terminal CLK, and the second clock CLK2 of the gate high voltage VGH is input to the reset terminal RESET.

The eighth and ninth TFTs T8 and T9 are turned on by the initialization signal INIS of the gate high voltage VGH supplied through the initialization terminal INI. The first, third, and sixth TFTs T1, T3, and T6 are the start signal VST of the gate high voltage VGH supplied through the start terminal START, or the output OUT of the k-1 stage. k-1)). The fourth TFT T4 is turned on by the second clock CLK2 of the gate high voltage VGH supplied through the reset terminal RESET. The seventh TFT T7 is turned off by the first clock CLK1 of the gate low voltage VGL supplied through the clock terminal CLK.

Due to the turn-on of the first and eighth TFTs T1 and T8, the Q node Q is charged to the gate high voltage VGH. Due to the turn-on of the third and ninth TFTs T3 and T9, the QB node QB is discharged to the gate low voltage VGL. Due to the turn-on of the sixth and ninth TFTs T6 and T9 and the turn-off of the seventh TFT T7, the first node N1 is discharged to the gate low voltage VGL. Since the fifth TFT T5 is turned off by the gate low voltage VGL of the first node N1, the gate electrode and the drain electrode of the fourth TFT T4 are disconnected.

The pull-up TFT TU is turned on by the gate high voltage VGH of the Q node Q to connect the clock terminal CLK and the output node NO. The pull-down TFT TD is turned off by the gate low voltage VGL of the QB node QB to block the connection between the gate low voltage terminal VGLT and the output node NO. Accordingly, since the first clock CLK1 of the gate low voltage VGL is applied to the output node NO during the first period t1, the output OUT (1) of the first stage ST (1) is applied. It occurs at the gate low voltage VGL.

Secondly, during the second period t2, the start terminal START has an output OUT (k-1) of the k-1 stage, which is the start signal VST of the gate low voltage VGL or the front carry signal. The first clock CLK1 of the gate high voltage VGH is input to the clock terminal CLK, and the second clock CLK2 of the gate low voltage VGL is input to the reset terminal RESET.

The eighth and ninth TFTs T8 and T9 are turned on by the initialization signal INIS of the gate high voltage VGH supplied through the initialization terminal INI. The seventh TFT T7 is turned on by the first clock CLK1 of the gate high voltage VGH supplied through the clock terminal CLK. The first, third, and sixth TFTs T1, T3, and T6 have a start signal VST of the gate low voltage VGL supplied through the start terminal START, or an output OUT of the k-1th stage. k-1)). The fourth TFT T4 is turned off by the second clock CLK2 of the gate low voltage VGL supplied through the reset terminal RESET.

Due to the turn-off of the sixth TFT T6 and the turn-on of the seventh TFT T7, the first node N1 is charged to the gate high voltage VGH. Since the fifth TFT T5 is turned on by the gate high voltage VGH of the first node N1, the gate electrode and the drain electrode of the fourth TFT T4 are connected. Due to the turn-off of the first TFT T1, the gate high voltage VGH is no longer supplied to the Q node Q, but the Q node Q is connected to the gate high voltage by the third capacitor C3. VGH). Due to the turn-off of the third TFT T3, the gate low voltage VGL is no longer supplied to the QB node QB, but the QB node QB is connected to the gate low voltage by the second capacitor C2. VGL).

The pull-up TFT TU is turned on by the gate high voltage VGH of the Q node Q to connect the clock terminal CLK and the output node NO. The pull-down TFT TD is turned off by the gate low voltage VGL of the QB node QB to block the connection between the gate low voltage terminal VGLT and the output node NO. Therefore, the output OUT (k) of the k-th stage ST (k) is generated at the gate high voltage VGH during the second period t2. Meanwhile, since the second clock CLK2 of the gate high voltage VGH is applied to the output node NO during the second period t2, the Q node Q is bootstrapping by the first capacitor C1. And rises to a voltage VGH 'at a level higher than the gate high voltage VGH.

Third, the output terminal OUT (k-1) of the k-1 stage, which is the start signal VST of the gate low voltage VGL or the front carry signal, is applied to the start terminal START during the third period t3. The first clock CLK1 of the gate low voltage VGL is input to the clock terminal CLK, and the second clock CLK2 of the gate high voltage VGH is input to the reset terminal RESET.

The eighth and ninth TFTs T8 and T9 are turned on by the initialization signal INIS of the gate high voltage VGH supplied through the initialization terminal INI. The fourth TFT T4 is turned on by the second clock CLK2 of the gate high voltage VGH supplied through the reset terminal RESET. The first, third, and sixth TFTs T1, T3, and T6 have a start signal VST of the gate low voltage VGL supplied through the start terminal START, or an output OUT of the k-1th stage. k-1)). The seventh TFT T7 is turned off by the first clock CLK1 of the gate low voltage VGL supplied through the clock terminal CLK.

Since the sixth and seventh TFTs T6 and T7 are turned off, the first node N1 maintains the gate high voltage VGH by the fourth capacitor C4. Since the fifth TFT T5 is turned on by the gate high voltage VGH of the first node N1, the gate electrode and the drain electrode of the fourth TFT T4 are connected. Due to the turn-on of the fourth and fifth TFTs T4 and T5, the QB node QB is charged to the gate high voltage VGH.

The pull-down TFT TD is turned on by the gate high voltage VGH of the QB node QB to connect the gate low voltage terminal VGLT and the output node NO. Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the gate low voltage VGL. The second TFT T2 is turned on by the gate high voltage VGH of the QB node QB to connect the Q node Q and the output node NO. Due to the turn-on of the second TFT T2, the Q node Q is discharged to the gate low voltage VGL. The pull-up TFT TU is turned off by the gate low voltage VGL of the Q node Q to block the connection between the clock terminal CLK and the output node NO. Therefore, the output OUT (k) of the k-th stage ST (k) is generated as the gate low voltage VGL during the third period t3.

Fourth, during the fourth period t4, the start terminal START has the start signal VST of the gate low voltage VGL or the output OUT (k-1) of the k-1 stage, which is the front carry signal. The first clock CLK1 of the gate high voltage VGH is input to the clock terminal CLK, and the second clock CLK2 of the gate low voltage VGL is input to the reset terminal RESET.

The eighth and ninth TFTs T8 and T9 are turned on by the initialization signal INIS of the gate high voltage VGH supplied through the initialization terminal INI. The seventh TFT T7 is turned on by the first clock CLK1 of the gate high voltage VGH supplied through the clock terminal CLK. The first, third, and sixth TFTs T1, T3, and T6 have a start signal VST of the gate low voltage VGL supplied through the start terminal START, or an output OUT of the k-1th stage. k-1)). The fourth TFT T4 is turned off by the second clock CLK2 of the gate low voltage VGL supplied through the reset terminal RESET.

Due to the turn-off of the sixth TFT T6 and the turn-on of the seventh TFT T7, the first node N1 is charged to the gate high voltage VGH. Since the fifth TFT T5 is turned on by the gate high voltage VGH of the first node N1, the gate electrode and the drain electrode of the fourth TFT T4 are connected. Due to the turn-off of the fourth TFT T4, the gate high voltage VGH is no longer supplied to the QB node QB, but the QB node QB is connected to the gate high voltage by the second capacitor C2. VGH). Since the second TFT T2 is turned on by the gate high voltage VGH of the QB node QB, the Q node Q maintains a connection with the output node NO.

The pull-down TFT TD is turned on by the gate high voltage VGH of the QB node QB to connect the gate low voltage terminal VGLT and the output node NO. The pull-up TFT TU is turned off by the gate low voltage VGL of the Q node Q to block the connection between the clock terminal CLK and the output node NO. Accordingly, the output OUT (k) of the kth stage ST (k) is generated as the gate low voltage VGL during the fourth period t4.

Since the operation of the k-th stage ST (k) is repeated as described in the third and fourth periods t3 and t4 during the remaining active period, the description thereof will be omitted.

As described above, the present invention connects the second TFT T2 for controlling the discharge of the Q node to the output node NO of the stage, not the DC voltage source. In particular, since the size of the second TFT T2 is smaller than that of the pull-down TFT TD connected to the gate low voltage terminal VGLT, the second TFT T2 is more resistant to DC stress than the pull-down TFT TD. be sensitive. Therefore, the present invention can solve the problem of deteriorating the device characteristics of the TFT or shifting the threshold voltage by removing the second TFT T2 from the direct current stress, thereby increasing the reliability of the shift register.

Further, since the second TFT T2 is connected to the Q node Q, the source is compared with the third and sixth TFTs T3 and T6 connected to the gate low voltage terminal VGLT due to the bootstrapping effect of the Q node. The voltage difference between the electrode and the drain electrode can be large. In this case, the gate insulating film or the protective film may be destroyed in the second TFT T2 due to the voltage difference between the source electrode and the drain electrode. Therefore, since the gate high voltage VGH is applied from the output node NO of the stage when the Q node Q rises to the voltage VGH 'higher than the gate high voltage VGH by bootstrapping, The voltage difference between the source electrode and the drain electrode of the two TFTs T2 can be reduced.

4 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention. Referring to FIG. 4, the display device according to the exemplary embodiment includes a display panel 10, a data driving circuit, a gate driving circuit, a timing controller 11, and the like.

The display device according to an embodiment of the present invention may include any display device that sequentially supplies gate pulses (or scan pulses) to the gate lines (or scan lines) to write digital video data to the pixels by line sequential scanning. have. For example, a display device according to an embodiment of the present invention includes a liquid crystal display (LCD), an organic light emitting diode display (OLED), and a field emission display (FED). The electrophoretic display device may be implemented as one of electrophoresis (EPD). Although the present invention has been exemplified in the following embodiments with the display device implemented as a liquid crystal display device, it should be noted that the display device of the present invention is not limited to the liquid crystal display device. The liquid crystal display may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display.

In the display panel 10, a liquid crystal layer is formed between two substrates. The lower substrate of the display panel 10 has data lines, gate lines crossing the data lines, TFTs formed at intersections of the data lines and the gate lines, and are connected to the TFTs by an electric field between the pixel electrode and the common electrode. A TFT array including liquid crystal cells to be driven, a storage capacitor, and the like is formed. A color filter array including a black matrix and a color filter is formed on the upper substrate of the display panel 10. The liquid crystal display according to the exemplary embodiment of the present invention may also be implemented in a liquid crystal mode such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, or fringe field switching (FFS). The common electrode may be formed on the upper substrate in the vertical electric field driving method such as the TN mode and the VA mode, and may be formed on the lower substrate together with the pixel electrode in the horizontal electric field driving method such as the IPS mode and the FFS mode. Polarizing plates having optical axes orthogonal to each other are attached to the upper substrate and the lower substrate of the display panel 10, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal layer.

The data drive circuit includes a plurality of source drive ICs 12. [ The source drive ICs 12 receive the digital video data DATA from the timing controller 11. Each of the source drive ICs 12 converts the digital video data DATA into a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, and synchronizes the data voltage with a gate pulse. The data lines of the display panel 10 are supplied to each other. The source drive ICs 12 may be connected to data lines of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driving circuit includes a level shifter 13 and a shift register 14. The level shifter 13 level shifts the TTL (Logic-Transistor-Logic) logic level voltage of the clocks CLKs input from the timing controller 11 to the gate high voltage VGH and the gate low voltage VGL. The level shifted clocks CLKs are input to the shift register 14. The shift register 14 is connected to the gate lines of the display panel 10 to sequentially output gate pulses to the gate lines. The shift register 14 is directly formed on the lower substrate of the display panel 10 by a gate drive-IC in panel (GIP) method. In the GIP method, the level shifter 13 is mounted on a printed circuit board 15.

The timing controller 11 receives digital video data RGB from an external host system through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 11 transmits digital video data DATA input from the host system to the source drive ICs 12. In addition, the timing controller 11 receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a main clock, and the like from the host system through an LVDS or TMDS interface receiving circuit. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host system. The timing control signals include a gate timing control signal for controlling the operation timing of the gate driving circuit, and a data timing control signal DCS for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes a start voltage and clocks CLKs sequentially generated on i (i is a natural number of 3 or more). The start voltage is input to the shift register 14 to control the shift start timing of the shift register 14. The clocks CLKs are input to the level shifter 13, level shifted, and then input to the shift register 14, and are used as clock signals for shifting the start voltage.

The data timing control signal DCS includes a source start pulse, a source sampling clock, a polarity control signal, a source output enable signal, and the like. The source start pulse controls the shift start timing of the source drive ICs 12. The source sampling clock is a clock signal that controls the sampling timing of data in the source drive ICs 12 based on the rising or falling edge. The polarity control signal controls the polarity of the data voltage output from the source drive ICs 12. If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source drive IC 13: Level shifter
14: shift register 15: printed circuit board
111: Q node voltage control unit 112: QB node voltage control unit
113: first node voltage controller 114: output unit
115: initialization unit

Claims (11)

It is provided with a plurality of stages that sequentially receive the i (i is a natural number of two or more) phase clocks of which the phase is delayed in sequence,
The stage includes:
A Q node voltage controller configured to charge the Q node in response to a start signal or a front carry signal input through a start terminal and to discharge the Q node in response to a first logic level voltage of the QB node;
A QB node that discharges the QB node in response to a start signal or a front carry signal input through the start terminal, and charges the QB node in response to a clock input through a reset terminal and a first logic level voltage of a first node Node voltage controller; And
An output unit connecting an output node to any one of a clock terminal and a second logic level voltage terminal supplied with a second logic level voltage according to the voltages of the Q node and the QB node,
The Q node voltage control unit,
Shifting the Q node and an output node in response to a first logic level voltage of the QB node to discharge the Q node. The method of claim 1,
The stage includes:
An initialization unit for initializing the Q node and discharging the QB node during an active period in response to an initialization signal input through an initialization terminal; And
And a first node voltage controller configured to charge the first node in response to a clock input through the clock terminal, and discharge the first node in response to a start signal or a front carry signal input through the start terminal. And a shift register. 3. The method of claim 2,
The Q node voltage control unit,
A first TFT connecting the Q node and the start terminal in response to a start signal or a front carry signal input through the start terminal; And
And a second TFT connecting the Q node and the output node in response to the voltage of the QB node. The method of claim 3, wherein
The QB node voltage control unit,
A third TFT configured to connect the QB node and a second logic level voltage terminal in response to a start signal or a front carry signal input through the start terminal;
A fourth TFT connecting the QB node and a reset terminal in response to a clock input through the reset terminal; And
And a fifth TFT connecting the gate electrode and the drain electrode of the fourth TFT in response to a first logic level voltage of the first node. 5. The method of claim 4,
The first node voltage control unit,
A sixth TFT connecting the first node and a second logic level voltage terminal in response to a start signal or a front carry signal input through the start terminal; And
And a seventh TFT connecting the first node and a clock terminal in response to a clock input through the clock terminal. The method of claim 5, wherein
The initialization unit,
An eighth TFT connecting the Q node and the first TFT in response to an initialization signal input through the initialization terminal; And
And a ninth TFT connecting the start terminal to the gate electrodes of the third and sixth TFTs in response to an initialization signal input through the initialization terminal. The method according to claim 6,
The output unit includes:
A pull-up TFT connecting the clock terminal and an output node in response to the voltage of the Q node; And
And a pull-down TFT connecting the second logic level voltage terminal and an output node in response to the voltage of the QB node. The method of claim 1,
And a clock input to the reset terminal is a clock whose phase is delayed by at least one or more phases than a clock input to the clock terminal. The method of claim 1,
And the first logic level voltage is higher than the second logic level voltage. The method of claim 1,
The stage includes:
A first capacitor connected between the Q node and the output node;
A second capacitor connected between the QB node and the second logic level voltage terminal to maintain a constant voltage of the QB node;
A third capacitor connected between the Q node and the second logic level voltage terminal to maintain a constant voltage of the Q node; And
And a fourth capacitor connected between the first node and the second logic level voltage terminal to maintain a constant voltage of the first node. A display panel on which data lines and gate lines are formed;
A data driving circuit converting input digital video data into an analog data voltage and supplying the converted digital video data to the data lines; And
A gate driving circuit including a shift register configured to sequentially output gate pulses synchronized with the data lines to the gate lines,
The shift register includes a plurality of stages that sequentially receive outputs of i (i is a natural number of two or more) phase clocks whose phases are sequentially delayed, and sequentially generate outputs.
The stage includes:
A Q node voltage controller configured to charge the Q node in response to a start signal or a front carry signal input through a start terminal and to discharge the Q node in response to a first logic level voltage of the QB node;
A QB node that discharges the QB node in response to a start signal or a front carry signal input through the start terminal, and charges the QB node in response to a clock input through a reset terminal and a first logic level voltage of a first node Node voltage controller; And
An output unit connecting an output node to any one of a clock terminal and a second logic level voltage terminal supplied with a second logic level voltage according to the voltages of the Q node and the QB node,
The Q node voltage control unit,
And discharging the Q node by connecting the Q node and the output node in response to a first logic level voltage of the QB node.

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