KR101773193B1 - Active Matrix Display - Google Patents

Abstract

The present invention relates to an active matrix display device capable of rapidly removing a ripple component of a common voltage to improve picture quality.
The active matrix display device includes at least one first common line connecting common electrodes of liquid crystal cells being charged; A plurality of second common lines connecting common electrodes of uncharged liquid crystal cells; A first bus line to which a first common voltage is applied; A second bus line to which a second common voltage is applied; And a scan driver for sequentially generating scan pulses in accordance with a time point of data application to the liquid crystal cells and switching current paths between the first bus line and the first common line, The first common line is applied to the first common line, and the current path between the second common line and the second common line is switched, And a gate driving circuit for applying the second common voltage to the gate driving circuit.

Description

[0001] Active Matrix Display [

The present invention relates to an active matrix display device capable of rapidly removing a ripple component of a common voltage to improve picture quality.

A display device of an active matrix driving system displays a moving image by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. As such an active matrix display device, a liquid crystal display is typically used.

The liquid crystal display includes pixel electrodes to which a data voltage is applied, and common electrodes which are opposite to the pixel electrodes and to which a common voltage is applied. The liquid crystal cells are driven by a potential difference between the pixel electrode and the common electrode.

The common electrodes are supplied with a common voltage Vcom through internal common lines VCL1 parallel to the gate lines and external common lines VCL2 connected in parallel with the internal common lines VCL1 as shown in FIG. Since the internal common lines VCL1 are coupled to the signal lines (data lines and gate lines, etc.) of the panel via the parasitic capacitors, the common voltage Vcom on the internal common lines VCL1 is the data voltage and / It is affected by the gate voltage (scan pulse). That is, when the scan pulse SCAN or the data voltage Vdata fluctuates, the common voltage Vcom can not be maintained at a constant DC level, but is swung as shown in FIG. The ripple component of this common voltage Vcom adversely affects the charging characteristics of the pixel and must be rapidly attenuated. However, in the conventional liquid crystal display device, since the ripple components of the common voltage Vcom due to the voltage fluctuation are discharged simultaneously through the single common external line VCL2, the attenuation rate of the actual ripple components is very slow. When the common voltage Vcom varies due to the ripple components, uneven charging, horizontal stripes, and the like may occur.

A method may be considered in which the line width of the common lines VCL1 and VCL2 is reduced by increasing the line width in order to further speed up the attenuation of the ripple components. However, the line width of the common lines (VCL1, VCL2) can not be expanded indefinitely under all circumstances, and the ripple components are not attenuated as satisfactorily even if the line width is greatly enlarged.

It is therefore an object of the present invention to provide an active matrix display device capable of rapidly removing a ripple component of a common voltage to improve image quality.

According to an aspect of the present invention, there is provided an active matrix display device including: at least one first common line connecting common electrodes of liquid crystal cells being charged; A plurality of second common lines connecting common electrodes of uncharged liquid crystal cells; A first bus line to which a first common voltage is applied; A second bus line to which a second common voltage is applied; And a scan driver for sequentially generating scan pulses in accordance with a time point of data application to the liquid crystal cells and switching current paths between the first bus line and the first common line, The first common line is applied to the first common line, and the current path between the second common line and the second common line is switched, And a gate driving circuit for applying the second common voltage to the gate driving circuit.

A display region in the display panel is defined by the liquid crystal cells; The gate driving circuit is embedded in a non-display area of the display panel located outside the display area.

A pull-up transistor connected between an input terminal of the gate shift clock signal and the output node and applying the scan pulse of the turn-on level to the output node according to the potential of the Q node; A pull-down transistor connected between the output node and the input terminal of the low-potential driving voltage, for applying the scan pulse of the turn-off level to the output node according to the potential of the QB node having the opposite potential to the Q node; A first switch element for switching a current path between the first bus line and the first common line according to a potential of the Q node; And a second switch element for switching a current path between the second bus line and the second common line according to the potential of the QB node.

The gate driving circuit includes a third switch element connected to be diode-connected between the Q node and the gate terminal of the first switch element; And a fourth switch element for applying the low potential driving voltage to the gate terminal of the first switch element in accordance with the potential of the QB node.

A pull-up transistor connected between an input terminal of the gate shift clock signal and the output node and applying the scan pulse of the turn-on level to the output node according to the potential of the Q node; A pull-down transistor connected between the output node and the input terminal of the low-potential driving voltage, for applying the scan pulse of the turn-off level to the output node according to the potential of the QB node having the opposite potential to the Q node; A first switch element for switching a current path between the first bus line and the first common line according to a potential of the output node; And a second switch element for switching a current path between the second bus line and the second common line according to the potential of the QB node.

The gate driving circuit includes a third switch element connected to be diode-connected between the output node and the gate terminal of the first switch element; And a fourth switch element for applying the low potential driving voltage to the gate terminal of the first switch element in accordance with the potential of the QB node.

A pull-up transistor connected between an input terminal of the gate shift clock signal and the output node and applying the scan pulse of the turn-on level to the output node according to the potential of the Q node; A pull-down transistor connected between the output node and the input terminal of the low-potential driving voltage, for applying the scan pulse of the turn-off level to the output node according to the potential of the QB node having the opposite potential to the Q node; A third switch element for applying the gate shift clock signal or the high potential driving voltage to the first node according to the potential of the Q node; A first switch element for switching a current path between the first bus line and the first common line according to a potential of the first node; A second switch element for switching a current path between the second bus line and the second common line according to a potential of the QB node; And a fourth switch element for applying the low potential driving voltage to the first node according to the potential of the QB node.

The active matrix display device further includes a power supply circuit for generating the first common voltage to supply the first common voltage to the first bus line and generating the second common voltage to supply the second common voltage to the second bus line.

The power supply circuit generates the first common voltage and the second common voltage at the same level or at different levels.

Wherein the power supply circuit fixes the second common voltage at a constant level; And swings the first common voltage between a first level higher than the second common voltage and a second level lower than the second common voltage for a predetermined period.

The active matrix display device according to the present invention includes a first common line connecting common electrodes of liquid crystal cells being charged to a first bus line by using a gate driving circuit and a second common line connecting common electrodes of uncharged liquid crystal cells 2 common lines to the second bus line using a gate drive circuit. Accordingly, by making the discharge path of the ripple component existing on the first common line different from the discharge path of the ripple component existing on the second common lines, the present invention rapidly removes the ripple component on the first common line, , Stripes in the horizontal direction, and the like can be prevented, and the image quality can be greatly improved.

1 is a view showing a connection configuration of a conventional common line;
2 shows a ripple component of a common voltage;
FIG. 3 is a view showing ripple components of a common voltage in a conventional liquid crystal display device discharged through a single external common line; FIG.
4 is a view showing an active matrix display device according to an embodiment of the present invention.
5 is a view schematically showing a connection configuration of a common line according to an embodiment of the present invention;
6 is a view showing an array of a liquid crystal display panel with a built-in gate driving circuit.
Fig. 7 is a view showing a first embodiment of the n-th unit shown in Fig. 6; Fig.
FIG. 8 is a view showing a simulation result waveform for FIG. 7; FIG.
Fig. 9 is a view showing a second embodiment of the n-th unit shown in Fig. 6; Fig.
Fig. 10 is a view showing a third embodiment of the n-th unit shown in Fig. 6; Fig.
Fig. 11 is a view showing a fourth embodiment of the n-th unit shown in Fig. 6; Fig.
12 is a diagram showing a simulation result waveform for FIG. 11. FIG.
Fig. 13 is a view showing a fifth embodiment of the n-th unit UNT (n) shown in Fig. 6; Fig.
FIGS. 14 and 15 are diagrams showing waveforms of simulation results for FIG. 11. FIG.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 4 to 15. FIG.

4 illustrates an active matrix display device according to an embodiment of the present invention.

Referring to FIG. 4, an active matrix display device according to an embodiment of the present invention is implemented as a liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a power supply circuit 14.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 10 includes a plurality of liquid crystal cells Clc arranged in a matrix form by an intersection structure of a plurality of data lines DL and a plurality of gate lines GL.

The pixel electrodes 1 and the pixel electrodes 1 connected to the data lines DL, the gate lines GL, the TFTs and the TFTs are formed on the lower glass substrate of the liquid crystal display panel 10, Common electrodes 2 for driving liquid crystal cells Clc, and the like are formed. The common electrodes 2 are connected to the common line CL and can form a storage on common storage capacitor Cst in the pixel array.

On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, and the like are formed.

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate whose optical axis is orthogonal is attached, and an alignment film for setting a pre-tilt angle of liquid crystal is formed at an interface with the liquid crystal.

The timing controller 11 arranges the input digital video data RGB in accordance with the resolution of the liquid crystal display panel 10 and supplies the data to the data driving circuit 12.

The timing controller 11 receives the timing signals such as the vertical / horizontal synchronizing signals Vsync and Hsync, the data enable signal DE and the dot clock signal DCLK to control the operation timing of the data driving circuit 12 And a gate control signal (GDC) for controlling the operation timing of the data driving control signal (DDC) and the gate driving circuit (13). The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock signal CLK, a gate output enable signal GOE, and the like. The data timing control signal DDC includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, and a source output enable signal SOUT, SOE).

The data driving circuit 12 latches the digital video data RGB under the control of the timing controller 11 and then converts the latched data into analog positive and negative polarity data voltages and supplies them to the data lines DL .

The gate driver circuit 13 generates a scan pulse under the control of the timing controller 11 and sequentially supplies the scan pulses to the gate lines GL. The gate driving circuit 13 supplies the first common voltage Vcom1 to the common line CL arranged on the horizontal line where the charging operation is activated by the scan pulse and supplies the first common voltage Vcom1 to the horizontal lines And supplies the second common voltage Vcom2 to the disposed common line CL.

The gate drive circuit 13 includes a level shift and a gate shift register. The level shifter level shifts the TTL (Transistor-Transistor-Logic) logic level voltage of the gate shift clocks (CLK) of at least two phases inputted from the timing controller 11 to the gate high voltage and the gate low voltage. The gate shift register is composed of a plurality of units that sequentially shift the gate start pulse (GSP) in accordance with the gate shift clock (CLK) and sequentially output the scan pulse. The gate driving circuit 13 may be formed directly on the lower substrate of the liquid crystal display panel 10 by a GIP (Gate In Panel) method. In the GIP system, the level shifter is mounted on the control PCB (not shown) together with the timing controller 11, and the gate shift register is embedded on the lower substrate of the liquid crystal display panel 10. [ Hereinafter, it will be described that the gate drive circuit 13 is embedded in the GIP scheme for the convenience of explanation, but it should be noted that the gate shift register is correctly embedded in the GIP scheme.

The power supply circuit 14 generates the first common voltage Vcom1 and the second common voltage Vcom2. The power supply circuit 14 supplies the first common voltage Vcom1 to the gate drive circuit 13 through the first bus wiring and supplies the second common voltage Vcom2 to the gate drive circuit 13). The power supply circuit 14 may generate the first common voltage Vcom1 and the second common voltage Vcom2 at the same level or may occur at different levels. When the first common voltage Vcom1 and the second common voltage Vcom2 are generated at different levels, the power supply circuit 14 can swing the first common voltage Vcom1 at regular intervals. For example, the power supply circuit 14 fixes the second common voltage Vcom2 at a constant level, and during the nth (n is a positive integer) frame period, the first common voltage Vcom1 is higher than the second common voltage Vcom2 And the first common voltage Vcom1 may be generated at a second level lower than the second common voltage Vcom2 during the (n + 1) -th frame period. On the other hand, when the liquid crystal display panel 10 is driven by the line-inversion method, the power supply circuit 14 fixes the second common voltage Vcom2 at a constant level, and applies the first common voltage Vcom1 to one horizontal period And may swing between the first level and the second level periodically. In this case, the output swing width of the data voltage is reduced, and the power consumption in the data driving circuit 12 can be reduced.

5 schematically shows a connection configuration of a common line for rapidly attenuating the ripple component of the common voltage.

Referring to FIG. 5, the common line CL includes a first common line CL1 and second common lines CL2 that connect the common electrodes of the liquid crystal cells on a horizontal line basis.

The first common line CL1 for connecting the common electrodes of the liquid crystal cells being charged is switched to be connected to the first bus line BL1 by the gate driving circuit 13 and is connected to the common electrodes of the uncharged liquid crystal cells And the second common lines CL2 are switched to be connected to the second bus line BL2 by the gate driving circuit 13. [ For example, assuming that the liquid crystal cells arranged in the nth horizontal line HL (n) are in the charged state, the common line arranged in the nth horizontal line HL (n) is connected to the first common line CL1 And the common lines arranged in the uncharged horizontal lines HL (n-2), HL (n + 2), etc. are connected to the first common line CL1 by the second common lines CL2 And is connected to the second bus line BL2. As a result, the ripple components on the first common line CL1 are discharged through the first discharge path including the first bus line BL1, and the ripple components on the second common lines CL2 are discharged through the second bus line BL2 The second discharge path including the second discharge path. When the discharge paths of the ripple components are made different from each other, the line resistance Rl on the first discharge path drastically decreases, so that the ripple component on the first common line CL1 is attenuated rapidly.

In order to eliminate filling unevenness and horizontal stripe, the ripple component on the first common line CL1 must be removed quickly. When the common voltage applied to the liquid crystal cells being charged is varied by the ripple component, it is difficult to set the potential difference between the pixel electrode and the common electrode in the liquid crystal cells being charged to a desired value. This is because the pixel electrodes of the liquid crystal cells being charged are electrically connected to the respective data lines. On the other hand, since uncharged liquid crystal cells are floating from each data line, they are not affected by variations in the common voltage. The potential of the pixel electrode is also changed in the same direction by the amount of potential variation of the common electrode due to the coupling effect, so that the existing potential difference can be maintained as it is. Therefore, even if the majority of the second common lines CL2 are connected to the second bus line BL2, the image quality degradation does not occur.

6 shows an array of the liquid crystal display panel 10 in which the gate drive circuit 13 is incorporated.

6, a pixel array is formed in a display area AA in which an image is displayed in the liquid crystal display panel 10 and a gate drive circuit 13 is provided in a non-display area NAA outside the display area AA .

The gate driving circuit 13 includes a plurality of units which receive the driving voltages Vdd and Vss and shift the gate start pulse GSP in accordance with the gate shift clock CLK to sequentially output the scanning pulse Vg UNT). Each of the units UNT receives the first common voltage Vcom1 through the first bus line BL1 and receives the second common voltage Vcom2 through the second bus line BL2, The first common voltage Vcom1 is supplied to the common line arranged in the horizontal line where the charging operation is activated by the first common voltage Vg and the second common voltage Vcom1 is supplied to the common line arranged in the most horizontal lines, (Vcom2). The common line to which the first common voltage Vcom1 is applied by any one of the units UNT functions as a first common line CL1 for connecting the common electrodes of the liquid crystal cells being charged, The common lines to which the second common voltage Vcom2 is applied by the units UNT function as the second common lines CL2 connecting the common electrodes of the uncharged liquid crystal cells.

Fig. 7 shows a first embodiment of the n-th unit UNT (n) shown in Fig. FIG. 8 shows a simulation result waveform for FIG. 7. FIG. In FIG. 8, 'VQ' denotes the potential of the Q node NQ, and 'VQB' denotes the QB node (NQB).

7 and 8, the n-th unit UNT (n) according to the first embodiment includes a first transistor T1, a second transistor T2, a pull-up transistor Tpu, a pull-down transistor Tpd, A first switch element S1, and a second switch element S2.

The first transistor T1 is switched according to one of the scan pulses PREV of the previous stage to apply the high potential driving voltage Vdd to the Q node NQ to activate the Q node NQ to the first level . The inverter INV deactivates the QB node NQB when the Q node NQ is activated.

The second transistor T2 is switched according to a scan pulse NEXT of the subsequent stage units to apply a low potential driving voltage Vss to the Q node NQ to inactivate the Q node NQ. The inverter INV activates the QB node NQB when the Q node NQ is inactivated.

The pull-up transistor Tpu applies the gate shift clock signal CLK to the output node NO within a period in which the Q node NQ is boot-strapping to a second level higher than the first level . The gate shift clock signal CLK applied to the output node NO is supplied to the nth gate line GL (n) as the nth scan pulse Vg (n) at the VGH level (turn-on level).

The pull-down transistor Tpd applies the low potential driving voltage Vss to the output node NO during the period in which the QB node NQB is activated. The low potential driving voltage Vss applied to the output node NO is supplied to the nth gate line GL (n) as the nth scan pulse Vg (n) at the VGL level (turn-off level).

The first switch element S1 has a gate terminal connected to the Q node NQ, a drain terminal connected to the first bus line BL1, and a source terminal connected to the nth common line CL (n) do. The first switch element S1 is turned on when the Q node NQ is activated to the first level to electrically connect the first bus line BL1 and the nth common line CL (n) And applies the first common voltage Vcom1 to the common line CL (n). At this time, the nth common line CL (n) functions as the first common line CL1 described in Fig.

The second switch element S2 has a gate terminal connected to the QB node NQB, a drain terminal connected to the second bus line BL2, and a source terminal connected to the nth common line CL (n) do. The second switch element S2 is turned on when the QB node NQB is activated to electrically connect the second bus line BL2 and the nth common line CL (n) of the second common voltage Vcom2. At this time, the n-th common line CL (n) functions as the second common line CL2 described with reference to Fig.

In Fig. 8, the first common voltage Vcom1 is inputted to the n-th unit UNT (n) at 5V and the second common voltage Vcom2 is inputted to the n-th unit UNT (n) at 8V. 8, the common voltage Vcom (n) applied to the n-th common line CL (n) through the n-th unit UNT (n) Level is 5V, which is the first common voltage Vcom1, and 8V, which is the second common voltage Vcom2 during the period in which the QB node NQB is activated.

Fig. 9 shows a second embodiment of the n-th unit UNT (n) shown in Fig.

9, the n-th unit UNT (n) according to the second embodiment includes a first transistor T1, a second transistor T2, a pull-up transistor Tpu, a pull-down transistor Tpd, A switch element S1, a second switch element S2, a third switch element S3 and a fourth switch element S4.

The first transistor T1, the second transistor T2, the pull-up transistor Tpu, the pull-down transistor Tpd, the first switch element S1 and the second switch element S2 are substantially the same as those described in FIG. Do.

The third switch element S3 is connected so as to be diode-connected between the Q node NQ and the gate terminal of the first switch element S1. The third switch element S3 increases the bootstrapping effect of the Q node NQ by reducing the capacitance of the parasitic capacitance connected to the Q node NQ.

The fourth switch element S4 has a gate terminal connected to the QB node NQB and a drain terminal connected to the first node NX between the gate terminal of the first switch element S1 and the third switch element S3. , And a source terminal to which a low potential driving voltage (Vss) is input. The fourth switch element S4 applies the low potential driving voltage Vss to the first node NX when the QB node NQB is activated.

Fig. 10 shows a third embodiment of the n-th unit UNT (n) shown in Fig.

10, the n-th unit UNT (n) according to the third embodiment includes a first transistor T1, a second transistor T2, a pull-up transistor Tpu, a pull-down transistor Tpd, And includes a switch element S1 and a second switch element S2.

The first transistor T1, the second transistor T2, the pull-up transistor Tpu, the pull-down transistor Tpd, and the second switch element S2 are substantially the same as those described in FIG.

The first switch element S1 has a gate terminal connected to the output node NO, a drain terminal connected to the first bus line BL1, and a source terminal connected to the nth common line CL (n) do. The first switch element S1 is turned on from the time point when the gate shift clock signal CLK is applied to the output node NO to the time point when the QB node NQB is activated, The first common voltage Vcom1 is applied to the nth common line CL (n) by electrically connecting the line CL (n). At this time, the nth common line CL (n) functions as the first common line CL1 described in Fig.

Fig. 11 shows a fourth embodiment of the n-th unit UNT (n) shown in Fig. Fig. 12 shows a simulation result waveform for Fig. In FIG. 12, 'VQ' represents the potential of the Q node NQ, 'VQB' represents the QB node NQB, and 'VNX' represents the potential of the first node NX.

11 and 12, the n-th unit UNT (n) according to the fourth embodiment includes a first transistor T1, a second transistor T2, a pull-up transistor Tpu, a pull-down transistor Tpd, A first switch element S1 and a second switch element S2, a third switch element S3 and a fourth switch element S4.

The first transistor T1, the second transistor T2, the pull-up transistor Tpu, the pull-down transistor Tpd, and the second switch element S2 are substantially the same as those described in FIG.

The first switch element S1 has a gate terminal connected to the first node NX, a drain terminal connected to the first bus line BL1, and a source terminal connected to the nth common line CL (n) Respectively. The first switch element S1 is turned on from the time point when the gate shift clock signal CLK is applied to the output node NO to the time point when the QB node NQB is activated, The first common voltage Vcom1 is applied to the nth common line CL (n) by electrically connecting the line CL (n). At this time, the nth common line CL (n) functions as the first common line CL1 described in Fig.

The third switch element S3 is connected so as to be diode-connected between the output node NO and the gate terminal of the first switch element S1. The third switch element S3 reduces the capacitance of the parasitic capacitance connected to the output node NO to stabilize the output node NO.

The fourth switch element S4 has a gate terminal connected to the QB node NQB and a drain terminal connected to the first node NX between the gate terminal of the first switch element S1 and the third switch element S3. , And a source terminal to which a low potential driving voltage (Vss) is input. The fourth switch element S4 applies the low potential driving voltage Vss to the first node NX when the QB node NQB is activated.

In Fig. 12, the first common voltage Vcom1 is inputted to the n-th unit UNT (n) at 11V and the second common voltage Vcom2 is inputted to the n-th unit UNT (n) at 8V. 12, the common voltage Vcom (n) applied to the n th common line CL (n) through the n th unit UNT (n) is shifted to the output node NO by the gate shift The first common voltage Vcom1 is 11V from the time when the clock signal CLK is applied to the time when the QB node NQB is activated and the second common voltage Vcom2 is 8V during the period in which the QB node NQB is activated. to be.

Fig. 13 shows a fifth embodiment of the n-th unit UNT (n) shown in Fig. Figs. 14 and 15 show waveforms of simulation results for Fig. 14 and 15, 'VQ' represents the potential of the Q node NQ, 'VQB' represents the QB node NQB, and 'VNX' represents the potential of the first node NX.

13 to 15, the n-th unit UNT (n) according to the fifth embodiment includes a first transistor T1, a second transistor T2, a pull-up transistor Tpu, a pull-down transistor Tpd, A first switch element S1 and a second switch element S2, a third switch element S3 and a fourth switch element S4.

The first transistor T1, the second transistor T2, the pull-up transistor Tpu, the pull-down transistor Tpd, and the second switch element S2 are substantially the same as those described in FIG.

The third switch element S3 is connected to a gate terminal connected to the Q node NQ, a drain terminal to which the gate shift clock signal CLK or the high potential drive voltage Vdd is inputted, a source connected to the first node NX, Terminal. The third switch element S3 is turned on when the Q node NQ is activated to the first level to apply the gate shift clock signal CLK or the high potential driving voltage Vdd to the first node NX.

The first switch element S1 has a gate terminal connected to the first node NX, a drain terminal connected to the first bus line BL1, and a source terminal connected to the nth common line CL (n) Respectively. When the gate shift clock signal CLK is applied to the first node NX, the first switch element S1 is turned on from the time when the gate shift clock signal CLK is applied to the first node NX, The first bus line BL1 and the nth common line CL (n) are electrically connected to each other until the QB node NQB is activated so that the first common line CL (n) The common voltage Vcom1 is applied. When the high potential driving voltage Vdd is applied to the first node NX, the first switch element S1 is turned on during the period in which the Q node NQ is activated to the first level, The first common voltage Vcom1 is applied to the nth common line CL (n) by electrically connecting the bus line BL1 and the nth common line CL (n). At this time, the nth common line CL (n) functions as the first common line CL1 described in Fig.

The fourth switch element S4 has a gate terminal connected to the QB node NQB and a drain terminal connected to the first node NX between the gate terminal of the first switch element S1 and the third switch element S3. , And a source terminal to which a low potential driving voltage (Vss) is input. The fourth switch element S4 applies the low potential driving voltage Vss to the first node NX when the QB node NQB is activated.

In Fig. 14, the first common voltage Vcom1 is input to the n-th unit UNT (n) at 5V and the second common voltage Vcom2 is input to the n-th unit UNT (n) at 8V. 14, the common voltage Vcom (n) applied to the n-th common line CL (n) through the n-th unit UNT (n) The first common voltage Vcom1 is 5 V from the time when the shift clock signal CLK is applied to the time when the QB node NQB is activated and the second common voltage Vcom2 during the period in which the QB node NQB is activated. 8V.

In Fig. 15, the first common voltage Vcom1 is input to the n-th unit UNT (n) at 11V and the second common voltage Vcom2 is input to the n-th unit UNT (n) at 8V. 15, the common voltage Vcom (n) applied to the n-th common line CL (n) through the n-th unit UNT (n) Level during the period in which the QB node NQB is activated and is 8V which is the second common voltage Vcom2 during the period in which the QB node NQB is activated.

In the above description, "the first common voltage Vcom1 is supplied to the common line connected to the liquid crystal cells in which the charging operation is activated by the scan pulse Vg". Note that "supplying to the common line connected to the liquid crystal cells in which the charging operation is activated" does not mean "supplying only the common line connected to the liquid crystal cells in which the charging operation is activated ". In the present invention, the first common voltage Vcom1 includes at least one horizontal line among the horizontal lines vertically adjacent to the charging horizontal line, including a common line connected to the liquid crystal cells of the horizontal line being charged To the common lines connected to the liquid crystal cells. This is because the output period of the first common voltage Vcom1 is wider than the output period of the scan pulse Vg (n), as shown in the simulation results of Figs. 8, 12, 14 and 15. Fig. For example, in the circuit as shown in FIG. 7 and FIG. 9, since the output period of the first common voltage Vcom1 is one horizontal period later and one horizontal period later than the scan pulse Vg (n) The common voltage Vcom1 may be supplied to the common line arranged on the nth horizontal line and the common line arranged on the (n-1) th and (n + 1) th horizontal lines. 10 and 11, since the output period of the first common voltage Vcom1 is one horizontal period later than the scan pulse Vg (n) as shown in Fig. 12, the first common voltage Vcom1, May be supplied to a common line disposed on the (n-1) th horizontal line and a common line disposed on the n th horizontal line. When the gate shift clock signal CLK is input in FIG. 13, since the output period of the first common voltage Vcom1 is one horizontal period later than the scan pulse Vg (n) as shown in FIG. 14, 1 common voltage Vcom1 may be supplied to the common line arranged on the (n-1) th horizontal line and the common line arranged on the nth horizontal line. 13, when the high-level driving voltage Vdd is input, the output period of the first common voltage Vcom1 becomes one horizontal period ahead of the scan pulse Vg (n) The first common voltage Vcom1 can be supplied to the common line arranged on the nth horizontal line and the common line arranged on the (n-1) th and (n + 1) th horizontal lines.

As described above, in the active matrix display device according to the present invention, the first common line connecting the common electrodes of the liquid crystal cells being charged is connected to the first bus line by using the gate driving circuit, And the second common lines connecting the electrodes are connected to the second bus line using the gate driving circuit. Accordingly, by making the discharge path of the ripple component existing on the first common line different from the discharge path of the ripple component existing on the second common lines, the present invention rapidly removes the ripple component on the first common line, , Stripes in the horizontal direction, and the like can be prevented, and the image quality can be greatly improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: liquid crystal display panel 11: timing controller
12; Data driving circuit 13: Gate driving circuit
14: Power supply circuit

Claims (10)

At least one first common line connecting common electrodes of the liquid crystal cells being charged;
A plurality of second common lines connecting common electrodes of uncharged liquid crystal cells;
A first bus line to which a first common voltage is applied;
A second bus line to which a second common voltage is applied; And
A first common line and a second common line, the scan lines sequentially generating scan pulses in accordance with the time of data application to the liquid crystal cells, switching current paths between the first bus lines and the first common lines, The first common voltage is applied to the first common line and the current path between the second bus line and the second common line is switched to apply the first common voltage to the second common lines arranged on the horizontal line, And a gate driving circuit for applying the second common voltage,
The first common line connected to the liquid crystal cells in which the charging operation is activated is exclusively connected to the first bus line to which the first common voltage is applied,
Wherein the plurality of second common lines connected to the liquid crystal cells in which the charging operation is not activated are connected in common to the second bus lines to which the second common voltage is applied. The method according to claim 1,
A display region in the display panel is defined by the liquid crystal cells;
Wherein the gate driving circuit is embedded in a non-display area of the display panel located outside the display area. 3. The method of claim 2,
The gate drive circuit includes:
A pull-up transistor connected between an input terminal and an output node of the gate shift clock signal and applying the scan pulse of the turn-on level to the output node according to the potential of the Q node;
A pull-down transistor connected between the output node and the input terminal of the low-potential driving voltage, for applying the scan pulse of the turn-off level to the output node according to the potential of the QB node having the opposite potential to the Q node;
A first switch element for switching a current path between the first bus line and the first common line according to a potential of the Q node; And
And a second switch element for switching the current path between the second bus line and the second common line according to the potential of the QB node. The method of claim 3,
The gate drive circuit includes:
A third switch element connected to be diode-connected between the Q node and the gate terminal of the first switch element; And
And a fourth switch element for applying the low potential driving voltage to the gate terminal of the first switch element in accordance with the potential of the QB node. 3. The method of claim 2,
The gate drive circuit includes:
A pull-up transistor connected between an input terminal and an output node of the gate shift clock signal and applying the scan pulse of the turn-on level to the output node according to the potential of the Q node;
A pull-down transistor connected between the output node and the input terminal of the low-potential driving voltage, for applying the scan pulse of the turn-off level to the output node according to the potential of the QB node having the opposite potential to the Q node;
A first switch element for switching a current path between the first bus line and the first common line according to a potential of the output node; And
And a second switch element for switching the current path between the second bus line and the second common line according to the potential of the QB node. 6. The method of claim 5,
The gate drive circuit includes:
A third switch element connected to make a diode connection between the output node and the gate terminal of the first switch element; And
And a fourth switch element for applying the low potential driving voltage to the gate terminal of the first switch element in accordance with the potential of the QB node. 3. The method of claim 2,
The gate drive circuit includes:
A pull-up transistor connected between an input terminal and an output node of the gate shift clock signal and applying the scan pulse of the turn-on level to the output node according to the potential of the Q node;
A pull-down transistor connected between the output node and the input terminal of the low-potential driving voltage, for applying the scan pulse of the turn-off level to the output node according to the potential of the QB node having the opposite potential to the Q node;
A third switch element for applying the gate shift clock signal or the high potential driving voltage to the first node according to the potential of the Q node;
A first switch element for switching a current path between the first bus line and the first common line according to a potential of the first node;
A second switch element for switching a current path between the second bus line and the second common line according to a potential of the QB node; And
And a fourth switch element for applying the low potential driving voltage to the first node according to the potential of the QB node. The method according to claim 1,
And a power supply circuit for generating the first common voltage to supply the first common voltage to the first bus line and generating the second common voltage to supply the second common voltage to the second bus line. 9. The method of claim 8,
Wherein the power supply circuit generates the first common voltage and the second common voltage at the same level or occurs at different levels. 9. The method of claim 8,
The power supply circuit includes:
Fixing the second common voltage to a constant level;
And swings the first common voltage at a period between a first level higher than the second common voltage and a second level lower than the second common voltage for a predetermined period.

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