CN116758871A - Driving method and driving circuit thereof - Google Patents
Driving method and driving circuit thereof Download PDFInfo
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- CN116758871A CN116758871A CN202310542532.7A CN202310542532A CN116758871A CN 116758871 A CN116758871 A CN 116758871A CN 202310542532 A CN202310542532 A CN 202310542532A CN 116758871 A CN116758871 A CN 116758871A
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000007667 floating Methods 0.000 claims abstract description 10
- 230000008859 change Effects 0.000 claims description 23
- 230000007704 transition Effects 0.000 claims description 4
- 230000008878 coupling Effects 0.000 description 126
- 238000010168 coupling process Methods 0.000 description 126
- 238000005859 coupling reaction Methods 0.000 description 126
- 239000003990 capacitor Substances 0.000 description 117
- 238000010586 diagram Methods 0.000 description 22
- 239000013256 coordination polymer Substances 0.000 description 14
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 230000011218 segmentation Effects 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000003086 colorant Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Abstract
The invention discloses a driving method and a driving circuit thereof, which are used for a display panel. The driving method is to generate a plurality of driving signals and transmit the driving signals to a plurality of driving lines of the display panel, wherein the level of a first driving signal corresponding to two adjacent driving lines and the level of a first driving signal corresponding to a second driving signal are changed from an initial level to a predetermined level, and when the level of the first driving signal is changed, the level of the second driving signal is fixed or the second driving line is in a floating state.
Description
2019/06/25, 202111170063.8, driving method and driving circuit thereof
Technical Field
The present invention relates to a driving method and a driving circuit thereof, and more particularly, to a driving method and a driving circuit thereof for reducing current consumption required for driving a display panel.
Background
The LCD (Liquid Crystal Display, LCD) has the advantages of light and thin profile, low radiation, small volume, low energy consumption, etc., and is widely used in information products such as notebook computers or flat panel televisions, among which the LCD (Active Matrix TFT LCD) using an active matrix type tft is widely used. In brief, the driving system of the active matrix type tft-lcd is composed of a timing controller (Timing Controller), a Source Driver (Source Driver) and a Gate Driver (Gate Driver). The source driving module and the gate driving module respectively control source driving lines and gate driving lines, which are mutually intersected on the panel to form a circuit unit matrix, and each circuit unit (Cell) comprises liquid crystal molecules and transistors. The display principle of the LCD is that the grid driving module sends the grid driving signal to the grid of the transistor to turn on the transistor, and the source driving module converts the data into output voltage and sends the output voltage to the source of the transistor, and the voltage at one end of the liquid crystal is equal to the voltage at the drain of the transistor, and the inclination angle of the liquid crystal molecule is changed according to the drain voltage, so that the light transmittance is changed to achieve the aim of displaying different colors.
However, as technology evolves, the resolution of the lcd increases gradually (e.g., from Full HD to 4K), and the quality of the lcd increases. As the resolution of the lcd increases, the number of driving components in the driving circuit for driving the display panel in the lcd increases. The conventional display panel has a plurality of driving lines, such as a gate driving line and a source driving line, and a coupling capacitor between adjacent driving lines, such as a coupling capacitor between the source driving line and the source driving line, a coupling capacitor between the gate driving line and the gate driving line, and a coupling capacitor between the source driving line and the gate driving line. When the driving circuit generates a driving signal and transmits the driving signal to the driving line to drive the display panel to display a picture, the driving signal transmitted to the driving line charges and discharges the coupling capacitor, so that power is consumed.
Therefore, how to reduce the power consumption of the coupling capacitor between the driving lines of the display panel is an urgent issue in the industry.
Disclosure of Invention
Therefore, the invention provides a driving method and a driving circuit thereof, which are used for reducing the power consumption of the coupling capacitor between the driving wires on the display panel, thereby reducing the total power consumption for driving the display panel.
The embodiment of the invention discloses a driving method, which is used for a display panel and comprises the steps of generating a plurality of driving signals and transmitting the driving signals to a plurality of driving lines of the display panel, wherein the level of a first driving signal corresponding to a first driving signal and the level of a second driving signal corresponding to two adjacent driving lines are changed from an initial level to a preset level, and when the level of the first driving signal is changed, the level of the second driving signal is fixed or the second driving line is in a floating state.
The embodiment of the invention also discloses a driving circuit for a display panel, which comprises a driving module and a timing controller. The driving module is coupled to a plurality of driving lines of the display panel, generates a plurality of driving signals, and transmits the driving signals to the driving lines. The time sequence controller is coupled with the driving module and controls the driving module to generate the driving signals, the level of a first driving signal corresponding to two adjacent driving lines and the level of a first driving signal corresponding to a second driving signal are changed from an initial level to a preset level, and when the level of the first driving signal is changed, the level of the second driving signal is fixed or in a floating state.
Drawings
Fig. 1 is a schematic diagram of a display according to an embodiment of the invention.
Fig. 2 is a waveform diagram of a driving method for charging two ends of a coupling capacitor according to an embodiment of the invention.
Fig. 3 is a waveform diagram of a driving method for charging two ends of a coupling capacitor according to an embodiment of the invention.
Fig. 4 to 7 are waveform diagrams of the driving method according to the embodiment of the invention for charging two ends of the coupling capacitor.
Fig. 8 is a schematic diagram of a source driving module according to an embodiment of the invention.
Fig. 9 to 15 are waveform diagrams of a driving method of the embodiment of the present invention for charging two ends of a coupling capacitor between source driving lines.
Fig. 16 is a schematic diagram of a gate driving module according to an embodiment of the invention.
Fig. 17 to 19 are waveform diagrams of a driving method of the embodiment of the present invention for charging two ends of a coupling capacitor between gate driving lines.
Fig. 20 to 23 are waveform diagrams of a driving method of the embodiment of the present invention for charging two ends of a coupling capacitor between a source driving line and a gate driving line.
Fig. 24 is a waveform diagram of a driving method for charging two ends of a coupling capacitor of a display panel according to an embodiment of the invention.
Wherein reference numerals are as follows:
10. display device
100. Display panel
102. Driving circuit
104. Gate driving module
104_1-104_N gate driving circuit
106. Source electrode driving module
106_1-106_N source electrode driving circuit
108. Time sequence controller
CN second end
CP first end
CS, CL capacitor
Cs2s, cg2g, cs2g coupling capacitance
Cycle period
GL 1-GL 3 gate drive line
GND ground voltage
MUX_1, MUX_2, MUX_3 selector
OP driving unit
PIX pixel
Source driving line of SL1 to SL4
t0 to t21 time
Vdd-6 Vdd, -Vdd-5 Vdd voltage value
Detailed Description
Referring to fig. 1, fig. 1 is a schematic diagram of a display 10 according to an embodiment of the invention. The display 10 may be, for example, a thin film transistor (Thin Film Transistor, TFT) liquid crystal display. The display 10 includes a display panel (panel) 100 and a driving circuit 102. As shown in fig. 1, the display panel 100 includes a plurality of pixels PIX. The display panel 100 has a plurality of driving lines including a plurality of gate driving lines GL1 to GLn and source driving lines SL1 to SLm, and for brevity, fig. 1 only shows the gate driving lines GL1 to GL3 and the source driving lines SL1 to SL4 as representative. Each junction between the gate driving lines GL1 to GLn and the source driving lines SL1 to SLm is a location of the pixel PIX, and is coupled to the transistor MN, and the transistor MN is coupled to the storage capacitor CS and the liquid crystal capacitor CL. The capacitors CS and CL may be coupled to a common voltage VCOM. The driving circuit 102 includes a driving module and a timing controller 108, wherein the driving module includes a gate driving module 104 and a source driving module 106. The timing controller 108 is coupled to the gate driving module 104 and generates a timing control signal to control the gate driving module 104 to generate a plurality of gate driving signals and transmit the gate driving signals to the gate driving lines GL1 to GLn respectively, so as to control the on state of the transistor MN. The timing controller 108 is coupled to the source driving module 106 and controls the source driving module 106 to generate a plurality of source driving signals according to the timing control signals and transmit the source driving signals to the source driving lines SL 1-SLm to control the potential difference across each liquid crystal molecule so as to drive the display panel 100 to display images.
In detail, the gate driving signals and the source driving signals generated by the gate driving module 104 and the source driving module 106 are voltage signals, so that the gate driving signals charge and discharge the coupling capacitances between the adjacent gate driving lines GL1 to GLn, the source driving signals generated by the source driving module 106 charge and discharge the coupling capacitances between the adjacent source driving lines SL1 to SLm, and even the gate driving signals and the source driving signals charge and discharge the coupling capacitances between the adjacent gate driving lines and the source driving lines. The timing controller 108 of the embodiment of the present invention controls the gate driving module 104 and/or the source driving module 106 to generate the gate driving signal and the source driving signal in a time-division and segmentation manner so as to charge the coupling capacitor. The time-sharing and segmentation mode is to generate a gate driving signal and a source driving signal in a switching voltage source mode, and when any coupling capacitor is charged by generating the gate driving signal and the source driving signal in the time-sharing and segmentation mode, a first end point of any coupling capacitor is charged, and a second end point of any coupling capacitor is a fixed voltage, wherein the switching voltage source mode can be switched from a low-voltage power supply to a high-voltage power supply to generate the gate driving signal and the source driving signal, that is, the absolute values of the levels of the gate driving signal and the source driving signal are changed from a low value to a high value so as to charge the coupling capacitor.
For example, please refer to fig. 2, fig. 2 is a waveform diagram illustrating a driving method for charging two ends of a coupling capacitor according to an embodiment of the present invention. Two ends of the coupling capacitor are two adjacent driving lines, such as an adjacent source driving line, an adjacent gate driving line, or an adjacent gate driving line and a source driving line, and driving signals corresponding to the two adjacent driving lines charge or discharge the two ends of the coupling capacitor. The X-axis is a time axis, the Y-axis is a voltage value across two ends of the coupling capacitor, the thick line represents a voltage change at a first end CP of the coupling capacitor, and the thick dotted line represents a voltage change at a second end CN of the coupling capacitor. For convenience of description, taking the timing controller 108 to control the source driving module 106 to generate the source driving signals as an example, the timing controller 108 controls the source driving module 106 to generate a plurality of source driving signals corresponding to the source driving lines SL 1-SLm in a period. In this example, the level of the first source driving signal of the two source driving signals corresponding to the two adjacent source driving lines is changed from the initial level of the ground voltage GND to the predetermined level of three times the voltage (i.e., 3 Vdd), so as to charge the first end CP of the coupling capacitor, and the level of the second source driving signal of the two source driving signals corresponding to the two adjacent source driving lines is always the ground voltage GND, i.e., the level of the second end CN of the coupling capacitor is kept constant. As can be seen from the above description, when the level of the first source driving signal is changed to charge the first end CP of the coupling capacitor, the level of the second source driving signal is fixed. This reduces the power loss, e.g. current loss, of charging the coupling capacitance.
Referring to fig. 3, fig. 3 is a waveform diagram illustrating a driving method for charging two ends of a coupling capacitor according to an embodiment of the invention. The X-axis is a time axis, the Y-axis is a voltage value across two ends of the coupling capacitor, the thick line segment represents a voltage change at the first end CP of the coupling capacitor, and the thick dotted line segment represents a voltage change at the second end CN of the coupling capacitor. In this embodiment, the timing controller 108 controls the source driving module 106 to generate a plurality of source driving signals corresponding to the source driving lines SL 1-SLm within a period. In this example, the levels of the first source driving signals corresponding to the two source driving signals of the two adjacent source driving lines are sequentially changed from the initial level to the predetermined level of the ground voltage GND to the voltage one Vdd, the voltage two Vdd to the voltage three Vdd, and the first end CP of the coupling capacitor is charged, and the level of the second source driving signal corresponding to the two source driving signals of the two adjacent source driving lines is always the ground voltage GND, i.e. the level of the second end CN of the coupling capacitor is kept constant. According to the embodiment of the invention, a time-sharing segmentation mode is adopted, the low-voltage power supply is sequentially switched to the high-voltage power supply to charge one end of the coupling capacitor, and when the switching voltage charges the end point of the coupling capacitor, the level of the other end of the coupling capacitor is fixed, so that the total power consumption of the charged coupling capacitor can be reduced.
Fig. 4 is a waveform diagram of a driving method for charging two ends of a coupling capacitor according to an embodiment of the present invention. In this example, the timing controller 108 controls the source driving module 106 to generate a plurality of source driving signals during the period cycle. In this example, the level of the first source driving signal of the two source driving signals corresponding to the two adjacent source driving lines is sequentially changed from the initial level to the predetermined level of one voltage Vdd, two voltage 2Vdd to three voltage 3Vdd at the time t0 to t1, t1 to t2, t2 to t3, and the first end CP of the coupling capacitor charges the coupling capacitor row with one voltage Vdd, two voltage 2Vdd and three voltage 3 Vdd. Then, the reference level of the first source driving signal is changed from the predetermined reference level of the triple voltage 3Vdd to the single voltage Vdd to discharge the coupling capacitor, and the reference level of the first source driving signal is not changed from the predetermined reference level of the triple voltage 3Vdd to the ground voltage GND, so that the charges can be recovered, and the power supply is further saved. The level of the first source driving signal is changed from a predetermined level of three times of voltage 3Vdd to one time of voltage Vdd, which is a discharge level. In addition, the level of the second source driving signal corresponding to the two source driving signals of the two adjacent source driving lines is always the ground voltage GND, i.e. the level of the second end CN of the coupling capacitor remains fixed.
Fig. 5 to 7 are waveform diagrams of the driving method according to the embodiment of the invention for charging two ends of the coupling capacitor. In the waveforms of fig. 5 to 7, the timing controller 108 controls the source driving module 106 to change the level of the first source driving signal of the two source driving signals corresponding to the two adjacent source driving lines from the first initial level to the first predetermined level of the voltage Vdd, the voltage Vdd of 2Vdd to 3Vdd, and sequentially charges the first end CP of the coupling capacitor with the voltage Vdd, the voltage Vdd of 2Vdd and the voltage Vdd of 3 Vdd; on the other hand, the timing controller 108 controls the source driving module 106 to change the level of the second source driving signal corresponding to the two source driving signals of the two adjacent source driving lines from the second initial level to the second predetermined level of the negative voltage-Vdd to the negative voltage-2 Vdd, and sequentially change the second terminal CN of the coupling capacitor from the lower negative voltage to the higher negative voltage to charge the second terminal CN of the coupling capacitor (i.e. sequentially charge the second terminal CN of the coupling capacitor with the negative voltage-Vdd and the negative voltage-2 Vdd). As can be seen from the above description, the absolute value of the first initial level (ground voltage GND) is smaller than the absolute value of the first predetermined level (three times the voltage 3 Vdd), and the absolute value of the second initial level (ground voltage GND) is smaller than the absolute value of the second predetermined level (two times the negative voltage-2 Vdd).
It should be noted that, in fig. 6, at times t0, t2, and t4, and in fig. 7, at times t0, t2, and t4, the timing controller 108 controls the source driving module 106 to make the first source driving signal corresponding to the first end CP of the coupling capacitor change different levels without changing the level of the second source driving signal corresponding to the second end CN of the coupling capacitor; in contrast, in fig. 6 and 7, at times t1 and t3, the timing controller 108 controls the source driving module 106 to change the level of the first source driving signal corresponding to the first end CP of the coupling capacitor when the second source driving signal corresponding to the second end CN of the coupling capacitor is changed to a different level. Thus, the total power consumption of the coupling capacitor can be reduced. In addition, in fig. 7, at time t5, the timing controller 108 controls the source driving module 106 to make the level of the first source driving signal corresponding to the first end CP of the coupling capacitor change from the first predetermined level (three times the voltage 3 Vdd) to the first initial level (ground voltage GND), make the level of the first source driving signal change to the discharge level (one times the voltage Vdd), and make the level of the second source driving signal corresponding to the second end CN of the coupling capacitor change from the second predetermined level (negative two times the voltage 2 Vdd) to the second initial level (ground voltage GND), so as to recycle charges to circuits generating supply voltages, such as a charging circuit (charge pump), thereby further saving power. As can be seen from the above description, the absolute value of the discharge level (one voltage Vdd, negative one voltage-Vdd) is smaller than the absolute value of the predetermined level (three voltage 3Vdd of the first predetermined level, negative two voltage-2 Vdd of the second predetermined level) and larger than the absolute value of the initial level (ground voltage GND).
Therefore, the driving method charges the coupling capacitor in a time-sharing and sectional mode, wherein the coupling capacitor is alternately switched from low voltage to high voltage to charge in a power switching mode, and the same positive potential or negative potential is achieved by less current consumption. On the other hand, the end points of the coupling capacitors are not charged at the same time, and then the low voltage power supply is used for providing charge, so as to achieve the purpose of saving electricity.
Referring to fig. 8, fig. 8 is a schematic diagram of a source driving module 106 according to an embodiment of the invention. The source driving module 106 includes a plurality of source driving circuits 106_1 to 106_n, each of the source driving circuits 106_1 to 106_n includes a selection circuit and a driving unit, the selection circuit may include selectors mux_1 and mux_2, for example, multiplexers, and the driving unit may be an amplifying unit OP. The selectors MUX_1 and MUX_2 are coupled to the timing controller 108, and the driving unit OP is coupled to an input signal VI_S. In this embodiment, the input signal VI_S can be Gamma voltages corresponding to the source driving circuits 106_1 to 106_N. The selector mux_1 receives the ground voltage GND, the voltage doubler Vdd, the voltage doubler 2Vdd, the voltage tripler 3Vdd, and the like, and is controlled by the timing controller 108 to select one of the supply voltages to provide to the driving unit OP, while the selector mux_2 receives the ground voltage GND, the voltage doubler-Vdd, the voltage doubler-2 Vdd, and the like, and is controlled by the timing controller 108 to select one of the supply voltages to provide to the driving unit OP, so that the source driving circuits 106_1 to 106_n of the embodiments of the present invention can receive the ground voltage GND, the voltage doubler (e.g., the voltage doubler Vdd, the voltage doubler 2Vdd, the voltage tripler 3Vdd, and the like) and the voltage doubler (e.g., the voltage doubler-Vdd, the voltage doubler-2 Vdd, the voltage tripler-3 Vdd, and the like) and select the supply voltages to provide the driving unit OP to generate the source driving signals to be transmitted to the corresponding source driving lines to drive the display panel, and further charge the coupling capacitors 2s between the source driving lines in a time-division manner according to the foregoing embodiments to reduce the total power consumption.
For example, the first selection circuit of the first source driving circuit 106_1 corresponding to the first source driving line SL1 receives the supply voltages, i.e., the ground voltage GND, the one-time voltage Vdd, the two-time voltage 2Vdd, the three-time voltage 3Vdd, the negative one-time voltage-Vdd, the negative two-time voltage-2 Vdd, and the timing controller 108 controls the first selection circuit to select the supply voltages and provide the supply voltages to the driving unit OP to generate the first source driving signal corresponding to one end of the coupling capacitor Cs2s between the first source driving line SL1 and the second source driving line SL2, and sends the first source driving signal to the first source driving line SL 1. Similarly, the second selection circuit of the second driving circuit 106_2 corresponding to the second source driving line SL2 receives the supply voltages, i.e., the ground voltage GND, the one-time voltage Vdd, the two-time voltage 2Vdd, the three-time voltage 3Vdd, the negative one-time voltage-Vdd, and the negative two-time voltage-2 Vdd, and the timing controller 108 controls the second selection circuit to select the supply voltages and provide the supply voltages to the driving unit OP to generate the second source driving signal corresponding to the other end of the coupling capacitor Cs2s between the first source driving line SL1 and the second source driving line SL2, and transmits the second source driving signal to the second source driving line SL 2.
For an embodiment of the driving method of the present invention applied to the coupling capacitance Cs2s between the source driving lines, please refer to fig. 9 to 12. Fig. 9 to 12 are waveform diagrams of the driving method according to the embodiment of the present invention for charging the two ends of the coupling capacitor Cs2s between the source driving lines. The thick line segment represents the variation of the level of the source driving signal corresponding to the odd source driving lines (i.e., SL1, SL3, SL5 …), which in the present embodiment corresponds to the voltage variation at the first end CP of the coupling capacitor, and the thick line segment represents the variation of the level of the source driving signal corresponding to the even source driving lines (i.e., SL2, SL4, SL6 …), which in the present embodiment corresponds to the voltage variation at the second end CN of the coupling capacitor. In this embodiment, a polarity inversion mode of the pixels PIX of the display panel 100 is a Column inversion mode (Column inversion), and the display rows and the rows are black-white images, for example, the odd rows (odd gate driving lines) are black images, the even rows (even gate driving lines) are white images, wherein the voltage of the common voltage VCOM is unchanged. As shown in fig. 9, when the Gate driving line GL1 is turned ON (Gate 1 ON) and the remaining Gate driving lines are turned OFF (other OFF), the driving method of the present invention switches to the high voltage at the time t0, t1, t2 to charge the first end of the coupling capacitor between the source driving lines (i.e. the odd source driving lines) at the low voltage and switches to the high voltage at the time t1, t2 to charge the second end of the coupling capacitor between the source driving lines (i.e. the even source driving lines) at the low negative voltage, so as to reduce the total current consumption of the coupling capacitor between the source driving lines, and further reduce the total power consumption of the driving display panel 100.
In fig. 10, the driving method of the embodiment of the invention charges the first end (i.e. the odd source driving line) of the coupling capacitor to three times of voltage 3Vdd by a time division segmentation method, and then changes the potential of the second end (i.e. the even source driving line) of the coupling capacitor to minus two times of voltage-2 Vdd by a time division method so as to reduce the total current consumption of the coupling capacitor between the source driving lines.
In fig. 11, the driving method of the embodiment of the invention fixes the second end (i.e. the even source driving line) of the coupling capacitor to the ground voltage (GND) first in time t 0-t 1, and does not change the voltage of the second end (i.e. the even source driving line) of the coupling capacitor when the voltage of the first end (i.e. the odd source driving line) of the coupling capacitor is changed in time t0, t2, t4, and in addition, does not change the voltage of the first end (i.e. the odd source driving line) of the coupling capacitor when the voltage of the second end (i.e. the even source driving line) of the coupling capacitor is changed in time t1, t3, so as to reduce the total current consumption of the coupling capacitor between the source driving lines.
In fig. 12, the driving method of the embodiment of the invention fixes the first end (i.e., the odd source driving line) of the coupling capacitor to the ground voltage (GND) at time t0, and does not change the voltage of the first end (i.e., the odd source driving line) of the coupling capacitor when the voltage of the second end (i.e., the even source driving line) of the coupling capacitor is changed in segments at times t0 and t2, and further does not change the voltage of the second end (i.e., the even source driving line) of the coupling capacitor when the voltage of the first end (i.e., the odd source driving line) of the coupling capacitor is changed in segments at times t1, t3 and t4, so as to reduce the total current consumption of the coupling capacitor between the source driving lines.
In another embodiment, please refer to fig. 13-15, fig. 13-15 are waveform diagrams of a driving method for charging two ends of a coupling capacitor Cs2s between source driving lines according to another embodiment of the present invention. The polarity inversion mode of the pixel PIX of the display panel 100 is a Dot inversion mode (Dot inversion), wherein the voltage of the common reference voltage VCOM is unchanged, the thick line segment represents the variation of the level of the source driving signal corresponding to the odd source driving lines (i.e. SL1, SL3, SL5 and …), in this embodiment, the voltage variation of the first end CP of the coupling capacitor may be equivalent, and the thick dotted line segment represents the variation of the level of the source driving signal corresponding to the even source driving lines (i.e. SL2, SL4, SL6 and …) may be equivalent to the voltage variation of the second end CN of the coupling capacitor. As shown in fig. 13, when the gate driving line GL1 is turned on and the remaining gate driving lines are turned off, the driving method of the embodiment of the invention charges the first end of the coupling capacitor (i.e. the odd source driving line) to three times of voltage 3Vdd by time division and segmentation method at time t1, t2, t3, and then changes the voltage of the second end of the coupling capacitor (i.e. the even source driving line) at time t4, t5 in a time division manner.
In fig. 14, the driving method of the embodiment of the invention fixes the second end (i.e. the even source driving line) of the coupling capacitor to the ground voltage (GND) first in time t 1-t 2, and does not change the voltage of the second end (i.e. the even source driving line) of the coupling capacitor when the voltage of the first end (i.e. the odd source driving line) of the coupling capacitor is changed in time t1, t3, t5, and in addition, does not change the voltage of the first end (i.e. the odd source driving line) of the coupling capacitor when the voltage of the second end (i.e. the even source driving line) of the coupling capacitor is changed in time t2, t4, so as to reduce the total current consumption of the coupling capacitor between the source driving lines.
In fig. 15, the driving method of the embodiment of the invention fixes the first end (i.e. the odd source driving line) of the coupling capacitor to the ground voltage (GND) first in time t 0-t 2, and does not change the voltage of the first end (i.e. the odd source driving line) of the coupling capacitor when the voltage of the second end (i.e. the even source driving line) of the coupling capacitor is changed in time t1, t3, and further does not change the voltage of the second end (i.e. the even source driving line) of the coupling capacitor when the voltage of the first end (i.e. the odd source driving line) of the coupling capacitor is changed in time t2, t4, t5, so as to reduce the total consumption current of the coupling capacitor between the source driving lines.
On the other hand, when the driving method according to the embodiment of the invention is applied to the gate driving module 104, please refer to fig. 16, fig. 16 is a schematic diagram of the gate driving module 104 according to the embodiment of the invention. The gate driving module 104 includes a plurality of source driving circuits 104_1 to 104_N, and each of the gate driving circuits 104_1 to 104_N includes a selection circuit. The selection circuit includes a selector MUX_3 coupled to the timing controller 108 and receives the ground voltage GND, the voltage doubling Vdd, the voltage doubling 2Vdd, the voltage doubling 3Vdd, the voltage doubling 4Vdd, the voltage doubling 5Vdd, the voltage doubling 6Vdd, the voltage doubling negative-Vdd, the voltage doubling negative 2Vdd, the voltage doubling negative 3Vdd, the voltage doubling negative 4Vdd, the voltage doubling negative 5Vdd, and one of the voltage supplying voltages is controlled by the timing controller 108 to generate the gate driving signal. Therefore, the gate driving circuits 104_1 to 104_n of the embodiment of the invention can select the ground voltage GND, the positive voltage (e.g., one-time voltage Vdd, two-time voltage 2Vdd, three-time voltage 3Vdd, four-time voltage 4Vdd, five-time voltage 5Vdd, six-time voltage 6Vdd, etc.) and the negative voltage (e.g., negative one-time voltage-Vdd, negative two-time voltage-2 Vdd, negative three-time voltage-3 Vdd, negative four-time voltage-4 Vdd, negative five-time voltage-5 Vdd, etc.) to generate the gate driving signals, and output the gate driving signals to the corresponding gate driving lines, so that the coupling capacitance Cg2g between the gate driving lines can be charged in a time-division and segmentation manner according to the foregoing embodiment to reduce the total power consumption of the display panel 100.
In detail, please refer to fig. 17 to 19, fig. 17 to 19 are waveform diagrams of the driving method of the embodiment of the present invention for charging two ends of the coupling capacitor Cg2g between the gate driving lines. The thick dotted line segment represents the voltage level variation of the first gate driving signal corresponding to the gate driving line GLn, and the thick solid line segment represents the voltage level variation of the second gate driving signal corresponding to the gate driving line gln+1. As shown in fig. 17, in this example, in the enabling interval of the gate driving line GLn, the level of the gate driving signal corresponding to two adjacent gate driving lines GLn, gln+1 may be first shifted from the disable level VGL to the ground voltage GND, that is, two ends of the coupling capacitor Cg2g between two adjacent gate driving lines are coupled to the ground voltage GND at time t0, which may be the initial level, and then the driving method of the present invention switches from the low voltage to the high voltage in segments at time t 1-t 6 to change the level of the first gate driving signal corresponding to the gate driving line GLn, that is, from the ground voltage GND to the predetermined level of six times the voltage 6Vdd, then from the six times the voltage 6Vdd to the ground voltage GND, and then to the disable level VGL (negative five times the voltage-5 Vdd). Meanwhile, the quasi-position time t0 to t6 of the second gate driving signal corresponding to the gate driving line gln+1 is maintained at the ground voltage GND. In addition, when the level of the first gate driving signal corresponding to the gate driving line GLn is shifted to the disable level VGL, the level of the second gate driving signal corresponding to the gate driving line gln+1 is also shifted to the disable level VGL.
In fig. 18, the driving method of the embodiment of the invention first makes the second gate driving line gln+1 in a Floating state (Floating) at time t0, i.e. the selection circuit does not provide the supply voltage to the second gate driving line gln+1, and switches the level of the first gate driving signal corresponding to the gate driving line GLn from the ground voltage GND to the six times of voltage 6Vdd, then to the ground voltage GND, and then to the disable level VGL (negative five times of voltage-5 Vdd) in a time-sharing manner from time t1 to time t 6. In addition, when the level of the first gate driving signal corresponding to the gate driving line GLn is changed to the disable level VGL, the second gate driving line gln+1 is not in the floating state, but the level of the second gate driving signal corresponding to the gate driving line gln+1 is the disable level VGL. In addition, when the level of the first gate driving signal corresponding to the gate driving line GLn is changed to the disable level VGL, the second gate driving line gln+1 may still be in the floating state, as long as the gate driving line gln+1 is in the non-floating state before the second gate driving signal corresponding to the gate driving line gln+1 is to drive the gate driving line gln+1.
In fig. 19, the driving method of the embodiment of the invention firstly converts the level of the second gate driving signal corresponding to the gate driving line gln+1 into the ground voltage GND at time t0, and gradually converts the level of the first gate driving signal corresponding to the gate driving line GLn from the disable level VGL (negative five-fold voltage-5 Vdd) to the ground voltage GND, then to the low voltage Vdd, then to the enable level (six-fold voltage 6 Vdd), then to the ground voltage GND, then to the low negative voltage-Vdd, and then to the disable level VGL (negative five-fold voltage-5 Vdd) in a time-sharing and sectional manner. In this way, the driving method of the present invention switches the low voltage to the high voltage to charge the coupling capacitance between the gate driving lines in a time-sharing and segmented manner, so as to reduce the total current consumption of the coupling capacitance between the gate driving lines, and further reduce the total power consumption of the driving display panel 100. In addition, the coupling capacitor is discharged by switching from high voltage to low voltage in a time-sharing and sectional manner, and the charge can be recovered, so that the power supply is further saved.
When the driving method of the present invention is applied to the coupling capacitance between the source driving line and the gate driving line of the display panel 100, please refer to fig. 20 to 23. Fig. 20 to 23 are waveform diagrams of the driving method according to the embodiment of the present invention for charging both ends of the coupling capacitor Cs2g between the source driving line and the gate driving line. The thick dotted line segment represents the voltage variation of the gate drive line corresponding to one end of the coupling capacitance Cs2g, and the thick solid line segment represents the voltage variation of the source drive line corresponding to the other end of the coupling capacitance Cs2 g. Fig. 20 and 21 show an embodiment of charging the coupling capacitor Cs2g by the driving method of the present invention when the level of the source driving signal corresponding to the source driving line is shifted to the forward direction. As can be seen from fig. 20 and 21, when the level of the source driving signal is shifted toward the forward direction, the level of the gate driving signal is changed from the disable level to the enable level, so that the total current consumption of the coupling capacitor between the gate driving line and the source driving line can be reduced.
Fig. 22 and 23 show an embodiment of charging the coupling capacitor Cs2g by the driving method of the present invention when the level of the source driving signal of the source driving line is shifted to the negative direction. As can be seen from fig. 22 and 23, when the level of the source driving signal is shifted toward the negative direction, the shift of the level of the gate driving signal from the disable level to the enable level is performed before the shift of the level of the gate driving signal from the disable level to the enable level, so that the total current consumption of the coupling capacitor between the gate driving line and the source driving line can be reduced.
In an embodiment of the invention, the timing controller 108 may control the source driving module 106 to determine whether to transition the levels of the source driving signals before or after the levels of the gate driving signals transition to the enable level according to the transition direction of the levels of the source driving signals.
In addition, when the driving method according to the embodiment of the present invention is applied to the driving circuit 102, the waveform diagram as shown in fig. 24 may be used to charge the coupling capacitor, so as to reduce the total current consumption for driving the display panel 100. In detail, when the level of the gate driving signal corresponding to the source driving line is about to be shifted in the negative direction, the level may be shifted before the enabling interval of the gate driving signal corresponding to the gate driving line GLn, for example, as shown in fig. 24, before the enabling interval of the gate driving signal of the gate driving line GLn, the level of the source driving signal corresponding to the second end CN of the coupling capacitor is gradually shifted from the ground voltage GND to the negative double voltage-2 Vdd. In addition, in the enable interval of the gate driving signal corresponding to the gate driving line GLn, the level of the source driving signal corresponding to the first end CP of the coupling capacitor is changed from the ground voltage GND to the triple voltage 3Vdd in a segmented manner, so that the total current consumption of the coupling capacitor of the display panel 100 can be reduced.
It should be noted that those skilled in the art can be applied to the display panel according to different requirements. For example, the driving method of the embodiments of fig. 10 and 11 can be used to charge and discharge the coupling capacitance between the source driving lines in the same period, and the combination is not limited thereto, and the present invention is also limited thereto.
In summary, the present invention provides a driving method and a driving circuit thereof, which charge the coupling capacitor of the display panel by switching the voltage and recover the charge, thereby reducing the amount of charge consumed by the coupling capacitor on the display panel and further reducing the total amount of charge consumed by driving the display panel.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A driving method for a display panel, comprising:
generating a plurality of driving signals and transmitting the driving signals to a plurality of driving lines of the display panel; the level of a driving signal corresponding to a first driving line is changed from an initial level to a predetermined level, and a second driving line adjacent to the first driving line is in a floating state during the level change of the driving signal corresponding to the first driving line.
2. The driving method according to claim 1, wherein the level of the driving signal corresponding to the first driving line is changed from the predetermined level to the initial level, and the level of the driving signal is changed to a discharge level before the level is changed from the predetermined level to the initial level, and the absolute value of the discharge level is smaller than the absolute value of the predetermined level and larger than the absolute value of the initial level.
3. The driving method of claim 1, further comprising:
providing a plurality of supply voltages; and
the supply voltages are selected to generate the drive signals corresponding to the first drive lines, the levels of the drive signals transitioning from the initial level to the predetermined level.
4. The driving method according to claim 1, wherein the driving lines of the display panel include a plurality of gate driving lines, the driving signals include a plurality of gate driving signals, the two adjacent driving lines are two adjacent gate driving lines, and the driving signal corresponding to the first gate driving line is a gate driving signal.
5. A driving circuit of a display panel, comprising:
the driving module is coupled with a plurality of driving lines of the display panel, generates a plurality of driving signals and transmits the driving signals to the driving lines; and
the time sequence controller is coupled with the driving module and used for controlling the driving module to generate the driving signals, the level of a driving signal corresponding to a first driving line is changed from an initial level to a predetermined level, and a second driving line adjacent to the first driving line is in a floating state during the level change period of the driving signal corresponding to the first driving line.
6. The driving circuit as recited in claim 5 wherein said driving signal level corresponding to said first driving line transitions from said predetermined level to said initial level, said driving signal level transitioning from said predetermined level to said initial level first to a discharge level, said discharge level having an absolute value less than an absolute value of said predetermined level and greater than an absolute value of said initial level.
7. The drive circuit of claim 5, wherein the drive module further comprises:
and the timing controller is used for controlling the selection circuit to select the supply voltages so as to generate the driving signals corresponding to the first driving lines, and the level of the driving signals is changed from the initial level to the preset level.
8. The driving circuit of claim 5, wherein the plurality of driving lines of the display panel comprise a plurality of gate driving lines, the plurality of driving signals generated by the driving module comprise a plurality of gate driving signals, the two adjacent driving lines are two adjacent gate driving lines, the driving signal corresponding to the first gate driving line is a gate driving signal, the driving module comprises:
and a gate driving circuit coupled to the gate driving lines and the timing controller, for generating the gate driving signals and transmitting the gate driving signals to the gate driving lines.
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| US201862689249P | 2018-06-25 | 2018-06-25 | |
| US62/689,249 | 2018-06-25 | ||
| CN201910555100.3A CN110634451B (en) | 2018-06-25 | 2019-06-25 | Driving method and driving circuit thereof |
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| CN202310542532.7A Pending CN116758871A (en) | 2018-06-25 | 2019-06-25 | Driving method and driving circuit thereof |
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| JP2003149676A (en) * | 2001-11-15 | 2003-05-21 | Matsushita Electric Ind Co Ltd | Active matrix type liquid crystal display device, and its driving method |
| JP2004117513A (en) * | 2002-09-24 | 2004-04-15 | Sony Corp | Device and method for displaying image |
| TWI282540B (en) * | 2003-08-28 | 2007-06-11 | Chunghwa Picture Tubes Ltd | Controlled circuit for a LCD gate driver |
| TW200926107A (en) * | 2007-12-10 | 2009-06-16 | Richtek Technology Corp | A row driving cells of electroluminescent display and the method thereof |
| CN100561563C (en) * | 2007-12-29 | 2009-11-18 | 友达光电股份有限公司 | LCD and Drive and Control Circuit thereof |
| US9129576B2 (en) * | 2008-05-06 | 2015-09-08 | Himax Technologies Limited | Gate driving waveform control |
| TWI410941B (en) * | 2009-03-24 | 2013-10-01 | Au Optronics Corp | Liquid crystal display capable of reducing image flicker and method for driving the same |
| CN101826314B (en) * | 2010-03-10 | 2012-09-05 | 敦泰科技(深圳)有限公司 | Driving method and driving circuit of thin film transistor (TFT) liquid crystal display screen |
| CN101976551B (en) * | 2010-10-19 | 2014-06-04 | 友达光电股份有限公司 | Display driving circuit, liquid crystal display and display driving method |
| WO2013018597A1 (en) * | 2011-08-02 | 2013-02-07 | シャープ株式会社 | Display device and method for powering same |
| CN103177682B (en) * | 2013-03-26 | 2015-05-13 | 京东方科技集团股份有限公司 | Display drive circuit and drive method thereof as well as display device |
| TWI527019B (en) * | 2014-06-25 | 2016-03-21 | 友達光電股份有限公司 | Timing signal generation circuit and precharging/discharging method thereof |
| TWI552138B (en) * | 2014-08-11 | 2016-10-01 | 友達光電股份有限公司 | Display and gate driver thereof |
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| CN113990265B (en) | 2023-06-30 |
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| CN110634451A (en) | 2019-12-31 |
| CN113990265A (en) | 2022-01-28 |
| TW202001867A (en) | 2020-01-01 |
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