CN110634451A - Driving method and driving circuit thereof - Google Patents

Abstract

The invention discloses a driving method and a driving circuit thereof, which are used for a display panel. The driving method is to generate a plurality of driving signals and transmit the driving signals to a plurality of driving lines of the display panel, wherein the level of a first driving signal and the level of a first driving signal of a second driving signal corresponding to two adjacent driving lines are changed from an initial level to a preset level, and when the level of the first driving signal is changed, the level of the second driving signal is fixed or the second driving line is in a floating state.

Description

Driving method and driving circuit thereof

technical field

The present invention relates to a driving method and a driving circuit thereof, in particular to a driving method and a driving circuit thereof for reducing the current consumption required for driving a display panel.

Background technique

Liquid Crystal Display (LCD) has the advantages of light and thin appearance, low radiation, small size and low energy consumption, and is widely used in information products such as notebook computers or flat-screen TVs. Among them, the active matrix thin film transistor liquid crystal display ( Active Matrix TFT LCD) is widely adopted. To put it simply, the driving system of the active matrix TFT-LCD is composed of a timing controller, a source driver and a gate driver. The source driving module and the gate driving module respectively control the source driving lines and the gate driving lines, which cross each other on the panel to form a matrix of circuit cells, and each circuit cell (Cell) includes liquid crystal molecules and transistors. The display principle of the liquid crystal display is that the gate drive module first sends the gate drive signal to the gate of the transistor to turn on the transistor, and at the same time, the source drive module converts the data into an output voltage, and then sends the output voltage to the source of the transistor. At this time, the voltage at one end of the liquid crystal will be equal to the voltage at the drain electrode of the transistor, and the tilt angle of the liquid crystal molecules will be changed according to the drain electrode voltage, thereby changing the light transmittance to achieve the purpose of displaying different colors.

However, with the evolution of technology, the resolution of the liquid crystal display is gradually increased (eg, from a Full HD resolution to a 4K resolution), and the picture display quality of the liquid crystal display is also improved accordingly. As the resolution of the liquid crystal display increases, the number of driving components in the driving circuit for driving the display panel in the liquid crystal display also increases. Among them, the existing display panel has a plurality of driving lines, such as gate driving lines and source driving lines, and there are coupling capacitances between adjacent driving lines, such as coupling capacitances between the source driving lines and the source driving lines, The coupling capacitance between the gate driving line and the gate driving line and the coupling capacitance between the source driving line and the gate driving line. When the driving circuit generates the driving signal and transmits it to the driving line to drive the display panel to display the picture, the driving signal transmitted to the driving line will charge and discharge the above-mentioned coupling capacitor, which consumes power.

Therefore, how to reduce the power consumed by the coupling capacitors between the driving lines of the display panel has become an urgent issue in the industry.

SUMMARY OF THE INVENTION

Therefore, the present invention provides a driving method and a driving circuit thereof to reduce the power consumption of coupling capacitors between driving lines on the display panel, thereby reducing the total power consumption for driving the display panel.

An embodiment of the present invention discloses a driving method for a display panel, including generating a plurality of driving signals and transmitting the driving signals to a plurality of driving lines of the display panel, a first driving signal corresponding to two adjacent driving lines and The level of the first driving signal of a second driving signal changes from an initial level to a predetermined level. When the level of the first driving signal changes, the level of the second driving signal is fixed or the second driving line is in floating state.

An embodiment of the present invention further discloses a driving circuit for a display panel, which includes a driving module and a timing controller. The driving module is coupled to a plurality of driving lines of the display panel, generates a plurality of driving signals, and transmits the driving signals to the driving lines. The timing controller is coupled to the driving module, and controls the driving module to generate the driving signals. When the level of the first driving signal changes to a predetermined level, the level of the second driving signal is fixed or in a floating state.

Description of drawings

FIG. 1 is a schematic diagram of a display according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of charging two ends of a coupling capacitor by a driving method according to an embodiment of the present invention.

FIG. 3 is a waveform diagram of charging two ends of a coupling capacitor by a driving method according to an embodiment of the present invention.

FIG. 4 to FIG. 7 are waveform diagrams of charging two ends of a coupling capacitor by a driving method according to an embodiment of the present invention, respectively.

FIG. 8 is a schematic diagram of a source driving module according to an embodiment of the present invention.

9 to 15 are waveform diagrams of charging both ends of the coupling capacitor between the source driving lines by the driving method according to the embodiment of the present invention.

FIG. 16 is a schematic diagram of a gate driving module according to an embodiment of the present invention.

FIG. 17 to FIG. 19 are waveform diagrams of charging the two ends of the coupling capacitor between the gate driving lines by the driving method according to the embodiment of the present invention.

FIGS. 20 to 23 are waveform diagrams of charging the two ends of the coupling capacitor between the source driving line and the gate driving line by the driving method according to the embodiment of the present invention.

FIG. 24 is a waveform diagram of charging both ends of a coupling capacitor of a display panel by a driving method according to an embodiment of the present invention.

Among them, the reference numerals are described as follows:

10 monitors

100 display panels

102 Drive circuit

104 Gate Drive Module

104_1～104_N gate drive circuit

106 source driver module

106_1～106_N source drive circuit

108 Timing Controller

CN second end

CP first end

CS, CL capacitors

Cs2s, Cg2g, Cs2g Coupling Capacitors

Cycle cycle

GL1～GLn gate drive lines

GND ground voltage

MUX_1, MUX_2, MUX_3 selectors

OP drive unit

PIX pixels

SL1～SLn source drive lines

t0～t21 time

Vdd～6Vdd, -Vdd～-5Vdd voltage value

Detailed ways

Please refer to FIG. 1 , which is a schematic diagram of a display 10 according to an embodiment of the present invention. The display 10 may be, for example, a thin film transistor (Thin Film Transistor, TFT) liquid crystal display. The display 10 includes a display panel 100 and a driving circuit 102 . As shown in FIG. 1 , the display panel 100 includes a plurality of pixels PIX. The display panel 100 has a plurality of driving lines, including a plurality of gate driving lines GL1-GLn and source driving lines SL1-SLm. For simplicity, only the gate driving lines GL1-GL3 and the source driving line SL1 are shown in FIG. 2 . ~SL4 as a representative. Each intersection of the gate driving lines GL1-GLn and the source driving lines SL1-SLm is the location of the pixel PIX, and is coupled to the transistor MN, which is coupled to the storage capacitor CS and the liquid crystal capacitor CL. Both the capacitors CS and CL can be coupled to a common voltage VCOM. The driving circuit 102 includes a driving module and a timing controller 108 . The driving module includes a gate driving module 104 and a source driving module 106 . The timing controller 108 is coupled to the gate driving module 104, and generates a timing control signal to control the gate driving module 104 to generate a plurality of gate driving signals and transmit them to the gate driving lines GL1-GLn respectively, so as to control the conduction state of the transistor MN . The timing controller 108 is coupled to the source driving module 106 and controls the source driving module 106 to generate a plurality of source driving signals through timing control signals and transmit them to the source driving lines SL1-SLm, so as to control the voltages at both ends of each liquid crystal molecule. The potential difference is used to drive the display panel 100 to display images.

In detail, the gate driving signal and the source driving signal generated by the gate driving module 104 and the source driving module 106 are voltage signals, so the gate driving signal will couple the adjacent gate driving lines GL1 to GLn. The capacitor is charged and discharged, and the source drive signal generated by the source drive module 106 will charge and discharge the coupling capacitance between the adjacent source drive lines SL1-SLm, and even the gate drive signal and the source drive signal will affect the adjacent The coupling capacitance between the gate driving line and the source driving line is charged and discharged. The timing controller 108 in the embodiment of the present invention controls the gate driving module 104 and/or the source driving module 106 to generate the gate driving signal and the source driving signal in a time-division manner to charge the above-mentioned coupling capacitor. The time-division and subsection method is to generate the gate driving signal and the source driving signal in a switching voltage source mode, and when the gate driving signal and the source driving signal are generated in the time-division subsection mode, any coupling capacitor is charged. When , a first terminal of any coupling capacitor is charged, and a second terminal of any coupling capacitor is a fixed voltage, and the switching voltage source mode is to switch from a low-voltage power supply to a high-voltage power supply to generate a gate The gate driving signal and the source driving signal, that is, the absolute value of the level of the gate driving signal and the source driving signal, are changed from low value to high value, so as to charge the coupling capacitor.

For example, please continue to refer to FIG. 2 , which is a waveform diagram of charging two ends of a coupling capacitor by a driving method according to an embodiment of the present invention. The two ends of the coupling capacitor are adjacent two drive lines, such as adjacent source drive lines, adjacent gate drive lines, or adjacent gate drive lines and source drive lines, and the corresponding adjacent The driving signals of the two driving lines will charge or discharge both ends of the coupling capacitor. Among them, the X axis is the time axis, the Y axis is a voltage value across the two ends of the coupling capacitor, the thick solid line segment represents the voltage change of a first terminal CP of the coupling capacitor, and the thick dotted line segment represents a second terminal of the coupling capacitor The voltage change of CN. For convenience of description, the following takes the timing controller 108 controlling the source driving module 106 to generate source driving signals as an example. In one cycle, the timing controller 108 controls the source driving module 106 to generate a plurality of source driving signals. The source driving signals correspond to the source driving lines SL1 ˜SLm. In this example, the level of the first source driving signal corresponding to the two source driving signals of the adjacent two source driving lines is changed from the initial level of the ground voltage GND to the predetermined level of triple voltage (ie 3Vdd). The first terminal CP of the coupling capacitor is charged, and the level of the second source driving signal corresponding to the two source driving signals of the adjacent two source driving lines is always the ground voltage GND, that is, the level of the coupling capacitor is GND. The level of the second end CN remains fixed. It can be seen from the above description that when the level of the first source driving signal is changed to charge the first terminal CP of the coupling capacitor, the level of the second source driving signal is fixed. This reduces power losses, such as current losses, for charging the coupling capacitors.

Please continue to refer to FIG. 3 . FIG. 3 is a waveform diagram of charging two ends of a coupling capacitor by a driving method according to an embodiment of the present invention. Among them, the X axis is the time axis, the Y axis is a voltage value across the two ends of the coupling capacitor, the thick solid line segment represents the voltage change of the first terminal CP of the coupling capacitor, and the thick dashed line segment represents a second terminal CN of the coupling capacitor voltage change. In this embodiment, in one cycle, the timing controller 108 controls the source driving module 106 to generate a plurality of gate driving signals, and the source driving signals correspond to the source driving lines SL1 ˜SLm. In this example, the levels of the first source driving signals corresponding to the two source driving signals of the adjacent two source driving lines are sequentially located at times t0 - t1 , t1 - t2 and t2 - t3 from the initial level to The ground voltage GND is converted into a predetermined level of a double voltage Vdd, a double voltage 2Vdd to a triple voltage 3Vdd, and the first terminal CP of the coupling capacitor is charged, and the two source electrodes of the adjacent two source drive lines are charged. The level of the second source driving signal of the driving signal is always the ground voltage GND, that is, the level of the second terminal CN of the coupling capacitor remains fixed. In the embodiment of the present invention, the low-voltage power supply is switched to the high-voltage power supply in sequence to charge one end of the coupling capacitor in a time-division and segmentation manner, and when the switching voltage charges the end of the coupling capacitor, the level of the other end of the coupling capacitor is fixed. , which reduces the total power consumption of the charging coupling capacitor.

FIG. 4 is a waveform diagram of charging two ends of a coupling capacitor by a driving method according to an embodiment of the present invention. In this example, within a cycle, the timing controller 108 controls the source driving module 106 to generate a complex number of gate driving signals. In this example, the levels of the first source drive signals corresponding to the two source drive signals of the adjacent two source drive lines are sequentially changed from the initial level at times t0 to t1, t1 to t2, and t2 to t3. In order to convert the ground voltage GND into a predetermined level from a voltage of one time Vdd, two times the voltage of 2Vdd to three times the voltage of 3Vdd, and the first terminal CP of the coupling capacitor has a voltage of one time Vdd, two times the voltage of 2Vdd, and three times the voltage of 3Vdd. Coupling capacitor row charging. Next, the level of the first source driving signal is changed from the predetermined level of the triple voltage 3Vdd to the double voltage Vdd at time t3-t4 to discharge the coupling capacitor, and the level of the first source driving signal is not tripled The predetermined level of the voltage of 3Vdd is directly converted into the ground voltage GND, so that the electric charge can be recovered and the power supply can be further saved. The level of the first source driving signal is changed from the predetermined level of the triple voltage 3Vdd to the double voltage Vdd, and the double voltage Vdd is the discharge level. In addition, the level of the second source driving signal corresponding to the two source driving signals of the adjacent two source driving lines is always the ground voltage GND, that is, the level of the second terminal CN of the coupling capacitor remains fixed.

FIG. 5 to FIG. 7 are waveform diagrams of charging two ends of a coupling capacitor by a driving method according to an embodiment of the present invention, respectively. Different from the waveform diagrams in FIG. 3 , in FIGS. 5 to 7 , in the cycle, the timing controller 108 controls the source driving module 106 to make the second source driving signals corresponding to the two adjacent source driving lines The level of a source driving signal is changed from the first initial level of the ground voltage GND to the first predetermined level of the double voltage Vdd, the double voltage 2Vdd to the triple voltage 3Vdd, and the first predetermined level of the coupling capacitor is sequentially One terminal CP charges the coupling capacitor row with one voltage Vdd, two times voltage 2Vdd and three times voltage 3Vdd; on the other hand, the timing controller 108 controls the source driving module 106 to make the corresponding two adjacent source driving lines The level of the second source driving signal of the two source driving signals is changed from the second initial level, which is the ground voltage GND, to the second predetermined level of one negative voltage -Vdd to twice the negative voltage -2Vdd, and sequentially The second terminal CN of the coupling capacitor is charged with a lower negative voltage to a higher negative voltage (that is, the second terminal CN of the coupling capacitor is charged with a negative double voltage -Vdd and a negative double voltage -2Vdd in sequence. The second terminal CN of the coupling capacitor is charged). It can be known from the above description that the absolute value of the first initial level (ground voltage GND) is less than the absolute value of the first predetermined level (three times the voltage 3Vdd), and the absolute value of the second initial level (ground voltage GND) is lower than The absolute value of the second predetermined level (twice the negative pressure-2Vdd).

It should be noted that in FIG. 6 , at times t0 , t2 , t4 , and t6 , and in FIG. 7 , at times t0 , t2 , t4 , and t6 , the timing controller 108 controls the source driver module 106 to allow When the first source driving signal corresponding to the first terminal CP of the coupling capacitor changes to different levels, the level of the second source driving signal corresponding to the second terminal CN of the coupling capacitor does not change; As in FIG. 7 , at times t1 and t3, the timing controller 108 controls the source driving module 106 so that the second source driving signal corresponding to the second terminal CN of the coupling capacitor is changed to different levels, the corresponding level is not changed. The level of the first source driving signal at the first terminal CP of the coupling capacitor. In this way, the total power consumption of the coupling capacitor can be reduced. In addition, in FIG. 7 , at time t5, the timing controller 108 controls the source driving module 106 so that the level of the first source driving signal corresponding to the first terminal CP of the coupling capacitor is changed from the first predetermined level ( Before the triple voltage 3Vdd) is shifted to the first initial level (the ground voltage GND), the level of the first source driving signal is shifted to the discharge level (double the voltage Vdd), and the voltage corresponding to the coupling capacitor is also shifted. Before the level of the second source driving signal of the second terminal CN changes from the second predetermined level (negative double voltage -2Vdd) to the second initial level (ground voltage GND), let the second source driving signal The level of , is shifted to the discharge level (negative double voltage - Vdd), so that the charge can be recovered to the circuit that generates the supply voltage, such as a charge pump, to further save power. It can be known from the above description that the absolute value of the discharge level (one time voltage Vdd, negative one time voltage -Vdd) is less than the predetermined level (three times the voltage of the first predetermined level, 3Vdd, and the second predetermined level is negative twice the voltage. -2Vdd) and greater than the absolute value of the initial level (ground voltage GND).

Therefore, in the driving method of the present invention, the coupling capacitor is charged in a time-division and segmented manner, and the coupling capacitor is charged by switching from a low voltage to a high voltage in turn by switching the power supply, so as to achieve the same positive potential with less current consumption. or negative potential. On the other hand, the terminals of the coupling capacitors are not charged at the same time, and the low-voltage power supply provides charging charges to achieve the purpose of saving power.

Please refer to FIG. 8 , which is a schematic diagram of the source driving module 106 according to an embodiment of the present invention. The source driver module 106 includes a plurality of source driver circuits 106_1 ˜ 106_N. Each source driver circuit 106_1 ˜ 106_N includes a selection circuit and a driver unit. The selection circuit may include selectors MUX_1 and MUX_2 , such as a multiplexer. , and the driving unit may be an amplifying unit OP. The selectors MUX_1 and MUX_2 are coupled to the timing controller 108, and the driving unit OP is coupled to an input signal VI_S. In this embodiment, the input signal VI_S may be a gamma voltage corresponding to the source driving circuits 106_1 ˜ 106_N. The selector MUX_1 receives supply voltages such as the ground voltage GND, the double voltage Vdd, the double voltage 2Vdd, and the triple voltage 3Vdd, and is controlled by the timing controller 108 to select one of the supply voltages and provide it to the driving unit OP, and The selector MUX_2 receives supply voltages such as the ground voltage GND, the negative double voltage -Vdd, and the negative double voltage -2Vdd, and is controlled by the timing controller 108 to select one of the supply voltages and provide it to the driving unit OP. Therefore, this The source driving circuits 106_1 ˜ 106_N of the embodiment of the invention can receive the ground voltage GND, a positive double voltage (for example, a double voltage Vdd, a double voltage 2Vdd, a triple voltage 3Vdd, etc.) and a negative double voltage (such as a negative double voltage- Vdd, negative double voltage-2Vdd, negative triple voltage-3Vdd, etc.) and select these supply voltages to provide the driving unit OP to generate source driving signals and transmit them to the corresponding source driving lines to drive the display panel , and further charge the coupling capacitor Cs2s between the source driving lines according to the time-division and segmentation method of the foregoing embodiment to reduce the total power consumption.

For example, the first selection circuit of the first driving circuit 106_1 corresponding to the first source driving line SL1 receives the supply voltage ground voltage GND, double voltage Vdd, double voltage 2Vdd, triple voltage 3Vdd, negative one Double voltage -Vdd, negative double voltage -2Vdd, the timing controller 108 controls the first selection circuit to select the supply voltages and provide them to the driving unit OP to generate the first source driving signal and transmit it to the first source For the driving line SL1, the first source driving signal corresponds to one end of the coupling capacitor Cs2s between the first source driving line SL1 and the second source driving line SL2. Similarly, the second selection circuit of the second driving circuit 106_2 corresponding to the second source driving line SL2 receives the supply voltage ground voltage GND, double voltage Vdd, double voltage 2Vdd, triple voltage 3Vdd, negative double voltage Voltage -Vdd, negative double voltage -2Vdd, the timing controller 108 controls the second selection circuit to select the supply voltages and provide them to the driving unit OP to generate a second source driving signal and transmit it to the second source driving Line SL2, the second source driving signal corresponds to the other end of the coupling capacitor Cs2s between the first source driving line SL1 and the second source driving line SL2.

For an embodiment when the driving method of the present invention is applied to the coupling capacitor Cs2s between the source driving lines, please refer to FIGS. 9 to 12 . 9 to 12 are waveform diagrams of charging the two ends of the coupling capacitor Cs2s between the source driving lines by the driving method according to the embodiment of the present invention. The thick solid line segment represents the level change of the source drive signal corresponding to the odd-numbered source drive lines (ie, SL1, SL3, SL5...), which can be equivalent to the voltage change of the first terminal CP of the coupling capacitor in this embodiment, The thick dashed line segment represents the level change of the source drive signal corresponding to the even-numbered source drive lines (ie, SL2, SL4, SL6 . In this embodiment, a polarity inversion mode of the pixels PIX of the display panel 100 is a column inversion mode, and a black-and-white image is displayed between rows and rows. For example, the odd-numbered rows (odd-numbered gate driving lines) are Black images, even-numbered rows (even-numbered gate driving lines) are white images, and the voltage of the common voltage VCOM remains unchanged. As shown in FIG. 9 , when the gate driving line GL1 is turned on (Gate1 ON) and the remaining gate driving lines are turned off (Others OFF), the driving method of the present invention switches to low voltage at times t0, t1 and t2 in a time-division and segmental manner. The first end of the coupling capacitor between the high voltage and the source drive lines (ie, odd-numbered source drive lines) and the second end of the coupling capacitor between the source drive lines switched from a low negative voltage to a high negative voltage at time t1 and t2 The terminals (ie, even-numbered source driving lines) are charged, so as to reduce the total current consumption of the coupling capacitors between the source driving lines, thereby reducing the total power consumption of driving the display panel 100 .

In FIG. 10 , the driving method of the embodiment of the present invention first charges the first end of the coupling capacitor (ie, the odd-numbered source driving line) to three times the voltage of 3Vdd in a time-division method, and then changes the coupling in a time-division method. The potential of the second end of the capacitor (ie, the even-numbered source drive lines) is reduced to a negative double voltage of -2Vdd, so as to reduce the total current consumption of the coupling capacitors between the source drive lines.

In FIG. 11 , in the driving method of the embodiment of the present invention, the second end of the coupling capacitor (ie, the even-numbered source driving line) is first fixed to the ground voltage (GND) from time t0 to t1 , and the time t0 , t2 , and t4 are divided When the voltage of the first end of the coupling capacitor (that is, the odd-numbered source drive line) is changed in stages, the voltage of the second end of the coupling capacitor (that is, the even-numbered source drive line) is not changed. When the voltage of the second terminal (ie, the even-numbered source driving lines) is not changed, the voltage of the first terminal (ie, the odd-numbered source driving lines) of the coupling capacitor is not changed, so as to reduce the total current consumption of the coupling capacitors between the source driving lines.

In FIG. 12 , in the driving method of the embodiment of the present invention, the first end of the coupling capacitor (ie, the odd-numbered source driving line) is fixed to the ground voltage (GND) at time t0, and the coupling capacitance is changed segmentally at time t0 and t2 When the voltage of the second terminal (that is, the even-numbered source driving line) is not changed, the voltage of the first terminal (that is, the odd-numbered source driving line) of the coupling capacitor is not changed. When the voltage of one end (ie, odd-numbered source driving lines) is not changed, the voltage of the second end (ie, even-numbered source driving lines) of the coupling capacitor is not changed, so as to reduce the total consumption current of the coupling capacitors between the source driving lines.

In another embodiment, please refer to FIGS. 13 to 15 . FIGS. 13 to 15 are waveform diagrams of charging the two ends of the coupling capacitor Cs2s between the source driving lines by the driving method according to another embodiment of the present invention. The polarity inversion mode of the pixels PIX of the display panel 100 is a dot inversion mode, in which the voltage of the common reference voltage VCOM remains unchanged, and the thick solid line segments represent the corresponding odd-numbered source drive lines (ie, SL1, SL3, SL5). . The change of the level of the source drive signal of ...) can be equivalent to the change of the voltage of the second terminal CN of the coupling capacitor. As shown in FIG. 13 , when the gate driving line GL1 is turned on and the other gate driving lines are turned off, the driving method according to the embodiment of the present invention first divides the first end of the coupling capacitor by a time-division and segmentation method at time t1, t2, and t3. (ie, the odd-numbered source drive lines) are charged to triple the voltage of 3Vdd, and then change the voltage of the second end of the coupling capacitor (ie, the even-numbered source drive lines) in a time-division manner at time t4 and t5.

In FIG. 14 , in the driving method of the embodiment of the present invention, the second end of the coupling capacitor (ie, the even-numbered source driving line) is first fixed to the ground voltage (GND) from time t1 to t2, and the second end of the coupling capacitor (ie, the even-numbered source driving line) is fixed to the ground voltage (GND) at time t1, t3, and t5. When the voltage of the first end of the coupling capacitor (that is, the odd-numbered source drive line) is changed in stages, the voltage of the second end of the coupling capacitor (that is, the even-numbered source drive line) is not changed. In addition, the coupling capacitance is changed in sections at time t2 and t4. When the voltage of the second terminal (that is, the even-numbered source driving line) is not changed, the voltage of the first terminal (that is, the odd-numbered source driving line) of the coupling capacitor is not changed, so as to reduce the total power consumption of the coupling capacitor between the source driving lines. flow.

In FIG. 15 , in the driving method according to the embodiment of the present invention, the first end of the coupling capacitor (ie, the odd-numbered source driving lines) is fixed to the ground voltage (GND) at times t0 to t2, and is changed segmentally at times t1 and t3. When the voltage of the second end of the coupling capacitor (that is, the even-numbered source drive line), the voltage of the first end of the coupling capacitor (that is, the odd-numbered source drive line) does not change. In addition, the coupling capacitance is changed segmentally at time t2, t4, and t5. When the voltage of the first terminal (that is, the odd-numbered source driving line) is not changed, the voltage of the second terminal (that is, the even-numbered source driving line) of the coupling capacitor is not changed, so as to reduce the total power consumption of the coupling capacitor between the source driving lines. flow.

On the other hand, when the driving method according to the embodiment of the present invention is applied to the gate driving module 104, please refer to FIG. 16, which is a schematic diagram of the gate driving module 104 according to the embodiment of the present invention. The gate driving module 104 includes a plurality of source driving circuits 104_1 ˜ 104_N, and each gate driving circuit 104_1 ˜ 104_N includes a selection circuit MUX_3 . The selector MUX_3 is coupled to the timing controller 108, and receives the ground voltage GND, the double voltage Vdd, the double voltage 2Vdd, the triple voltage 3Vdd, the quadruple voltage 4Vdd, the five times voltage 3Vdd, the six times voltage 6Vdd, and the negative double voltage Voltage-Vdd, negative double voltage-2Vdd, negative triple voltage-3Vdd, negative quadruple voltage-4Vdd, negative five times voltage-5Vdd and other supply voltages, and are controlled by the timing controller 108 to select one of the supply voltages Thereby, a gate driving signal is generated. Therefore, the gate driving circuits 104_1 ˜ 104_N of the embodiment of the present invention can select the ground voltage GND, the positive voltage (for example, the double voltage Vdd, the double voltage 2Vdd, the triple voltage 3Vdd, the quadruple voltage 4Vdd, the fifth voltage 3Vdd, Six times voltage 6Vdd, etc.) and negative times voltage (for example, negative double voltage-Vdd, negative double voltage-2Vdd, negative triple voltage-3Vdd, negative quadruple voltage-4Vdd, negative five times voltage-5Vdd, etc.) and The gate driving signal is generated and output to the corresponding gate driving line, and then the coupling capacitor Cg2g between the gate driving lines can be charged according to the time-division and segmentation method of the foregoing embodiment to reduce the total power consumption of the display panel 100 quantity.

In detail, please refer to FIGS. 17 to 19 . FIGS. 17 to 19 are waveform diagrams of charging the two ends of the coupling capacitor Cg2g between the gate driving lines by the driving method according to the embodiment of the present invention. The thick dotted line segment represents the voltage level change of the first gate driving signal corresponding to the gate driving line GLn, and the thick solid line segment represents the voltage level change of the second gate driving signal corresponding to the gate driving line GLn+1. As shown in FIG. 17 , in this example, in the enabling interval of the gate driving line GLn, the levels of the gate driving signals corresponding to the two adjacent gate driving lines GLn and GLn+1 can be disabled first. The energy level VGL is changed to the ground voltage GND, that is, the two ends of the coupling capacitor Cg2g between the two adjacent gate driving lines are coupled to the ground voltage GND at time t0, which can be the initial level, and then the driving method of the present invention is at time t0 From t1 to t6, the level of the first gate driving signal corresponding to the gate driving line GLn is changed by switching from low voltage to high voltage in a segmented manner, that is, from the ground voltage GND to the predetermined level of six times the voltage of 6Vdd, and then from The six times voltage 6Vdd is converted to the ground voltage GND, and then converted to the disable level VGL (negative five times the voltage across -5Vdd). Meanwhile, the quasi-positioning times t0 to t6 of the second gate driving signal corresponding to the gate driving line GLn+1 are maintained at the ground voltage GND. In addition, when the level of the first gate driving signal corresponding to the gate driving line GLn is changed to the disable level VGL, the level of the second gate driving signal corresponding to the gate driving line GLn+1 is also changed To disable the level VGL.

In FIG. 18, the driving method according to the embodiment of the present invention first makes the second gate driving line GLn+1 in a floating state at time t0, that is, the selection circuit does not provide a supply voltage to the second gate driving line GLn +1, and converts the level of the first gate driving signal corresponding to the gate driving line GLn from the ground voltage GND to the six-fold voltage 6Vdd from the ground voltage GND to the six-fold voltage 6Vdd, and then converts the level of the first gate driving signal from the low voltage to the high voltage in sections from the time t1 to t6 To the ground voltage GND, and then change to the disable level VGL (negative five times the voltage -5Vdd). In addition, when the level of the first gate driving signal corresponding to the gate driving line GLn is changed to the disable level VGL, the second gate driving line GLn+1 is not in a floating state, but corresponds to the gate driving The level of the second gate driving signal of the line GLn+1 is the disable level VGL. In addition, when the level of the first gate driving signal corresponding to the gate driving line GLn is changed to the disable level VGL, the second gate driving line GLn+1 can still be in a floating state, as long as the level corresponding to the gate driving line GLn is in the floating state. Before the second gate driving signal of the pole driving line GLn+1 wants to drive the gate driving line GLn+1, the gate driving line GLn+1 may be in a non-floating state.

In FIG. 19 , the driving method according to the embodiment of the present invention first converts the level of the second gate driving signal corresponding to the gate driving line GLn+1 to the ground voltage GND at time t0, and makes the corresponding The level of the first gate driving signal on the gate driving line GLn is gradually changed from the disable level VGL (negative five times voltage -5Vdd) to the ground voltage GND, and then to the low voltage Vdd, and then gradually changed from the low voltage Vdd to the ground voltage GND. The enable level (six times the voltage of 6Vdd), then gradually changes to the ground voltage GND, then changes to the low negative voltage -Vdd, and then gradually changes from the low negative voltage -Vdd to the disable level VGL (negative five times pressure -5Vdd). In this way, the driving method of the present invention switches from low voltage to high voltage to charge the coupling capacitors between the gate driving lines in a time-division and segmental manner, thereby reducing the total current consumption of the coupling capacitors between the gate driving lines, thereby reducing the The total power consumption for driving the display panel 100 . In addition, switching from high voltage to low voltage in a time-sharing manner discharges the coupling capacitor, which can recycle the charge to further save power.

When the driving method of the present invention is applied to the coupling capacitance between the source driving line and the gate driving line of the display panel 100 , please refer to FIGS. 20 to 23 . FIGS. 20 to 23 are waveform diagrams of charging the two ends of the coupling capacitor Cs2g between the source driving line and the gate driving line by the driving method according to the embodiment of the present invention. The thick dotted line segment represents the voltage change of the gate drive line corresponding to one end of the coupling capacitor Cs2g, and the thick solid line segment represents the voltage change of the source drive line corresponding to the other end of the coupling capacitor Cs2g. 20 and 21 are examples of charging the coupling capacitor Cs2g with the driving method of the present invention when the level of the source driving signal corresponding to the source driving line is switched to the forward level. It can be seen from FIG. 20 and FIG. 21 that when the level of the source driving signal changes to the positive level, it can be performed after the level of the gate driving signal is changed from the disable level to the enable level, and so on. The total current consumption of the coupling capacitance between the gate driving line and the source driving line can be reduced.

FIG. 22 and FIG. 23 are examples of charging the coupling capacitor Cs2g by the driving method of the present invention when the level of the source driving signal of the source driving line is switched to the negative direction. It can be seen from FIG. 22 and FIG. 23 that when the level of the source driving signal changes to the negative level, it can be performed before the level of the gate driving signal is changed from the disable level to the enable level, so The total current consumption of the coupling capacitance between the gate driving line and the source driving line can be reduced.

In an embodiment of the present invention, the timing controller 108 can control the source driving module 106 to determine before or after the level of the gate driving signal changes to the enabling level according to the changing direction of the level of the source driving signal. inverting the levels of the source driving signals.

In addition, when the driving method of the embodiment of the present invention is applied to the driving circuit 102 , the waveform shown in FIG. 24 can be used to charge the coupling capacitor, so as to reduce the total current consumption of driving the display panel 100 . In detail, when the level of the gate driving signal corresponding to the source driving line is to be switched to the negative direction, the level can be changed first before the enabling interval of the gate driving signal corresponding to the gate driving line GLn, as shown in Fig. As shown in 24, before the enabling interval of the gate driving signal of the gate driving line GLn, the level of the source driving signal corresponding to the second terminal CN of the coupling capacitor is gradually changed from the ground voltage GND to the negative twice voltage. -2Vdd. In addition, in the enabling interval of the gate driving signal corresponding to the gate driving line GLn, the level of the source driving signal corresponding to the first terminal CP of the coupling capacitor is further sub-transformed from the ground voltage GND to the triple voltage. 3Vdd, so the total current consumption of the coupling capacitor of the display panel 100 can be reduced.

It should be noted that those skilled in the art can be appropriately applied to the display panel according to different requirements. For example, in the same cycle, the driving methods of the embodiments of FIGS. 10 and 11 can be used to charge and discharge the coupling capacitances between the source driving lines, and the combination is not limited and falls within the scope of the present invention.

To sum up, the present invention provides a driving method and a driving circuit thereof, which can charge the coupling capacitor of the display panel by switching the voltage, and the method of recovering the electric charge, so as to reduce the consumption charge of the coupling capacitor on the display panel, and further Reduce the total power consumption to drive the display panel.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (40)

1. A driving method for a display panel, characterized in that, comprising: generating a plurality of driving signals, and transmitting the driving signals to a plurality of driving lines of the display panel; The level of the first driving signal corresponding to a first driving signal and a second driving signal of two adjacent driving lines is changed from an initial level to a predetermined level, and the level of the first driving signal is When the bit changes, the level of the second driving signal is fixed. 2 . The driving method of claim 1 , wherein the initial level of the first driving signal is a first initial level, and the predetermined level of the first driving signal is a The first predetermined level, the level of the second driving signal changes from a second initial level to a second predetermined level, when the level of the second driving signal changes, the level of the first driving signal is changed. The level is fixed. 3. The driving method according to claim 2, wherein the absolute value of the first initial level is smaller than the absolute value of the first predetermined level, and the absolute value of the second initial level is lower than the absolute value of the first predetermined level the absolute value of the second predetermined level. 4 . The driving method according to claim 2 , wherein the second driving signal is in a period during which the level of the second driving signal transitions from the second initial level to the second predetermined level. 5 . When the level of the signal changes, the level of the first driving signal is fixed. 5 . The driving method according to claim 4 , wherein the level of the second driving signal is changed from the second predetermined level to the second initial level, and the level of the second driving signal is changed. 6 . Before the level transitions from the second predetermined level to the second initial level, it is converted to a discharge level, and the absolute value of the discharge level is smaller than the absolute value of the second predetermined level, and greater than the absolute value of the second initial level. 6 . The driving method of claim 1 , wherein the absolute value of the initial level is smaller than the absolute value of the predetermined level. 7 . 7 . The driving method according to claim 1 , wherein during the transition from the initial level to the predetermined level of the level of the first driving signal, the level of the first driving signal When changing, the level of the second driving signal is fixed. 8 . The driving method of claim 7 , wherein the level of the first driving signal is changed from the predetermined level to the initial level, and the level of the first driving signal is changed from the predetermined level to the initial level. 9 . Before the predetermined level is converted to the initial level, it is converted to a discharge level, and the absolute value of the discharge level is smaller than the absolute value of the predetermined level and greater than the absolute value of the initial level. 9. The driving method of claim 1, further comprising: Provide multiple supply voltages; selecting the supply voltages to generate the first driving signal, the level of the first driving signal is transitioned from the initial level to the predetermined level; and The supply voltages are selected to generate the second driving signal, and when the level of the first driving signal changes, the level of the second driving signal is fixed. 10 . The driving method of claim 1 , wherein the driving lines of the display panel comprise a plurality of source driving lines, the driving signals comprise a plurality of source driving signals, and the adjacent two The driving lines are adjacent two source driving lines, and the first driving signal and the second driving signal corresponding to the adjacent two source driving lines are a first source driving signal and a second source respectively. pole drive signal. 11 . The driving method of claim 10 , wherein after the level of a gate driving signal is changed to a uniform energy level, the level of the first source driving signal is changed in a forward direction to the desired level. 12 . the predetermined level. 12 . The driving method of claim 10 , wherein before the level of a gate driving signal is changed to an energy level, the level of the first source driving signal is changed to a negative direction to the desired level. 13 . the predetermined level. 13 . The driving method of claim 1 , wherein the driving lines of the display panel comprise a plurality of gate driving lines, the driving signals comprise a plurality of gate driving signals, and the adjacent two The driving lines are two adjacent gate driving lines, and the first driving signal and the second driving signal corresponding to the two adjacent gate driving lines are a first gate driving signal and a second gate driving signal respectively. pole drive signal. 14. A driving method for a display panel, comprising: generating a plurality of driving signals, and transmitting the driving signals to a plurality of driving lines of the display panel; Wherein, the level of a driving signal corresponding to a first driving line changes from an initial level to a predetermined level, and during the level changing period of the driving signal corresponding to the first driving line, adjacent to the first driving line A second driving line of a driving line is in a floating state. 15 . The driving method according to claim 14 , wherein the level of the driving signal corresponding to the first driving line is changed from the predetermined level to the initial level, and the level of the driving signal is 15 . 15 . Before the level transitions from the predetermined level to the initial level, it is converted to a discharge level, and the absolute value of the discharge level is smaller than the absolute value of the predetermined level and greater than the initial level the absolute value of . 16. The driving method of claim 14, further comprising: provide multiple supply voltages; and The supply voltages are selected to generate the driving signal corresponding to the first driving line, and the level of the driving signal is changed from the initial level to the predetermined level. 17 . The driving method of claim 14 , wherein the driving lines of the display panel comprise a plurality of gate driving lines, the driving signals comprise a plurality of gate driving signals, and the adjacent two The driving lines are two adjacent gate driving lines, and the driving signal corresponding to the first gate driving line is a gate driving signal. 18. A driving method for a display panel, comprising: generating a plurality of source driving signals, and transmitting the source driving signals to a plurality of source driving lines of the display panel; generating a plurality of gate driving signals, and transmitting the gate driving signals to a plurality of gate driving lines of the display panel; and According to the changing direction of the levels of the source driving signals, determining the level of changing the source driving signals before or after the level of at least one of the gate driving signals is changed to an energy level bit. 19 . The driving method of claim 18 , wherein after the level of at least one of the gate driving signals is changed to the enable level, the level of the source driving signals is changed to the enabling level. 20 . Bits are transformed in the positive direction. 20 . The driving method of claim 18 , wherein before the level of at least one of the gate driving signals changes to the enable level, the level of the source driving signals Bits are shifted in the negative direction. 21. A drive circuit for a display panel, characterized in that, comprising: a driving module, coupled to a plurality of driving lines of the display panel, generating a plurality of driving signals, and transmitting the driving signals to the driving lines; and a timing controller, coupled to the driving module, to control the driving module to generate the driving signals corresponding to the difference between a first driving signal and a second driving signal of the first driving signal of two adjacent driving lines The level changes from an initial level to a predetermined level, and when the level of the first driving signal changes, the level of the second driving signal is fixed. 22 . The driving circuit of claim 21 , wherein the initial level of the first driving signal is a first initial level, and the predetermined level of the first driving signal is a The first predetermined level, the level of the second driving signal changes from a second initial level to a second predetermined level, when the level of the second driving signal changes, the level of the first driving signal is changed. The level is fixed. 23. The driving circuit of claim 22, wherein the absolute value of the first initial level is less than the absolute value of the first predetermined level, and the absolute value of the second initial level is lower than the absolute value of the first predetermined level the absolute value of the second predetermined level. 24 . The driving circuit according to claim 22 , wherein the second driving signal changes from the second initial level to the second predetermined level during the period when the level of the second driving signal changes from the second initial level to the second predetermined level. 24 . When the level of the signal changes, the level of the first driving signal is fixed. 25 . The driving circuit of claim 24 , wherein the level of the second driving signal changes from the second predetermined level to the second initial level, and the level of the second driving signal is 25 . 25 . Before the level transitions from the second predetermined level to the second initial level, it is converted to a discharge level, and the absolute value of the discharge level is smaller than the absolute value of the second predetermined level, and greater than the absolute value of the second initial level. 26. The driving circuit of claim 21, wherein the absolute value of the initial level is smaller than the absolute value of the predetermined level. 27 . The driving circuit of claim 21 , wherein during the transition from the initial level to the predetermined level of the level of the first driving signal, the level of the first driving signal When changing, the level of the second driving signal is fixed. 28. The driving circuit of claim 27, wherein the level of the first driving signal is changed from the predetermined level to the initial level, and the level of the first driving signal is changed from the predetermined level to the initial level. Before the predetermined level is converted to the initial level, it is converted to a discharge level, and the absolute value of the discharge level is smaller than the absolute value of the predetermined level and greater than the absolute value of the initial level. 29. The driving circuit of claim 21, wherein the driving module further comprises: a first selection circuit, receiving a plurality of supply voltages and coupled to the timing controller, the timing controller controls the first selection circuit to select the supply voltages to generate the first driving signal, the first selection circuit The level of a driving signal is transitioned from the initial level to the predetermined level; and a second selection circuit, receiving the supply voltages and coupled to the timing controller, the timing controller controls the second selection circuit to select the supply voltages to generate the second driving signal, When the level of the first driving signal changes, the level of the second driving signal is fixed. 30. The driving circuit of claim 21, wherein the driving lines of the display panel comprise a plurality of source driving lines, and the driving signals generated by the driving module comprise a plurality of source driving signals , the two adjacent driving lines are adjacent two source driving lines, and the first driving signal and the second driving signal corresponding to the adjacent two source driving lines are respectively a first source driving signal and a second source drive signal, the drive module includes: A source driving circuit, coupled to the source driving lines and the timing controller, generates the source driving signals, and transmits the source driving signals to the source driving lines. 31 . The driving circuit of claim 30 , wherein after the level of a gate driving signal is changed to an energy level, the level of the first source driving signal is changed to a positive level to the desired level. 32 . the predetermined level. 32 . The driving circuit of claim 30 , wherein before the level of a gate driving signal is changed to a uniform energy level, the level of the first source driving signal is changed to a negative direction to the desired level. 33 . the predetermined level. 33. The driving circuit of claim 21, wherein the driving lines of the display panel comprise plural gate driving lines, and the driving signals generated by the driving module comprise plural gate driving signals , the two adjacent driving lines are adjacent two gate driving lines, and the first driving signal and the second driving signal corresponding to the two adjacent gate driving lines are respectively a first gate driving line signal and a second gate driving signal, the driving module includes: A gate driving circuit, coupled to the gate driving lines and the timing controller, generates the gate driving signals, and transmits the gate driving signals to the gate driving lines. 34. A drive circuit for a display panel, comprising: a driving module, coupled to a plurality of driving lines of the display panel, generating a plurality of driving signals, and transmitting the driving signals to the driving lines; and a timing controller, coupled to the driving module, controls the driving module to generate the driving signals, the level of a driving signal corresponding to a first driving line is changed from an initial level to a predetermined level, corresponding to During the level change of the driving signal of the first driving line, a second driving line adjacent to the first driving line is in a floating state. 35. The driving circuit of claim 34, wherein when the level of the driving signal corresponding to the first driving line changes from the predetermined level to the initial level, the level of the driving signal is Before the level transitions from the predetermined level to the initial level, it is converted to a discharge level, and the absolute value of the discharge level is smaller than the absolute value of the predetermined level and greater than the initial level the absolute value of . 36. The driving circuit of claim 34, wherein the driving module further comprises: a selection circuit, which receives a plurality of supply voltages and is coupled to the timing controller, the timing controller controls the selection circuit to select the supply voltages to generate the driving signal corresponding to the first driving line, the The level of the driving signal is changed from the initial level to the predetermined level. 37. The driving circuit of claim 34, wherein the driving lines of the display panel comprise plural gate driving lines, and the driving signals generated by the driving module comprise plural gate driving signals , the two adjacent driving lines are adjacent two gate driving lines, the driving signal corresponding to the first gate driving line is a gate driving signal, and the driving module includes: A gate driving circuit, coupled to the gate driving lines and the timing controller, generates the gate driving signals, and transmits the gate driving signals to the gate driving lines. 38. A drive circuit for a display panel, characterized in that, comprising: a source driving module, coupled to a plurality of source driving lines of the display panel, generating a plurality of source driving signals, and transmitting the source driving signals to the source driving lines; a gate driving module, coupled to a plurality of gate driving lines of the display panel, generating a plurality of gate driving signals, and transmitting the gate driving signals to the gate driving lines; and a timing controller, coupled to the source driving module and the gate driving module, and controlling the source driving module and the gate driving module to generate the source driving signals and the gate driving a signal, the timing controller determines to change the level of at least one of the gate driving signals before or after the level of at least one of the gate driving signals changes to a uniform energy level according to the changing direction of the levels of the source driving signals the level of some source drive signals. 39. The driving circuit of claim 38, wherein after the level of at least one of the gate driving signals is changed to the enable level, the level of the source driving signals is Bits are transformed in the positive direction. 40. The driving circuit of claim 38, wherein before the level of at least one of the gate driving signals is changed to the enable level, the level of the source driving signals is Bits are shifted in the negative direction.

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