KR20090113080A - Gate drive circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE: A gate drive circuit for a liquid crystal display device is provided to improve operation speed without increase channel width of a transistor by discharging with a charge transistor and a discharge transistor together. CONSTITUTION: In gate drivers(GD21-GD21n), an RS flip-flop outputting an output signal and an inverse signal according to a set signal and a reset signal. An OR-gate performs OR-operation of the inverse signal of the RS flip-flop and a gate signal of a next stage. A charge transistor outputs the gate signal to corresponding gage line of a liquid panel by the output of RS flip-flop and a clock signal for a charge period. A discharge transistor which is turned on by an output signal of the OR gate discharges a gate signal.

Description

 GATE DRIVE CIRCUIT FOR LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technique of a liquid crystal display device, and more particularly to a gate driving circuit of a liquid crystal display device adapted to improve the operation speed of the gate driver.

Recently, with the development of information technology (IT), the importance of the flat panel display device as a visual information transmission medium has been further emphasized, and low power consumption, thinning, light weight, and high quality are required to secure an improved competitiveness in the future. Liquid crystal display (LCD), which is a representative display device of flat panel display devices, displays images by using optical anisotropy of liquid crystals, and has advantages such as thin, small size, low power consumption, and high quality. It is widely applied to display devices of portable terminals.

Such a liquid crystal display device is a display device in which image information is individually supplied to liquid crystal pixels arranged in a matrix, and the light transmittance of the liquid crystal pixels is adjusted to display a desired image. Accordingly, the liquid crystal display includes a liquid crystal panel in which liquid crystal pixels, which are the smallest unit for implementing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. Since the LCD does not emit light by itself, a backlight unit is provided to supply light to the LCD. The driver includes a timing controller and a data driver and a gate driver.

FIG. 1 is a driving block diagram of a liquid crystal display according to the related art, and as shown therein, a gate control signal GDC and a data control signal DDC for controlling the driving of the gate driver 12 and the data driver 13. A timing controller 11 for outputting the digital video data RGB and reordering the digital video data RGB; A gate driver 12 supplying a gate signal to each gate line GL0 to GLn of the liquid crystal panel 14 in response to the gate control signal GDC; A data driver 13 supplying a pixel signal to each of the data lines DL1 to DLm of the liquid crystal panel 14 in response to the data control signal DDC; The liquid crystal panel 14 includes a liquid crystal cell driven by the gate signal and the pixel signal in a matrix form to display an image. The operation thereof will be described with reference to FIGS. 2 to 5.

The timing controller 11 may include a gate control signal GDC and a data driver 13 for controlling the gate driver 12 using the vertical / horizontal synchronization signals Hsync / Vsync and the clock signal CLK supplied from the system. Outputs a data control signal (DDC) for controlling. In addition, the timing controller 11 samples the digital pixel data RGB input from the system, rearranges the digital pixel data RGB, and supplies the same to the data driver 13.

The gate control signal GDC includes a gate start pulse GSP, a gate shift clock signal GSC, a gate out enable signal GOE, and the like. The data control signal DDC includes a source start pulse SSP and a source. The shift clock signal SSC, the source out enable signal SOE, the polarity signal POL, and the like.

The gate driver 12 sequentially supplies the gate signal to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 11, thereby corresponding thin film transistor TFT on the horizontal line. ) Are turned on. Accordingly, pixel signals supplied through the data lines DL1 to DLm are stored in the respective storage capacitors C _ST through the thin film transistors TFT.

In more detail, the gate driver 12 shifts the gate start pulse GSP according to the gate shift clock GSC to generate a shift pulse. The gate driver 12 supplies a gate signal consisting of gate on and off sections (signals) to the corresponding gate line GL in a horizontal period in response to the shift clock. In this case, the gate driver 12 supplies a gate-on signal only in an enable period in response to the gate-out enable signal GOE, and supplies a gate-off signal (gate low signal) in other periods.

The data driver 13 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray scale value in response to the data control signal DDC input from the timing controller 11. The pixel signal thus converted is supplied to the data lines DL1 to DLm on the liquid crystal panel 14.

The liquid crystal panel 14 is formed in each crossing portion of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC And a thin film transistor (TFT) connected to each of them. The thin film transistor TFT is turned on when the gate signal is supplied from the gate line GL, and supplies the pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when the gate off signal is supplied through the gate line GL to maintain the pixel signal charged in the liquid crystal cell C _LC .

The liquid crystal cell C _LC includes a pixel electrode connected to a common electrode and a thin film transistor TFT with a liquid crystal interposed therebetween. The liquid crystal cell C _LC further includes a storage capacitor C _ST so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor C _ST is formed between the pixel electrode and the previous gate line. In the liquid crystal cell C _LC , an arrangement state of liquid crystals having dielectric anisotropy varies according to pixel signals charged through the thin film transistor TFT, and light transmittance is adjusted accordingly to implement gradation.

The gate driver 12 includes a series of gate drivers GD11 to GD1n that are driven in a shift register manner as shown in FIG. 2, and is synchronized with the clock signals CLK1 to CLK4 supplied from the timing controller 11. The gate signals VGOUT [1] to VGOUT [N] are output at the same timing as in FIG. The gate lines GL1 to GLn on the liquid crystal panel 14 are driven by the gate signals VGOUT [1] to VGOUT [N] thus output. The operation of generating such gate signals VGOUT [1] to VGOUT [N] is repeated in units of frames.

FIG. 4 is a detailed circuit diagram of the gate drivers GD11 to GD1n. As illustrated therein, an RS flip-flop outputs a signal of logic opposite to two output terminals Q and QB according to a set signal and a reset signal. (FF1); It is connected in series between the terminal of the clock signal CLK and the ground terminal, and the gate is connected to the output terminal Q and the inverted output terminal QB of the RS flip-flop FF1, respectively. It consists of a charging transistor (T _PU ) and a discharge transistor (T _PD ) for generating (G [N]). The operation thereof will be described with reference to the timing diagram of FIG. 5.

In the t1 section, the gate signal G [N-1] of the previous stage is input 'high' to the set terminal S of the RS flip-flop FF21, and the voltage VM of the intermediate level is applied to the output terminal Q thereof. Is output, whereby the large-sized charging transistor T _PU serving as a buffer is turned on. The intermediate level voltage VM is a voltage V _DD -V _{TH obtained} by subtracting the threshold voltage of the input transistor from the supply voltage. At this time, the next gate signal G [N + 1] is input to the reset terminal R of the RS flip-flop FF1 as 'low' to output a 'low' signal to the inverting output terminal QB. As a result, the small size discharge transistor T _PD is turned off.

Thereafter, the clock signal CLK = CLK [1] is input as 'high' in the period t2. Accordingly, due to the coupling phenomenon of the parasitic capacitance C _gd between the gate and the drain of the charging transistor T _PU , the voltage of the output terminal Q is reduced to the voltage VM and the clock signal of the intermediate level. The voltage VGH of CLK is added to bootstrapping to a higher level voltage VH. Accordingly, the gate signal G [N] of the gate driver is output at the voltage level VGH of the clock signal CLK in the t2 period. The gate signal G [N] thus output is supplied to the corresponding gate line of the liquid crystal panel 94.

Thereafter, the clock signal CLK = CLK [1] is lowered to the 'low' level voltage VGL in a period t3, and the clock signal CLK = CLK [2] supplied to the next gate driver is' The voltage rises to the high level. At this time, the gate signal G [N-1] of the previous stage is input as 'low' to the set terminal S of the RS flip-flop FF1. Thus, the charging transistor T _PU is turned off.

At this time, the gate signal G [N + 1] of the next stage is inputted to the reset terminal R of the RS flip-flop FF1 as 'high' to output a 'high' signal to the inverted output terminal QB. As a result, the small size discharge transistor T _PD is turned on. Accordingly, the discharging operation of the gate signal G [N] is performed through the discharging transistor T _PD so that the potential of the corresponding gate line transitions to a 'low' level.

By the way, the charging transistors T _PU and the discharge transistors T _PD which are components of the series of gate drivers GD11 to GD1n constituting the gate driver 12 are designed as a-Si: H TFTs. Their mobility is very low.

Accordingly, the channel width of the charging transistor and the discharge transistor of the gate driving circuit of the conventional liquid crystal display device is required to be 1000 μm or more, but in reality, the installation space of the gate driving circuit is extremely limited for driving a high resolution and large area TFT LCD. There was a difficulty in implementing the channel width. For this reason, the conventional liquid crystal display device has a problem in that the gate line cannot be charged or discharged in a line time.

Accordingly, an object of the present invention is to perform the discharge function by using both the charging transistor and the discharge transistor as components of the gate driver, thereby improving the operation speed without widening the channel width of the charging transistor and the discharge transistor. It is to make it possible.

The present invention for achieving the above object, so that the discharge operation is performed through the charging transistor when the gate signal is discharged through the discharge transistor after outputting the gate signal to the gate line of the liquid crystal panel in a series of gate drivers. It is characterized in that to enable rapid discharge.

The gate driver includes the series of gate drivers, and the gate driver is embedded in the panel.

According to the present invention, when the gate driver of the liquid crystal display device outputs the gate signal to the gate line of the liquid crystal panel and discharges the gate signal through the discharge transistor, the discharge operation is also performed through the charging transistor, thereby enabling rapid discharge. As a result, the operation speed of the gate driver is improved.

Therefore, there is an effect that can contribute to the development of a high-resolution large area gate driver that requires high-speed operation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 is a gate driving circuit diagram of the liquid crystal display according to the present invention. As shown in FIG. 6, the gate signals VGOUT [1] to FIG. 6 are sequentially driven in synchronization with the clock signals CLK1 to CLK4. And a series of gate drivers GD21 to GD2n for outputting VGOUT [N], and discharging the gate signal through both the charging transistor and the discharge transistor of each of the gate drivers GD21 to GD2n in a discharge section. do.

7 is a detailed circuit diagram of each of the gate drivers GD21 to GD2n according to the present invention. As shown therein, a signal of logic opposite to the two output terminals Q and QB in accordance with the set signal and the reset signal is shown. An RS flip-flop FF1 for outputting; An oar gate OR1 that performs an ord operation on the signal output from the inverted output terminal QB of the RS flip-flop FF1 and the next gate signal G [N + 1]; The gate signal G [N] is output to the corresponding gate line of the liquid crystal panel by the signal and the clock signal output from the output terminal Q of the RS flip-flop FF1 in the charging section, and the turn-on state is maintained even in the discharge section. A charging transistor T _PUD for holding and discharging the gate signal G [N]; A discharge transistor T _PD is turned on by an output signal of the OR gate OR1 in a discharge section to discharge the gate signal G [N].

Referring to Figures 8 to 12 attached to the operation of the present invention configured as described above in detail as follows.

In the present invention, as shown in Fig. 6, a series of outputting gate signals VGOUT [1] to VGOUT [N] to each gate line of the liquid crystal panel while driving like a shift register in synchronization with clock signals CLK1 to CLK4. In implementing the gate drivers GD21 to GD2n, the gate signals are discharged through both the charging transistors and the discharge transistors of the gate drivers GD21 to GD2n in the discharge section to enable rapid discharge.

To this end, the gate drivers GD21 to GD2n are implemented as shown in FIG. 7, and the operation thereof will be described with reference to the timing diagram of FIG. 8.

First, the gate signal G [N-1] of the previous stage is input as 'high' to the set terminal S of the RS flip-flop FF1 in the period t1, and the voltage of the intermediate level is applied to the output terminal Q thereof. VM) is output, whereby the large-sized charging transistor T _PUD is turned on. However, since the clock signal CLK = CLK [1] is still input as 'low', the gate signal G [N] is output as the voltage VGL having the 'low' level. The intermediate level voltage VM is a voltage V _DD -V _{TH obtained} by subtracting the threshold voltage of the input transistor from the supply voltage.

At this time, the reset signal RESET is inputted to the reset terminal R of the RS flip-flop FF21 as 'low', and a 'low' signal is output to the inverted output terminal QB thereof. Since the signal G [N + 1] is output 'low', a 'low' signal is output to the output terminal Gd of the OR gate OR1, so that the small-sized discharge transistor T _D is turned off. Becomes

Thereafter, the clock signal CLK is input as 'high' in a period t2. Accordingly, due to the coupling phenomenon of the parasitic capacitance C _gd between the gate and the drain of the charging transistor T _PUD , the voltage of the output terminal Q is set to the intermediate level voltage VM and the clock signal CLK. ) Is bootstrapping to a higher level voltage (VH) plus a voltage (VGH). Accordingly, the gate signal G [N] is output at the voltage level VGH of the clock signal CLK from the corresponding gate driver in the t2 period.

Thereafter, the clock signal CLK drops to the 'low' level voltage VGL in a period t3 and is supplied to the gate of the charging transistor T _PUD due to the coupling phenomenon of the parasitic capacitance C _gd . The voltage to be lowered to the intermediate level voltage VM maintains that level.

Therefore, at this time, the charging transistor T _PUD is maintained in a turn-on state, so that the gate signal G [N] is 'low' level voltage VGL through the charging transistor T _PUD . Discharged.

At the same time, the gate signal G [N + 1] is output as 'high' in the next gate driver to which the clock signal CLK [2] is supplied, thereby outputting the output terminal Gd of the OR gate OR1. 'High' is printed. Accordingly, since the discharge transistor T _PD is also turned on, the discharge operation of the gate signal G [N] is performed through this.

As described above, since the discharging operation of the gate signal G [N] is simultaneously performed through the charging transistor T _PUD and the discharging transistor T _PD in the discharge period t3, one discharge is performed as in the usual case. Compared to the discharge operation performed through the transistor T _PD , the discharge operation proceeds quickly, and the falling time of the gate signal G [N] is shortened by that amount.

Thereafter, the gate signal G [N + 2] is input as 'high' from the gate driver of the second stage to the reset terminal R of the RS flip-flop FF1 in a period t4. Accordingly, a 'low' signal is output to the output terminal Q of the RS flip-flop FF1 to turn off the charging transistor T _PUD , but the 'high' signal continues to the inverting output terminal QB. Is outputted, whereby 'high' is continuously output from the oragate OR1. Accordingly, the discharge transistor T _PD is kept turned on to continue the discharge operation of the gate signal G [N].

FIG. 9 is a detailed circuit diagram illustrating an embodiment of the gate driver of FIG. 7, and the RS flip-flop FF1 composed of transistors T1-T7 as shown therein; An OR gate OR1 composed of transistors T8-T15; A gate signal output section 71 composed of a charging transistor T _PUD and a discharge transistor T _PD is included.

In the RS flip-flop FF1, the transistor T1 is turned on when the start signal VST corresponding to the gate signal G [N-1] of the previous stage is input as 'high' in FIG. 7. A high signal is output to the output terminal Q. Subsequently, when the reset signal RESET is input 'high', the transistor T3 is turned on so that the signal of the output terminal Q is muted to the ground terminal through the transistor T3. ) Becomes the 'low' state. At this time, since the transistor T5 is turned off by the 'low' signal output from the output terminal Q, the 'high' signal is supplied to the gate of the transistor T6 through the diode-type transistor T4 and the transistor ( T6) is turned on. At this time, the start signal VST is input as 'low' and the transistor T7 is turned off. Accordingly, a 'high' signal is output to the inverting output terminal QB through the transistor T6.

In the OR gate OR1, the output signal of the inverted output terminal QB of the RS flip-flop FF1 is input 'high' so that the transistor T9 is turned on or the gate signal G [N of the next stage is turned on. +1]) is input as 'high' and the transistor T10 is turned on, thereby turning off the transistors T12 and T15. At this time, a 'high' signal is supplied to the gate of the transistor T13 through the diode-type transistor T11, and the transistor T13 is turned on. Accordingly, a 'high' signal is output to the output terminal Gd through the transistor T13.

The gate signal output unit 71 operates in the same manner as in FIG. That is, in the charging mode, the charging transistor T _PUD is turned on by the signal of the output terminal QB of the RS flip-flop FF1 to output the gate signal G [N] to the corresponding gate line of the liquid crystal panel. . In the discharge mode, the discharge transistor T _PD is turned on by the output signal of the OR gate OR1, and the gate signal G [N] is discharged through the discharge transistor T _PD . The transistor T _PUD also maintains a turn-on state, whereby a discharge operation is performed.

FIG. 10 is a detailed circuit diagram illustrating another embodiment of the gate driver of FIG. 7, which includes an RS flip-flop FF1 composed of transistors T1-T5; An oar gate OR1 composed of transistors T6-T10; A gate signal output section 71 composed of a charging transistor T _PUD and a discharge transistor T _PD is included. When FIG. 10 is compared with FIG. 9, the RS flip-flop FF1 and the OR gate OR1 are simply configured, and the current consumption is small.

In the RS flip-flop FF1, when the start signal VST corresponding to the gate signal G [N-1] of the previous stage is input as 'high' in FIG. 7, the transistor T1 is turned on. The high signal is output to the output terminal Q. Subsequently, when the reset signal RESET is input as 'high', the transistor T3 is turned on so that the signal of the output terminal Q is muted to the ground terminal through the transistor T3. ) Becomes the 'low' state. At this time, since the transistor T5 is turned off by the 'low' signal output from the output terminal Q, the 'high' signal is output to the inverting output terminal QB through the diode-type transistor T4.

In the OR gate OR1, the output signal of the inverted output terminal QB of the RS flip-flop FF1 is input 'high' so that the transistor T7 is turned on or the gate signal G [N of the next stage is turned on. +1]) is input as 'high' and the transistor T8 is turned on, thereby turning off the transistor T10. At this time, a 'high' signal is output to the output terminal Gd through the diode transistor T9.

The gate signal output unit 71 operates in the same manner as in FIGS. 7 and 9.

FIG. 11 shows operation simulation results of the gate drivers GD21 to GD2n operating as described above, and the voltages of the respective output terminals Q node, QB node, and Gd node are different from those of the timing shown in FIG. As shown in the figure, it can be seen that the gate signal VGOUT [N] is quickly discharged in the discharge section.

FIG. 12 shows simulation results of the output characteristics of the gate drivers GD21 to GD2n operating as described above. The gate signal G1 output from the conventional gate driver is output from the gate driver according to the present invention. Compared with G2), the falling time is much shorter.

1 is a driving block diagram of a liquid crystal display device according to the prior art.

FIG. 2 is a detailed block diagram of the gate driver of FIG. 1. FIG.

3 is a waveform diagram of each part in FIG.

4 is a circuit diagram of the gate driver in FIG.

5 is a timing diagram of signals output from respective parts of FIG. 4.

6 is a block diagram of a gate driving circuit according to the present invention;

7 is a circuit diagram of the gate driver in FIG.

8 is a waveform diagram of a signal output from each part of FIG. 7;

FIG. 9 is a detailed circuit diagram illustrating an implementation of the gate driver of FIG. 7. FIG.

FIG. 10 is a detailed circuit diagram illustrating another embodiment of the gate driver of FIG. 7. FIG.

11 is a waveform diagram showing a simulation result for a gate driving circuit according to the present invention.

12 is a comparison waveform diagram of an output signal of a gate driver in the present invention.

*** Description of the symbols for the main parts of the drawings ***

GD21-GD2n: Gate Driver FF1: RS Flip-Flop

OR1: OA gate 71: gate signal output unit

Claims (8)

It comprises a series of gate drivers for outputting a gate signal to each gate line of the liquid crystal panel while sequentially driving in synchronization with the input clock signal, and discharges through both the charging transistor and the discharge transistor when the gate signal is discharged. A gate driving circuit of a liquid crystal display device, characterized in that. The gate driver of claim 1, wherein the gate driver An RS flip-flop for outputting an output signal and an inverted output signal according to the set signal and the reset signal; An oar gate that performs an OR operation on the inverted output signal of the RS flip-flop and the next gate signal; A charging transistor for outputting a gate signal to a corresponding gate line of the liquid crystal panel by the output signal and the clock signal of the RS flip-flop in a charging section, and discharging the gate signal by maintaining a turn-on state even in a discharge section; And a discharge transistor which is turned on by an output signal of the ora gate in a discharge section and discharges the gate signal. The gate driving circuit of claim 1, wherein the charging transistor is turned on by a voltage of an intermediate level output from the RS flip-flop during a discharge period to perform a discharge function. 4. The gate driving circuit of claim 3, wherein the intermediate level voltage is a voltage obtained by subtracting a threshold voltage of an input terminal transistor from a supply voltage. The method of claim 2, wherein the RS flip-flop The power supply terminal VGH is connected to the output terminal Q through the transistor T1, and its connection point is connected to the ground terminal through transistors T2 and T3 connected in parallel, respectively, and the power supply terminal VGH Is connected to the gate of the transistor T6 through the diode-type transistor T4, and its connection point is connected to the ground terminal through the transistor T5 connected to the output terminal Q, and the power supply terminal VGH. Is connected to the inverting output terminal QB and the gate of the transistor T2 through the transistor T6, and its connection point is connected to the ground terminal through the transistor T7, and the start signal terminal VST is connected to the transistor. And a reset terminal (RESET) connected to the gates of the transistor (T3). The transistor flip-flop of claim 2, wherein the power supply terminal VGH is commonly connected to the gate of the output terminal Q and the transistor T5 through the transistor T1, and the connection point thereof is a transistor T2 connected in parallel; The power supply terminal VGH is connected to the ground terminal of the transistor T4 through the diode-type transistor T4, and the connection point thereof is connected to the ground terminal through the transistor T3. A terminal connected to the ground terminal through T5, a start signal terminal VST is connected to the gate of the transistor T1, and a reset terminal RESET is connected to the gate of the transistor T3. Gate driving circuit of liquid crystal display device. The power supply terminal VGH is connected to the gates of the transistors T12 and T15 through a transistor T8 having a gate connected to the output terminal Q, and the connection point of the oragate is a gate. Is connected to the ground terminal through transistors T9 and T10 respectively connected to the inverting output terminal QB and the next gate terminal G [N + 1], and the power supply terminal VGH is diode type. The transistor T11 is connected to the gate of the transistor T13, and its connection point is connected to the ground terminal through the transistor T12, and the power supply terminal VGH is connected to the output terminal Gd through the transistor T13. And a connection point thereof is connected to a ground terminal through the transistor (T15). 2. The OR gate of claim 1, wherein the power supply terminal VGH is connected to the gate of the transistor T10 through a transistor T6 having a gate connected to the output terminal Q, and the connection point thereof is connected to the inverted output terminal ( The transistors T7 and T8 connected to QB) and the next gate terminal G [N + 1], respectively, are connected to the ground terminal, and the power supply terminal VGH is connected to the diode transistor T9. And a connection point thereof is connected to a ground terminal through the transistor (T10).

Images