KR20090090657A - Driving apparatus for liquid crystal display device - Google Patents

Abstract

A driving apparatus for liquid crystal display device is provided to prevent an image sticking of the liquid crystal panel by displaying the pixel signal of one frame in a certain cycle in horizontal or the vertical direction. The driving apparatus for liquid crystal display device comprises the timing controller(10), and the gate driving unit(20) and data driver(30). The timing controller outputs pixel data of one frame among the odd number and even frames in case of printing out the gate control signal(GDC), and data control signal(DDC) and pixel data(RGB). The timing controller outputs pixel data shifted in horizontal or the vertical direction among the odd number and even frames. The gate driving unit supplies the scan pulse to each of the gate line(GL1~GLn) of the liquid crystal panel in the control lower part of the gate control signal. The data driver outputs the pixel signal shifted in horizontal or the vertical direction among the odd number and even frames.

Description

DRIVING APPARATUS FOR LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technology of a liquid crystal display device, and more particularly, to driving a liquid crystal display device suitable for preventing occurrence of an afterimage or a yogore phenomenon due to continuous supply of two or more pixel signals having different levels between two adjacent pixels. Relates to a device.

Recently, with the development of information technology (IT), the importance of the flat panel display device as a visual information transmission medium has been further emphasized, and low power consumption, thinning, light weight, and high quality are required to secure improved competitiveness in the future.

A liquid crystal display (LCD), which is a typical display device of a flat panel display device, is an apparatus for displaying an image using optical anisotropy of liquid crystal, and has advantages such as thin, small size, low power consumption, and high quality.

Such a liquid crystal display device is a display device in which image information is individually supplied to pixels arranged in a matrix, and a desired image is displayed by adjusting light transmittance of the pixels. Accordingly, the liquid crystal display includes a liquid crystal panel in which pixels, which are the smallest unit for implementing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. Since the LCD does not emit light by itself, a backlight unit is provided to supply light to the LCD. The driver includes a timing controller and a data driver and a gate driver.

In general, the gate-on signal is sequentially output to each gate line on the liquid crystal panel so that the switching transistors on the corresponding horizontal line are turned on at that time, and the pixel signal supplied through the data line is stored in the storage capacitor through the transistors to form a liquid crystal. Supplied to the cell. Thereafter, the gate off signal is supplied to turn off the transistors on the horizontal line, but the pixel signal is maintained by the storage capacitor for one frame, thereby displaying an image of one frame.

In order to continuously supply two or more different pixel signals of different sizes to two adjacent pixels in order to display a grid-like or fixed pattern image on the liquid crystal panel, line afterimage and line bleeding (yogore) phenomenon appear. When described in more detail with reference to the following.

FIG. 1 illustrates a part of a liquid crystal panel in which black and white lattice-shaped images are displayed, wherein first and third regions REG1 and REG3 are regions in which black is displayed and second and fourth regions. The regions REG2 and REG4 are regions in which white is displayed. In this case, the gray level pixel signal for displaying black is continuously supplied to the first and third regions REG1 and REG3 for several frames, and the second and fourth regions REG2 and REG4 are supplied. The gray level pixel signal for displaying white is continuously supplied for several frames.

When switching to another screen in such a state, afterimages and line spreads on the boundary surfaces of the first and fourth regions REG1 and REG4 and the boundary surfaces of the second and fourth regions REG2 and REG4 (yogore). The phenomenon appears. Similarly, a line residual image and line bleeding (yogore) phenomenon appear on the interface between the first and second regions REG1 and REG2 and the boundary between the third and fourth regions REG3 and REG4.

As described above, in the conventional liquid crystal display device, when displaying an image having a lattice shape or a fixed pattern on the liquid crystal panel, a pixel signal having a large level difference is continuously supplied to the pixels of the corresponding area by two or more frames, thereby switching to another screen. At the moment, there was a problem that the afterimage or bleeding (yogore) phenomenon appears.

Accordingly, an object of the present invention is to output a pixel signal of one frame in a fixed form, instead of outputting a fixed pixel signal in a fixed form when displaying an image of a lattice shape or a fixed pattern on a liquid crystal panel of a liquid crystal display device. This is to prevent the phenomenon from occurring.

According to the present invention for achieving the above object, in outputting the digital pixel data while outputting the gate control signal and the data control signal, the pixel data of the odd frame is output as it is, and the pixel data of the even frame is vertical. And a timing controller shifting the pixel by a predetermined pixel in the horizontal direction and outputting the shifted pixel. A gate driver supplying scan pulses to the gate lines of the liquid crystal panel under the control of the gate control signal; In supplying a pixel signal to each data line of the liquid crystal panel under the control of the data control signal, a data driver for outputting pixel signals of odd frames as they are and shifting pixel signals of even frames in the vertical and horizontal directions. It is characterized by including the configuration.

In the present invention, when displaying an image of a lattice shape or a fixed pattern on a liquid crystal panel of a liquid crystal display device, the pixel signals of each frame are not output in a fixed form, but are shifted and displayed in a horizontal or vertical direction at a predetermined period, thereby providing a line. It is effective to prevent afterimages or line bleeding.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing an embodiment of a driving apparatus of a liquid crystal display according to the present invention. As shown in FIG. 2, a gate control signal for controlling the driving of the gate driver 20 and the data driver 30 is shown. GDC) and data control signal DDC, and outputs the pixel data RGB of odd frame as it is and outputs the pixel data of even frame as it is, when sampling and rearranging digital pixel data RGB. A timing controller 10 for shifting and outputting RGB in the vertical and horizontal directions; A gate driver 20 for supplying scan pulses to the gate lines GL1 to GLn of the liquid crystal panel 40 under the control of the gate control signal GDC; In supplying pixel signals to the data lines DL1 to DLm of the liquid crystal panel 40 under the control of the data control signal DDC, the pixel signals of odd frames are output as they are, and the pixel signals of even frames are vertical. And a data driver 30 which shifts and outputs in the horizontal direction. The LCD panel 40 includes a liquid crystal cell driven by the scan pulse and the pixel signal in a matrix form to display an image.

The timing controller 10 includes a vertical shift unit 11A for outputting pixel data RGB of an odd frame as it is and shifting the pixel data RGB of an even frame by horizontal lines in a vertical direction; And a data processor 11 configured to output pixel data RGB of an odd frame as it is and shift the pixel data RGB of an even frame by one pixel in a horizontal direction. do.

When described in detail with reference to Figures 3 to 7 attached to the operation of the present invention configured as described above are as follows.

The timing controller 10 may include a gate control signal GDC and a data driver 30 for controlling the gate driver 20 using the vertical / horizontal synchronization signals Hsync / Vsync and the clock signal CLK supplied from the system. Outputs a data control signal (DDC) for controlling. In addition, the timing controller 10 samples the digital pixel data RGB input from the system, rearranges the digital pixel data RGB, and supplies the same to the data driver 30.

Here, the gate control signal GDC means a gate start pulse GSP, a gate shift clock signal GSC, and a gate out enable signal GOE, and the data control signal DDC means a source start pulse SSP, The source shift clock signal SSC, the source out enable signal SOE, and the polarity signal POL.

The gate driver 20 sequentially supplies the gate signals to the gate lines GL1 to GLn under the control of the gate control signal GDC input from the timing controller 10, thereby corresponding thin film transistors TFT on the horizontal line are provided. ) Are turned on. Accordingly, pixel signals supplied through the data lines DL1 to DLm are stored in the respective storage capacitors C _ST through the thin film transistors TFT.

In more detail, the gate driver 20 shifts the gate start pulse GSP according to a gate shift clock signal GSC to generate a shift pulse. The gate driver 20 supplies a gate signal consisting of gate on and off sections (signals) to the corresponding gate line GL in a horizontal period in response to the shift clock signal. In this case, the gate driver 20 supplies a gate-on signal only in an enable period in response to the gate-out enable signal GOE, and supplies a gate-off signal (gate low signal) in other periods.

The data driver 30 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray scale value under the control of the data control signal DDC input from the timing controller 10. The pixel signal thus converted is supplied to the data lines DL1 to DLm on the liquid crystal panel 40.

In more detail, the data driver 30 generates the sampling signal by shifting the source start pulse SSP according to the source shift clock signal SSC. Subsequently, the data driver 30 sequentially inputs and latches the pixel data RGB by a predetermined unit in response to the sampling signal. The data driver 30 converts the latched pixel data RGB for one line into an analog pixel signal and supplies the same to the data lines DL1 to DLm.

The liquid crystal panel 40 is formed in each crossing portion of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC Thin film transistors (TFTs) connected to the respective transistors.

The thin film transistor TFT is turned on when the gate signal is supplied from the gate line GL, and supplies the pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when the gate off signal is supplied through the gate line GL to maintain the pixel signal charged in the liquid crystal cell C _LC . The liquid crystal cell C _LC includes a pixel electrode connected to a common electrode and a thin film transistor TFT with a liquid crystal interposed therebetween. The liquid crystal cell C _LC further includes a storage capacitor C _ST so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor C _ST is formed between the pixel electrode and the previous gate line. In the liquid crystal cell C _LC , an arrangement state of liquid crystals having dielectric anisotropy varies according to pixel signals charged through the thin film transistor TFT, and light transmittance is adjusted accordingly to implement gradation.

Meanwhile, in the present invention, when a pixel signal having a large level difference is continuously supplied for two or more frames in order to display a lattice shape or a fixed pattern on the liquid crystal panel 40, a line afterimage or a line bleeding phenomenon occurs. In order to prevent this, the pixel signals are shifted and displayed at predetermined intervals. The shift process will be described in more detail as follows.

The data processor 11 of the timing controller 10 outputs the pixel data RGB of one frame of an odd frame or an even frame as it is, and shifts the pixel data RGB of another frame in a vertical and horizontal direction. For example, the pixel data RGB of the odd frame is output as it is, and the pixel data RGB of the even frame is shifted and output in the vertical and horizontal directions. The shift method may be various. In this embodiment, the shift is performed at the frame period between positions shifted by one pixel (one pixel in the diagonal direction) in the horizontal and vertical directions from the original position.

In this case, the data processing unit 11 of the timing controller 10 outputs the pixel data RGB as shown in FIGS. 3A and 3B. That is, the data processor 11 sequentially outputs pixel data RGB of an odd frame in synchronization with the data enable signal DE as shown in (a) of FIG. 3.

In addition, the vertical shifter 11A of the data processor 11 delays the pixel data RGB of even frames by one horizontal line as shown in FIG. 3B and then horizontally in synchronization with the data enable signal DE. Output sequentially line by line.

In this case, the vertical shifter 11A of the data processor 11 inserts black data into the first horizontal line of an even frame and outputs the black data, and outputs pixel data RGB of each horizontal line to a second horizontal line. In order from the output. In other words, the pixel data RGB of the first horizontal line is output to the second horizontal line, and the pixel data RGB of the second horizontal line is output to the third horizontal line. do.

4 and 5 illustrate an example in which the vertical shift unit 11A processes pixel data RGB by using a line memory. The pixel data RGB of odd frames is illustrated in FIGS. 4A and 4B. As shown in b), the output is performed in a form that is not shifted in the vertical direction, and the pixel data RGB of even frames is written and read as shown in FIGS. 5A and 5B. Output in the form of shifted bit by bit.

That is, the vertical shift unit 11A writes / reads the pixel data RGB of the odd frame through the first and second line memories, and outputs the first data as shown in FIGS. 4A and 4B. When the pixel data RGB of the horizontal line is written to the first line memory, and then the pixel data RGB of the second horizontal line is written to the second line memory, the pixels of the first horizontal line written to the first line memory are written. Reads and outputs the data RGB, and when the pixel data RGB of the third horizontal line is written to the first line memory, the pixel data RGB of the second horizontal line written to the second line memory is read out. The pixel data RGB of the fourth horizontal line by reading the pixel data RGB of the fourth horizontal line and reading the pixel data RGB of the third horizontal line written in the first line memory. RGB). Therefore, the pixel data RGB is output in a form not shifted in the vertical direction.

However, the vertical shift unit 11A outputs pixel data RGB of even frames by shifting one horizontal line in the vertical direction using three line memories. That is, as shown in FIGS. 5A and 5B, the pixel data RGB of the first and second horizontal lines is sequentially written to the first and second line memories, and then the pixel data RGB of the third horizontal line is written. Is written to the third line memory, the pixel data RGB of the first horizontal line written in the first line memory is read and output, and the pixel data RGB of the fourth horizontal line is written to the first line memory. When the pixel data RGB of the second horizontal line written in the second line memory is read out, and the pixel data RGB of the fifth horizontal line is written into the second line memory. The pixel data RGB of each horizontal line is output by reading and outputting the pixel data RGB of the third horizontal line.

FIG. 6 is a liquid crystal panel 40 showing that the pixel data RGB of a lattice shape or a fixed pattern is output by one vertical line shift in the vertical direction by the vertical shifter 11A of the data processor 11. An illustration of the.

The horizontal shifter 11B of the data processor 11 shifts the pixel data RGB output by the vertical shifter 11A through the above process by one pixel in the horizontal direction.

Correspondingly, the data driver 30 outputs the pixel signals of odd frames without shifting them in the horizontal and vertical directions, and outputs the pixel signals of even frames by shifting one horizontal line in the vertical direction and in the horizontal direction. The output is shifted by one pixel.

7 (a) and 7 (b) show an embodiment of outputting a pixel signal from the data driver 30.

That is, FIG. 7A illustrates an example in which the data driver 30 is implemented as one data driving integrated device 30A. In this case, the pixel driver of the odd frame is output as it is without shifting in the horizontal direction. An example is shown.

FIG. 7B illustrates an example in which the data driver 30 is implemented with three data driving integrated devices 30A, 30B, and 30C. In this case, the pixel signals of even frames are horizontally aligned. Shows an example of sequentially shifting output by 1 pixel.

In other words, since the pixel signals of the even frames output from the data driving integrated device 30A are shifted by one channel, the pixel signals of the last channel 720 are output to the first channel of the next data driving integrated device 30B. Similarly, since the pixel signal of an even frame output from the data driving integrated device 30B is shifted by one channel, the pixel signal of the last channel 720 is output to the first channel of the next data driving integrated device 30C. Since the pixel signals of the even frames output from the driving integrated device 30C are shifted by one channel, the pixel signals of the last channel 720 are output to the first channel of the data driving integrated device 30A.

1 is an exemplary view showing a part of a liquid crystal panel in which black and white lattice-shaped images are displayed.

2 is a block diagram of a driving device of a liquid crystal display device according to the present invention;

3A is a waveform diagram of a data enable signal showing that pixel data of an odd frame is output in an unshifted form;

3B is a waveform diagram of a data enable signal showing that pixel data of an even frame is output by one horizontal line shifted form;

4A and 4B are waveform diagrams of data enable signals showing write / lead timing of pixel data output in an unshifted form;

5A and 5B are waveform diagrams of data enable signals showing write / lead timing of pixel data output in the form of one horizontal line shift in the vertical direction.

6 is an exemplary diagram showing that pixel data of a lattice shape or a fixed pattern is output in the form of one horizontal line shift in a vertical direction.

Fig. 7A is a schematic diagram of a data driving integrated device showing output as it is without shifting pixel signals of odd frames in the horizontal direction.

FIG. 7B is a schematic diagram of a data driving integrated device illustrating an example in which pixel signals of even frames are sequentially shifted and output by one pixel in a horizontal direction; FIG.

*** Description of the symbols for the main parts of the drawings ***

10: timing controller 11: data processing unit

11A: vertical shift portion 11B: horizontal shift portion

12: control signal processor 20: gate driver

30: data driver 40: liquid crystal panel

Claims (6)

In outputting the gate control signal and the data control signal, and in outputting the digital pixel data, the pixel data of one frame of the odd frame or the even frame is output as it is, and the pixel data of the other frame is predetermined in the vertical and horizontal directions. A timing controller which shifts and outputs the pixel; A gate driver supplying scan pulses to the gate lines of the liquid crystal panel under the control of the gate control signal; In the case of supplying a pixel signal to each data line of the liquid crystal panel under the control of the data control signal, data for outputting the pixel signal of the one frame as it is, and shifting the pixel signal of the other frame in the vertical and horizontal directions and outputting the data. A drive device for a liquid crystal display device comprising a drive unit. The apparatus of claim 1, wherein one frame is an odd frame and the other frame is an even frame. The apparatus of claim 1, wherein the timing controller is configured to insert black data into the shifted first horizontal line and to output the black data. The method of claim 1, wherein the timing controller is A vertical shift unit for outputting the pixel data of the one frame as it is and shifting the pixel data of the other frame by one horizontal line in a vertical direction; And a horizontal shift unit for outputting the pixel data of the one frame as it is and shifting the pixel data of the other frame by one pixel in a horizontal direction. The method of claim 1, wherein the timing controller sequentially writes the pixel data of the first and second horizontal lines to the first and second line memories, and then writes the pixel data of the third horizontal line to the third line memory. When the pixel data of the first horizontal line written in the line memory is read and output, and the pixel data of the fourth horizontal line is written into the first line memory, the pixel data of the second horizontal line written in the second line memory is written. And driving the pixel data by one horizontal line in a read-out manner. The data driver of claim 1, wherein when the data driver is configured of a plurality of data driver integrated devices, pixel signals of an arbitrary data driver integrated device are horizontally shifted by one pixel so that the pixel signal of the last channel is next driven. A drive device for a liquid crystal display device, which is output to the first channel of the device.

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