KR101511546B1 - Liquid Crystal Display and Driving Method Thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a method of driving the same that reduce the number of swings of a common voltage and reduce power consumption of a data driving circuit in a liquid crystal display device driven by a line inversion method.

The liquid crystal display device includes a liquid crystal display panel in which a plurality of gate lines, a plurality of data lines intersecting the gate lines, a common electrode, and pixel electrodes are formed; A scan pulse is sequentially supplied to a first group of gate lines including first gate lines for each frame period and a second group of gate lines including a gate line arranged for each of the first gate lines, To a gate driving circuit; After supplying a data voltage of the first polarity to the data lines in synchronization with the scan pulses supplied to the first gate line group, the data lines are supplied to the data lines in synchronization with the scan pulses supplied to the second gate line group A data driving circuit for supplying a data voltage of a second polarity; A timing controller for controlling the operation timing of the driving circuits and generating a polarity control signal for controlling a polarity of a data voltage to be supplied to the data lines; And a common voltage generator for supplying a common voltage to the common electrode with a polarity opposite to the polarity of the data voltage.

Description

[0001] The present invention relates to a liquid crystal display device,

1 is a view schematically showing a liquid crystal cell included in a conventional liquid crystal display panel.

2 is a view showing a part of a liquid crystal display panel driven by a conventional line-inversion method;

3 is a waveform diagram of a common voltage supplied in synchronization with a data voltage in a conventional line-inversion method.

4 is a block diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

5 is an internal configuration diagram of the timing controller of FIG.

FIG. 6 is an internal configuration view of the gate drive circuit of FIG. 4;

7 is a waveform diagram of a scan pulse generated in FIG.

8 is an internal configuration diagram of the data driving circuit of FIG.

9 is a circuit diagram showing the digital / analog converter of FIG. 8;

10 is a waveform diagram of a polarity control signal supplied to the data driving circuit of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device driven by a line inversion method according to an embodiment of the present invention.

12 is a waveform diagram for explaining that the number of swings of the common voltage remarkably decreases.

13 is a block diagram illustrating a liquid crystal display device according to another embodiment of the present invention.

FIG. 14 is an internal configuration diagram of the timing controller of FIG. 13; FIG.

Fig. 15 is a waveform diagram of a polarity control signal supplied to the data driving circuit of Fig. 13; Fig.

16 is an internal configuration diagram of the gate drive circuit shown in Fig.

17A and 17B are waveform diagrams of scan pulses generated when an input image is a moving image and a still image, respectively.

18 is a flowchart illustrating a method of driving a liquid crystal display according to another embodiment of the present invention.

DESCRIPTION OF THE RELATED ART [0002]

110, 210: timing controller 112, 212:

114, 214: control signal generator 120, 220:

122: shift register 123: first latch array

124: second latch array 125: gamma compensation voltage generator

126: digital-to-analog converter 127: charge share circuit

128: output circuit 130, 230: gate drive circuit

132,234: Shift register array 134,236: Level shift array

Buffer array 232: Multiplexer array

260: Image analysis section

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display device which reduces the number of swings of a common voltage and reduces the power consumption of a data driving circuit in a liquid crystal display device driven by a line- ≪ / RTI >

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix form, and driving circuits for driving the liquid crystal display panel.

The liquid crystal display panel is provided with a thin film transistor for driving the liquid crystal cell Clc at the intersection of the gate line GL and the data line DL and the intersection of the gate line GL and the data line DL, A TFT (Thin Film Transistor) is formed. The thin film transistor TFT supplies the data voltage Vd supplied through the data line to the pixel electrode Ep of the liquid crystal cell Clc in response to the scan pulse from the gate line GL. To this end, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode thereof is connected to the data line DL, and the drain electrode thereof is connected to the pixel electrode of the liquid crystal cell Clc. The liquid crystal cell Clc is charged with the potential difference between the data voltage Vd supplied to the pixel electrode Ep and the common voltage Vcom supplied to the common electrode Ec, As the array changes, the amount of light transmitted is controlled or the light is blocked. The common electrode Ec is formed on the upper substrate or the lower substrate of the liquid crystal display panel according to a method of applying an electric field to the liquid crystal cell Clc and is connected to the storage line to which the common voltage Vcom is supplied, A storage capacitor Cst is formed between the electrodes Ep for maintaining the charged voltage of the liquid crystal cell Clc for one frame.

Such a liquid crystal display panel is driven by an inversion method in which the polarity of the liquid crystal cell Clc is inverted by a predetermined unit in order to prevent the deterioration of the liquid crystal cell Clc and improve the display quality. The inversion method includes a frame inversion in which the polarity of the liquid crystal cell is inverted in frame units, a line inversion in which the polarity of the liquid crystal cell is inverted in units of horizontal lines, a polarity of the liquid crystal cell in the vertical line unit A column inversion that inverts the liquid crystal cell, and a dot inversion that reverses the polarity of the liquid crystal cell in units of liquid crystal cells.

In particular, the line-inversion method reverses the polarity of the liquid crystal cell in units of horizontal lines and reverses the polarity of the liquid crystal cell on a frame-by-frame basis as shown in FIG. In the line inversion method, as shown in FIG. 3, the driving voltage range of the data voltage (Vd) is higher than the other inverting methods by driving the data voltage (Vd) and the common voltage (Vcom) There is an advantage of lowering. When the driving voltage range of the data voltage Vd is lowered, the power consumption of the data driving circuit is reduced accordingly.

However, in order to lower the driving voltage range of the data voltage Vd, the common voltage Vcom must be swung every horizontal line unit. Therefore, the liquid crystal display driven by the conventional line- A large power consumption is required for swinging.

In addition, the conventional liquid crystal display driven by the line-inversion method can reduce the power consumption of the data driving circuit to some extent by using the common voltage Vcom swinging in the opposite phase to the polarity of the data voltage Vd. However, Since the data voltage Vd having the opposite polarity is supplied to the liquid crystal cells each time in units of the period 1H, there is a limit in reducing the power consumption of the data driving circuit drastically.

It is therefore an object of the present invention to provide a liquid crystal display device and a method of driving the same that reduce the number of swings of a common voltage and reduce the power consumption of a data driving circuit in a liquid crystal display device driven by a line inversion method.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel having a plurality of gate lines, a plurality of data lines crossing the gate lines, a common electrode, and pixel electrodes; A scan pulse is sequentially supplied to a first group of gate lines including first gate lines for each frame period and a second group of gate lines including a gate line arranged for each of the first gate lines, To a gate driving circuit; After the data voltages of the first polarity are supplied to the data lines in synchronization with the scan pulses supplied to the first gate line group, the data lines are supplied in synchronization with the scan pulses supplied to the second gate line group, A data driving circuit for supplying a data voltage of a second polarity to the data driving circuit; A timing controller for controlling the operation timing of the driving circuits and generating a polarity control signal for controlling a polarity of a data voltage to be supplied to the data lines; And a common voltage generator for supplying a common voltage to the common electrode with a polarity opposite to the polarity of the data voltage.

Wherein the gate driving circuit comprises: a shift register array including a plurality of stages connected in a dependent manner to shift an input signal according to a gate shift clock; A level shift array for level shifting an output voltage of the shift register array; And a buffer array formed between the level shift array and the gate lines; The N-2 (N is a positive integer) stage output of the shift register array is supplied as an N-th stage input signal.

The polarity control signal is inverted in polarity at half the time of one frame period, and is maintained at the same polarity during the one frame period.

Wherein the data driving circuit supplies a data voltage of a first polarity to the data lines in synchronization with a scan pulse supplied to the odd gate lines during an odd frame period, Supplying a data voltage of a second polarity to the data lines; After the data voltage of the second polarity is supplied to the data lines in synchronization with the scan pulse supplied to the odd gate lines during the odd frame period, The data voltage of the first polarity is supplied.

Wherein the common voltage generator supplies a common voltage of the second polarity to the common electrode in synchronization with the data voltage of the first polarity and supplies the common voltage of the first polarity to the common electrode in synchronization with the data voltage of the second polarity. And supplies a common voltage.

According to another aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel having a plurality of gate lines, a plurality of data lines crossing the gate lines, a common electrode, and pixel electrodes; An image analyzing unit for analyzing input data and detecting input of moving image data and still image data; A gate driving circuit supplying a scan pulse to the gate lines and making a scan pulse supply order in the moving picture different from a scan pulse supply order on the still picture; A data driving circuit for supplying a data voltage to the data lines and making the data voltage polarity inversion period in the moving image shorter than a data voltage inversion period on the static image; A timing controller for controlling the operation timing of the driving circuits and generating a polarity control signal for controlling the polarity of the data voltage; And a common voltage generating unit for supplying a common voltage having a polarity opposite to the data voltage to the common electrode and making the common voltage polarity inversion period in the moving picture shorter than a common voltage inversion period on the still picture.

A liquid crystal display panel in which a plurality of gate lines, a plurality of data lines intersecting the gate lines, a common electrode, and pixel electrodes are formed according to an exemplary embodiment of the present invention; The method comprising: generating a polarity control signal for controlling the operation timing of the driving circuits and for controlling a polarity of a data voltage to be supplied to the data lines; A scan pulse is sequentially supplied to a first group of gate lines including first gate lines for each frame period and a second group of gate lines including a gate line arranged for each of the first gate lines, And supplying the data voltages of the first polarity to the data lines in synchronism with the scan pulses supplied to the first gate line group and then synchronizing with the scan pulses supplied to the second gate line group Supplying a data voltage of a second polarity to the data lines; And supplying a common voltage to the common electrode with a polarity opposite to the polarity of the data voltage.

According to another aspect of the present invention, there is provided a liquid crystal display panel including a plurality of gate lines, a plurality of data lines crossing the gate lines, a common electrode, and pixel electrodes, The method of driving a liquid crystal display device according to claim 1,

Analyzing the input data to detect whether the moving image data and the still image data are input; Generating a polarity control signal for controlling the operation timing of the driving circuits and for controlling a polarity of a data voltage to be supplied to the data lines; Supplying a scan pulse to the gate lines and making a scan pulse supply order in the moving picture different from a scan pulse supply order on the still picture; Supplying a data voltage to the data lines and making a data voltage polarity inversion period in the moving picture shorter than a data voltage inversion period on the still picture; And supplying a common voltage having a polarity opposite to the data voltage to the common electrode so that a common voltage polarity inversion period in the moving picture is shorter than a common voltage inversion period on the still picture.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 4 to 18. FIG.

FIG. 4 is a block diagram showing a liquid crystal display according to an embodiment of the present invention, and FIG. 5 is an internal configuration diagram of the timing controller of FIG.

4, a liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of gate lines GL1 to GLn (n is a positive integer) and a plurality of data lines DL1 to DLm Are formed at intersections of the liquid crystal cells Clc and the gate lines GL1 to GLn and the data lines DL1 to DLm formed in the pixel regions defined by the intersections, A liquid crystal display panel 140 including thin film transistors (TFTs) for driving a liquid crystal cell Clc and liquid crystal cells Clc arranged on odd-numbered horizontal lines through data lines DL1 to DLm, A data driving circuit 120 for supplying data voltages of a second polarity sequentially to liquid crystal cells Clc arranged in odd-numbered horizontal lines after supplying data voltages of a first polarity, GL1, GL3, GL5, ..., GLn-1, A gate driving circuit 130 for sequentially supplying scan pulses to the first gate lines GL2, GL4, GL6, ..., GLn, and driving circuits 120, 130, as well as input digital video data RiGiBi ) Into the odd data DHLo supplied to the odd-numbered horizontal liquid crystal cells Clc and the even data DHLe supplied to the even-numbered horizontal liquid crystal cells Clc, And a common voltage generator 150 for supplying a common voltage to the common electrode with a polarity opposite to the polarity of the data voltage.

The liquid crystal display panel 140 has a structure in which an upper substrate and a lower substrate are bonded together.

On the lower substrate of the liquid crystal display panel 140, the gate lines GL1 to GLn and the data lines DL1 to DLm cross each other. The thin film transistors TFT formed at the intersections of the odd-numbered gate lines GL1, GL3, GL5, ..., GLn-1 and the data lines DL1 to DLm are connected to the odd-numbered gate lines GL1, GL3 , GL5,..., GLn-1, thereby turning on data voltages of the first polarity supplied through the data lines DL1 to DLm to the odd-numbered horizontal liquid crystal cells Clc, To the pixel electrodes Ep formed on the pixel electrodes. The thin film transistors TFT formed at the intersections of the even-numbered gate lines GL2, GL4, GL6, ..., GLn and the data lines DL1 to DLm are connected to odd-numbered gate lines GL2, GL4, GL6 , ..., and GLn) are sequentially turned on so that the data voltages of the second polarity supplied through the data lines (DL1 to DLm) are applied to the pixels (Clc) formed in the horizontal liquid crystal cells Clc And supplies them to the electrodes Ep. Here, the gate electrode of the thin film transistors TFT is connected to one of the gate lines GL1 to GLn, the source electrode thereof is connected to one of the data lines DL1 to DLm, and the thin film transistors TFT Is connected to one of the pixel electrodes Ep of the liquid crystal cells Clc. The second polarity is opposite in polarity to the first polarity. The liquid crystal cell Clc is charged with the potential difference between the data voltage supplied to the pixel electrode Ep and the common voltage Vcom supplied to the common electrode Ec and the arrangement of the liquid crystal molecules is changed by the electric field formed by this potential difference The light amount of the transmitted light is adjusted. The common electrode Ec is formed on the upper substrate or the lower substrate according to a method of applying an electric field to the liquid crystal cell. The common electrode Ec is supplied with a common voltage Vcom having a polarity opposite to that of the data voltage supplied to the pixel electrode Ep. In order to maintain the charging voltage of the liquid crystal cell Clc for one frame between the pixel electrode Ep of the liquid crystal cell Clc and the front-end gate line or between the pixel electrode Ep of the liquid crystal cell Clc and another storage line, A storage capacitor is formed.

A color filter for realizing color and a black matrix for reducing optical interference between adjacent liquid crystal cells Clc are formed on the upper substrate of the liquid crystal display panel 140. Further, polarizers each having an optical axis orthogonal to each other are attached to the upper substrate and the lower substrate, and an alignment film for setting the pretilt angle of the liquid crystal is formed on the inner surfaces of the substrates.

The timing controller 110 rearranges the digital video data RiGiBi from the system (not shown) to supply the data to the data driving circuit 120 and controls the driving circuits 120 and 130 using the timing signals from the system ≪ / RTI > To this end, the timing controller 110 includes a data alignment unit 112 and a control signal generation unit 114 as shown in FIG.

The data sorting unit 112 rearranges the digital video data RiGiBi from the system to generate odd data DHLo supplied to the liquid crystal cells Clc arranged on the odd-numbered horizontal lines and odd- And separated into the superior data DHLe supplied to the disposed liquid crystal cells Clc. The data sorting unit 112 sequentially supplies the odd data DHLo to the data driving circuit 120 and then supplies the data driving circuit 120 sequentially with the even data DHLe.

The control signal generating unit 114 generates a control signal for driving the data driving circuit 120 using timing signals from the system, that is, the vertical / horizontal synchronizing signals Hsync and Vsync, the dot clock DCLK and the data enable signal DE, And a gate control signal GDC for controlling the gate driving circuit 130. The gate control signal GDC for controlling the gate driving circuit 130 and the data control signal DDC for controlling the gate driving circuit 130 are generated. Here, the data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity control signal POL, A pulse GSP, a gate shift clock GSC, a gate output signal GOE, and the like.

The source start pulse SSP indicates the starting point of data, i.e., the first liquid crystal cell Clc in one horizontal period. The source sampling clock SSC indicates a latch operation of data in the data driving circuit 120 based on a rising or falling edge. The source output signal SOE indicates the output of the data driving circuit 120. The polarity control signal POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 140. [ The gate start pulse (GSP) indicates a starting horizontal line at which the scanning starts from one vertical period in which one screen is displayed. The gate shift clock GSC is a timing control signal for sequentially shifting the gate start pulse GSP inputted to the shift register in the gate driving circuit 130. The gate shift clock GSC is a timing control signal for sequentially shifting the gate start pulse GSP, Width. The gate output signal GOE indicates the output of the gate drive circuit 130. [

The data driving circuit 120 supplies the odd data DHLo from the timing controller 110 to the data voltages of the first polarity using the gamma reference voltages GMA supplied from the gamma reference voltage generator And sequentially supplies the data voltages of the first polarity to the pixel electrodes Ep of the odd-numbered horizontal liquid crystal cells Clc via the data lines DL1 to DLm. Subsequently, the data driving circuit 120 converts the superior data DHLe from the timing controller 110 into the data voltages of the second polarity using the gamma reference voltages GMA supplied from the gamma reference voltage generator And sequentially supplies the data voltages of the second polarity to the pixel electrodes Ep of the even horizontal liquid crystal cells Clc via the data lines DL1 to DLm. To this end, the data driving circuit 120 includes a shift register, first and second latch arrays, a digital-to-analog converter, a multiplexer, and an output buffer. Such a data driving circuit 120 will be described later with reference to FIGS. 8 to 10. FIG.

The gate driving circuit 130 sequentially supplies the scan pulses to the odd-numbered gate lines GL1, GL3, GL5, ..., GLn-1 to select the horizontal lines to which the data voltages of the first polarity are supplied, The scan lines are sequentially supplied to the first, second, and third gate lines GL2, GL4, GL6, ..., GLn to select the horizontal lines to which the data voltages of the second polarity are supplied. To this end, the gate drive circuit 130 includes a shift register array, a level shift array, an output buffer array, and the like. The gate drive circuit 130 will be described later with reference to FIGS. 6 and 7. FIG.

The common voltage generating unit 150 generates a high potential common voltage + Vcom and a low potential common voltage -Vcom and supplies the data voltage having the opposite polarity to the data voltage supplied to the pixel electrode Ep of the liquid crystal cell Clc And supplies the common voltage to the common electrode Ec of the liquid crystal cell Clc. For example, assuming that the first polarity is a positive polarity and the second polarity is a negative polarity, the common voltage generating unit 150 generates the common voltage Vs of the liquid crystal cells Clc disposed on the odd- The common electrode Ec of the liquid crystal cells Clc is supplied with the low potential common voltage -Vcom during the period in which the data voltage is supplied to the liquid crystal cells Ep, The common electrode Ec of the liquid crystal cells Clc is supplied with the high potential common voltage + Vcom while the data voltage is supplied to the pixel electrodes Ep. In other words, the common voltage generator 150 supplies the common electrode with the low potential common voltage (-Vcom) for approximately one-half frame period in one frame period, and the high common voltage + Vcom) to the common electrode.

FIG. 6 is an internal configuration diagram of the gate driving circuit 130, and FIG. 7 is a waveform diagram of a scan pulse generated in FIG.

Referring to FIG. 6, the gate drive circuit 130 includes a shift register array 132, a level shift array 134, and an output buffer array 136.

The shift register array 132 includes a plurality of stages for sequentially generating a shift output signal by shifting the input signal by one horizontal period (1H) according to the gate shift clock GSC supplied from the timing controller 110, And shift registers S / R1 to S / Rn. The shift registers S / R1 to S / Rn sequentially output shift output signals shifted by one horizontal period (1H) in response to the gate shift clock GSC during the first sub frame period SF1 within one frame period (1/2) in response to the gate shift clock (GSC) during the second sub-frame period (SF2) within one frame period and the odd shift registers (S / R1, S / (S / R2, S / R4, ... S / Rn) which sequentially generate a shift signal having a predetermined number of shifts and a period (1H) of shift output signals. To this end, the first odd shift register S / R1 receives the gate start pulse GSP as an input signal and the second odd shift registers S / R3, ..., S / Rn-1 And the outputs of the preceding-stage odd-numbered shift registers S / R1, ..., S / Rn-3 are supplied as input signals. The first odd shift register S / R2 receives the output of the last odd shift register S / Rn-1 as an input signal and receives the output of the second odd shift register S / R4, ... S / Rn are supplied as input signals with the outputs of the preceding stage well shift registers S / R2, ..., S / Rn-2, respectively.

The level shift array 134 has level shifts L / S1 to L / Sn connected one-to-one to the output terminals of the shift registers S / R1 to S / Rn. The level shifts L / S1 to L / Sn are used to shift the shift output signal supplied from the shift registers S / R1 to S / Rn in response to the gate output signal GOE from the timing controller 110, Level shift to the scan pulses SP1 to SPn swinging between the voltage Vgl and the gate high voltage Vgh. The gate high voltage Vgh is higher than the threshold voltage of the thin film transistors TFT of the liquid crystal display panel 140 and the gate low voltage Vgl is lower than the threshold voltage of the thin film transistors TFT That is, the gate-off voltage.

The output buffer array 136 is arranged between the level shifters L / S1 to L / Sn and the gate lines GL1 to GLn to supply scan pulses L / S1 to L / (SP1 to SPn) are stabilized and output.

7, the gate driving circuit 130 sequentially generates the odd scan pulses SP1, SP3, ..., SPn-1 during the first sub-frame period SF1 within one frame period, (SP2, SP4, ... SPn) during the second sub-frame period (SF2) within one frame period after sequentially supplying the scan pulses (SP1, SP2, ... SPn) And supplies them to the even-numbered gate lines GL2, GL4, ..., GLn.

Fig. 8 is an internal configuration diagram of the data driving circuit 120, and Fig. 9 is a circuit diagram showing the digital / analog converter of Fig.

8, the data driving circuit 120 includes a plurality of integrated circuits (ICs), each integrated circuit including a shift register 122, which is connected between an input line and a data line, A first latch array 123, a second latch array 124, a gamma compensation voltage generator 125, a digital-to-analog converter (DAC) 126, a charge share circuit 127, And an output circuit 128.

The shift register 122 shifts the source start pulse SSP from the timing controller 110 according to the source shift clock SSC to generate a sampling signal. The shift register 122 shifts the source start pulse SSP and transfers the carry signal CAR to the shift register 122 at the next stage.

The first latch array 123 samples the digital video data DHLo and DHLe from the timing controller 110 in response to a sampling signal sequentially input from the shift register 122 and outputs the data DHLo and DHLe ) For one horizontal line, and then outputs data for one horizontal line at the same time.

The second latch array 124 latches one horizontal line of data input from the first latch array 123 and then forwards the second latch array 124 of the other data ICs 124 during the low logic period of the source output signal SOE And simultaneously outputs the latched digital video data DHLo and DHLe.

The gamma compensation voltage generator 125 further divides the plurality of gamma reference voltages supplied from the gamma reference voltage generator (not shown) by the number of gradations that can be represented by the number of bits of the digital video data DHLo and DHLe, To generate positive and negative gamma compensation voltages VGH and VGL, respectively.

The DAC 126 includes a P-decoder (PDEC) 1261 to which a positive gamma compensation voltage VGH is supplied, an N-decoder (NDEC) 1262 to which a negative gamma compensation voltage VGL is supplied, And a multiplexer 1263 for selecting the output of the P-decoder 1261 and the output of the N-decoder 1262 in response to the polarity control signals POL. The P-decoder 1261 decodes the digital video data DHLo and DHLe input from the second latch array 124 and outputs a positive gamma compensation voltage VGH corresponding to the gray level of the data, The decoder 122 decodes the digital video data DHLo and DHLe input from the second latch array 94 and outputs a negative gamma compensation voltage VGL corresponding to the gray level value of the data. The multiplexer 103 selects the positive gamma compensation voltage VGH and the negative gamma compensation voltage VGL in response to the polarity control signal POL. Here, as shown in FIG. 10, the polarity control signal POL is inverted at a half time point of one frame period and is maintained at the same polarity for one frame period.

The charge sharing circuit 127 short-circuits the neighboring data output channels during the high logic period of the source output signal SOE to output the average value of the neighboring data voltages to the charge share voltage, The common voltage Vcom is supplied to the data output channels during the high logic period to reduce a sharp change in the positive polarity data voltage and the negative polarity data voltage.

The output circuit 128 includes a buffer to minimize signal attenuation of the data voltage supplied to the data lines DL1 to DLk.

FIG. 11 is a diagram illustrating a procedure of charging liquid crystal cells for each horizontal line in a liquid crystal display device driven by a line-inversion method according to an embodiment of the present invention. FIG. 12 illustrates that the number of swings of the common voltage is significantly reduced Fig. 11, only a part of the liquid crystal display panel is shown for convenience of explanation. The serial numbers in Figs. 11 and 12 indicate the supply order of the data voltages per horizontal line.

11 and 12, a liquid crystal display according to an exemplary embodiment of the present invention sequentially applies a positive polarity data voltage to liquid crystal cells arranged on odd-numbered horizontal lines for line inversion driving And sequentially supplies the data voltages of negative polarity to the liquid crystal cells arranged on the even horizontal lines. Here, the low-potential common voltage (-Vcom) is supplied to the common electrode during the period in which the positive polarity data voltage is supplied to the liquid crystal cells arranged on the odd-numbered horizontal lines, as shown in Fig. During the period in which the positive polarity data voltage is supplied to the liquid crystal cells arranged on the even horizontal lines, the high common voltage + Vcom is supplied to the common electrode as shown in FIG. Accordingly, the common voltage Vcom according to the exemplary embodiment of the present invention swings at a period of one frame period, unlike the conventional method in which the common voltage Vcom is swung in one horizontal period. As a result, the number of swings is greatly reduced compared with the conventional method. Since the number of swings of the common voltage Vcom is reduced, the power consumption in the common voltage generating unit is drastically reduced. 12, in the liquid crystal display according to an embodiment of the present invention, the data voltages of the same polarity are sequentially supplied to the liquid crystal cells for approximately one frame period, thereby greatly increasing the load of the output buffer of the data driving circuit The power consumed by the data driving circuit can be greatly reduced.

Meanwhile, in the liquid crystal display device according to an embodiment of the present invention, the liquid crystal cells arranged on the odd-numbered horizontal lines are sequentially charged first and then the liquid crystal cells arranged on the odd-numbered horizontal lines are sequentially charged. There is a possibility that the moving image characteristic deteriorates compared with the conventional one. Accordingly, when the input image is a moving image, all the liquid crystal cells are sequentially driven in the same manner as in the related art. Only when the input image is a still image, the liquid crystal cells are divided into odd / even horizontal lines as in the embodiment of the present invention . This will be described later with reference to another embodiment of the present invention.

FIG. 13 is a block diagram showing a liquid crystal display device according to another embodiment of the present invention, and FIG. 14 is an internal configuration diagram of the timing controller of FIG.

Referring to FIG. 13, a liquid crystal display according to another embodiment of the present invention includes a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm intersecting with each other, TFTs formed at intersections of the liquid crystal cells Clc and the gate lines GL1 to GLn and the data lines DL1 to DLm and driving the liquid crystal cells Clc, An image analyzing unit 260 for analyzing input digital video data RiGiBi to detect whether a still image or a moving image is inputted and a detection unit 260 for detecting a detection signal from the image analyzing unit 260 The driving circuits 220 and 230 are controlled so that the digital video data RiGiBi are arranged differently according to the attributes of the image and the sorted data RGB are displayed on the liquid crystal display panel 240 in response to the control signals DS1 and DS2, A timing controller 210 for outputting sorted data (RGB) A data driving circuit 220 for converting the data voltages into data voltages and supplying the data voltages to the data lines DL1 to DLm; A gate drive circuit 230 for changing the supply order of the pulses, and a common voltage generator 250 for supplying a common voltage to the common electrode with a polarity opposite to the polarity of the data voltage.

The liquid crystal display panel 240 is substantially the same as in Fig.

The image analyzing unit 260 analyzes the digital video data RiGiBi inputted from the system (not shown) to detect whether the input image is a still image or a moving image and outputs the detected signals DS1 and DS2 to the timing controller (210). To this end, the image analysis unit 260 alternately stores the input digital video data RiGiBi on a frame basis using a frame memory, and compares the stored inter-frame data to determine whether the input image is a moving image or a still image . The image analyzer 260 supplies the first detection signal DS1 if the input image is a moving image and the second detection signal DS2 if the input image is a still image to the timing controller 210. [ Meanwhile, the image analyzing unit 260 may use a known image detecting method such as the use of a motion factor to detect the attribute of the input image. The image analysis unit 260 may be embedded in the timing controller 210.

The timing controller 210 arranges the digital video data RiGiBi differently according to the attributes of the video in response to the detection signals DS1 and DS2 from the video analyzer 260 and outputs the sorted data RGB And controls the driving circuits 220 and 230 to be displayed on the liquid crystal display panel 240. To this end, the timing controller 110 includes a data alignment unit 212 and a control signal generation unit 214 as shown in FIG.

When the first detection signal DS1 is input, the data sorting unit 212 sequentially arranges the input digital video data RiGiBi without discriminating the odd data / superior data and outputs the sorted data RGB to the data And supplies it to the driving circuit 220.

When the second detection signal DS2 is input, the data sorting unit 212 rearranges the input digital video data RiGiBi to generate odd data (e.g., And DHLo supplied to the liquid crystal cells Clc disposed on the even horizontal lines. The data sorting unit 212 sequentially supplies the odd data DHLo to the data driving circuit 220 and sequentially supplies the data driving circuit 220 with the even data DHLe.

The control signal generating unit 214 generates a control signal by using the first detection signal DS1 and the timing signals Hsync, Vsync, DCLK, and DE from the system when the first detection signal DS1 is input. A first data control signal DDC1 (POL1) for controlling the gate driving circuit 220 and a gate control signal GDC for controlling the gate driving circuit 230 are generated. The first data control signal DDC1 (POL1) includes the first polarity control signal POL1 as shown in FIG. The polarity of the first polarity control signal POL1 is inverted in one horizontal period (1H), and its polarity is reversed in one frame period.

The control signal generating unit 214 generates a control signal by using the second detection signal DS2 and the timing signals Hsync, Vsync, DCLK, and DE from the system when the second detection signal DS2 is input. A second data control signal DDC2 (POL2) for controlling the gate driving circuit 220 and a gate control signal GDC for controlling the gate driving circuit 230 are generated. The second data control signal DDC2 (POL2) includes the second polarity control signal POL2 as shown in FIG. The second polarity control signal POL2 has a polarity that is inverted from a 1/2 vertical period (1/2 V), i.e., a 1/2 frame period, within one frame period. Also, the polarity of the second polarity control signal POL2 is inverted in one frame period.

The control signal generating unit 214 couples the first or second detection signals DS1 and DS2 input from the image analyzing unit 260 to the gate driving circuit 230. Details of the control signals SSP, SSC, SOE, GDC, GSP, GSC, and GOE generated from the control signal generating unit 214 are substantially the same as those described with reference to FIG.

The data driving circuit 220 converts the data RGB from the timing controller 210 into gamma reference voltages GMA supplied from a gamma reference voltage generator (not shown) And sequentially supplies the data voltages to the pixel electrodes Ep of the liquid crystal cells Clc via the data lines DL1 to DLm. Here, the data voltages have different polarities for each horizontal line by the first polarity control signal POL1.

When the input image is a still image, the data driving circuit 220 converts the odd data DHLo from the timing controller 210 to gamma reference voltages GMA supplied from a gamma reference voltage generator (not shown) The data voltages of the first polarity are sequentially supplied to the pixel electrodes Ep of the odd-numbered horizontal liquid crystal cells Clc via the data lines DL1 to DLm do. Subsequently, the data driving circuit 220 converts the superior data DHLe from the timing controller 210 to the data voltages of the second polarity using the gamma reference voltages GMA supplied from the gamma reference voltage generator And sequentially supplies the data voltages of the second polarity to the pixel electrodes Ep of the even horizontal liquid crystal cells Clc via the data lines DL1 to DLm. Here, the first and second polarities of the data voltages are controlled by the second polarity control signal POL2.

The data driving circuit 220 includes a shift register, first and second latch arrays, a digital / analog converter, a multiplexer, and an output buffer, as shown in FIGS. A detailed description thereof will be omitted.

The gate driving circuit 230 sequentially supplies the scan pulses to the gate lines GL1 to GLn in response to the first detection signal DS1 to select the horizontal lines to which the data voltages are supplied.

The gate driving circuit 230 sequentially supplies scan pulses to the odd-numbered gate lines GL1, GL3, GL5, ..., GLn-1 in response to the second detection signal DS2 if the input image is a still image After the horizontal lines to which the data voltages of the first polarity are supplied, the scan lines are sequentially supplied to the even-numbered gate lines GL2, GL4, GL6, ..., GLn, Select lines. To this end, the gate drive circuit 230 includes a shift register array, a level shift array, an output buffer array, and the like. The gate drive circuit 230 will be described later with reference to FIGS. 16 and 17. FIG.

The common voltage generating unit 250 generates a high potential common voltage + Vcom and a low potential common voltage -Vcom to generate a polarity opposite to the polarity of the data voltage supplied to the pixel electrode Ep of the liquid crystal cell Clc To the common electrode Ec of the liquid crystal cell Clc.

16 is an internal configuration diagram of the gate driving circuit 230, and FIGS. 17A and 17B are waveform diagrams of scan pulses generated when an input image is a moving image and a still image, respectively.

16, the gate drive circuit 230 includes a multiplexer array 232, a shift register array 234, a level shift array 236, and an output buffer array 238.

The multiplexer array 232 selects one of the shift output signal from the previous shift register and the shift output signal from the previous shift register in response to the detection signals DS1 and DS2, Multiplexers (MUX). The multiplexers (MUX) couple the plurality of shift registers S / R1 to S / Rn depending on the first detection signal DS1 by inputting the output of the previous stage shift register into the current one-stage shift register. The multiplexers MUX are connected to the odd shift registers S / R1, S / R3, ..., S / S by inputting the output of the full-stage shift register to the current stage shift register in response to the second detection signal DS2. Rn-1) are connected in a dependent manner, and the well shift registers S / R2, S / R4, ... S / Rn are connected in a dependent manner. The previous leading edge of the first outstanding shift register (S / R2) becomes the last radial shift register (S / Rn-1).

The shift register array 234 includes a plurality of stages for sequentially generating a shift output signal by shifting the input signal by one horizontal period (1H) according to the gate shift clock GSC supplied from the timing controller 210, And shift registers S / R1 to S / Rn.

When the first detection signal DS1 is input, the plurality of shift registers S / R1 to S / Rn sequentially shifts the input signal according to the gate shift clock GSC supplied from the timing controller 210, 1H) to sequentially generate shift output signals.

On the other hand, when the second detection signal DS2 is input, the odd-numbered shift registers S / R1, S / R3, ... S / Rn-1 are turned on during the first sub- And sequentially generates one horizontal period (1H) shifted shift output signal in response to the gate shift clock GSC. Subsequently, the odd shift registers S / R2, S / R4, ..., S / Rn are reset in one horizontal period (1H) in response to the gate shift clock GSC during the second sub- ) Generates shifted shift output signals sequentially. To this end, the first odd shift register S / R1 receives the gate start pulse GSP as an input signal and the second odd shift registers S / R3, ..., S / Rn-1 And the outputs of the preceding-stage odd-numbered shift registers S / R1, ..., S / Rn-3 are supplied as input signals. The first odd shift register S / R2 receives the output of the last odd shift register S / Rn-1 as an input signal and receives the output of the second odd shift register S / R4, ... S / Rn are supplied as input signals with the outputs of the preceding stage well shift registers S / R2, ..., S / Rn-2, respectively.

The level shift array 236 has level shifts L / S1 to L / Sn connected one-to-one to the output terminals of the shift registers S / R1 to S / Rn. The level shifts L / S1 to L / Sn are used to shift the shift output signal supplied from the shift registers S / R1 to S / Rn in response to the gate output signal GOE from the timing controller 210, Level shift to the scan pulses SP1 to SPn swinging between the voltage Vgl and the gate high voltage Vgh. Here, the gate high voltage Vgh is a voltage higher than the threshold voltage of the thin film transistors TFT of the liquid crystal display panel 240, that is, the gate-on voltage, and the gate low voltage Vgl is the threshold voltage of the thin film transistors TFT Voltage, that is, a gate-off voltage.

The output buffer array 238 is arranged between the level shifters L / S1 to L / Sn and the gate lines GL1 to GLn to supply scan pulses L / S1 to L / (SP1 to SPn) are stabilized and output.

In this configuration, when the first detection signal DS1 is input, the gate driving circuit 230 generates the scan pulses SP1 to SPn and sequentially supplies the scan pulses SP1 to SPn to the gate lines GL1 to GLn as shown in FIG. 17A.

When the second detection signal DS2 is input, the gate driving circuit 230 outputs odd scan pulses SP1, SP3, ..., SPn-1 during the first sub frame period SF1 within one frame period as shown in FIG. 17B, 1) are sequentially generated and sequentially supplied to the odd-numbered gate lines GL1, GL3, ..., GLn-1, and the even-numbered scan pulses SP2 , SP4, ..., SPn are sequentially generated and sequentially supplied to the even-numbered gate lines GL2, GL4, ..., GLn.

18 is a flowchart illustrating a method of driving a liquid crystal display according to another embodiment of the present invention.

Referring to FIG. 18, the driving method of a liquid crystal display (LCD) device according to another embodiment of the present invention detects an input digital video data attribute to determine whether the input video is a moving image (S10)

As a result of the determination in step S10, if the input image is a moving image, the driving method of the liquid crystal display sequentially arranges (RGB) the input digital video data without discriminating the odd data / superior data.

The driving method of the liquid crystal display device sequentially scans all the gate lines and displays data (RGB) arranged in the liquid crystal cells arranged on the corresponding horizontal lines in accordance with the scanning sequence, The polarity of the liquid crystal cells is controlled by using the first polarity control signal POL1 whose polarity is inverted with a period of 1H. (S30, S40)

The driving method of the liquid crystal display swings the polarity of the common voltage to have a polarity opposite to that of the liquid crystal cells in a period of one horizontal period (1H) as shown in FIG. 3. (S50)

On the other hand, if it is determined in step S10 that the input image is a still image, the driving method of the liquid crystal display separates input digital video data into odd data and superior data and sequentially arranges them DHLo and DHLe (S60 )

A method of driving a liquid crystal display sequentially scans odd-numbered gate lines and then successively scans superior gate lines. The data DHLo and DHLe arranged in the liquid crystal cells arranged on the corresponding horizontal lines are displayed in accordance with the scanning sequence, and the polarities of the liquid crystal cells are reversed at 1/2 of one frame period as shown in FIG. And the polarities of the liquid crystal cells are kept at the same polarity during one frame period (S70, S80).

The driving method of the liquid crystal display swings the polarity of the common voltage with a period of one frame period as shown in FIG. 12 so that the common voltage has a polarity opposite to that of the liquid crystal cells.

As described above, in the method of driving a liquid crystal display according to another embodiment of the present invention, when the input image is a moving image, all the liquid crystal cells are sequentially driven in the same manner as in the prior art, In the case of a still image, the liquid crystal cells may be divided and driven by the odd / even horizontal lines to reduce the number of swings of the common voltage and power consumption of the data driving circuit, as in the embodiment of the present invention.

As described above, in the liquid crystal display and the driving method thereof according to the present invention, the data voltages of the first polarity are supplied to the data lines in synchronization with the scan pulses supplied to the odd gate line group, The data voltage of the second polarity is supplied to the data lines in synchronization with the scan pulses and the common voltage is supplied to the common electrode with the polarity opposite to the polarity of the data voltage so that the number of swings of the common voltage can be greatly reduced . In addition, by supplying a data voltage of the same polarity to the data lines for approximately one frame period, power consumed in the data driving circuit can be greatly reduced.

Further, in the liquid crystal display device and the driving method thereof according to the present invention, an apparatus for detecting the attribute of an input image is added, and the liquid crystal cells are divided and divided into odd / even horizontal lines only when the input image is a still image, The power consumption of the data driving circuit is reduced, and when the input image is a moving image, all the liquid crystal cells are sequentially driven in the same manner as in the prior art, thereby preventing display quality deterioration in a moving image.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (13)

A liquid crystal display panel in which a plurality of gate lines, a plurality of data lines intersecting the gate lines, a common electrode, and pixel electrodes are formed; A scan pulse is sequentially supplied to a first group of gate lines including first gate lines for each frame period and a second group of gate lines including a gate line arranged for each of the first gate lines, To a gate driving circuit; After supplying a data voltage of the first polarity to the data lines in synchronization with the scan pulses supplied to the first gate line group, the data lines are supplied to the data lines in synchronization with the scan pulses supplied to the second gate line group A data driving circuit for supplying a data voltage of a second polarity; A timing controller for controlling the operation timing of the driving circuits and generating a polarity control signal for controlling a polarity of a data voltage to be supplied to the data lines; And And a common voltage generator for generating a high potential common voltage and a low potential common voltage and supplying a common voltage having a polarity opposite to the polarity of the data voltage to the common electrode. The method according to claim 1, The gate drive circuit includes: A shift register array including a plurality of stages connected in a dependent fashion to shift an input signal according to a gate shift clock; A level shift array for level shifting an output voltage of the shift register array; And And a buffer array formed between the level shift array and the gate lines; And an N-2 (N is a positive integer of 3 or more) stage output of the shift register array is supplied as an N-th stage input signal. 3. The method of claim 2, Wherein the polarity control signal is inverted in polarity at a half of one frame period and is maintained at the same polarity during the one frame period. The method of claim 3, The data driving circuit includes: A scan pulse supplied to the even gate lines among the gate lines after supplying a data voltage of the first polarity to the data lines in synchronization with the scan pulse supplied to the odd gate lines of the gate lines during the odd frame period, Supplying a data voltage of a second polarity to the data lines in synchronization with the data lines; After the data voltage of the second polarity is supplied to the data lines in synchronization with the scan pulse supplied to the odd gate lines during the odd frame period, And supplies the data voltage of the first polarity to the data line. 5. The method of claim 4, Wherein the common voltage generator comprises: Supplying a common voltage of the second polarity to the common electrode in synchronization with the data voltage of the first polarity and supplying a common voltage of the first polarity to the common electrode in synchronization with the data voltage of the second polarity Wherein the liquid crystal display device is a liquid crystal display device. A liquid crystal display panel in which a plurality of gate lines, a plurality of data lines intersecting the gate lines, a common electrode, and pixel electrodes are formed; An image analyzing unit for analyzing input data and detecting input of moving image data and still image data; A gate driving circuit for supplying a scan pulse to the gate lines and making a scan pulse supply order in a moving picture different from a scan pulse supply order on a still picture; A data driving circuit for supplying a data voltage to the data lines and making the data voltage polarity inversion period in the moving image shorter than the data voltage inversion period on the still image; A timing controller for controlling the operation timing of the driving circuits and generating a polarity control signal for controlling the polarity of the data voltage; And And a common voltage generator for supplying a common voltage having a polarity opposite to that of the data voltage to the common electrode so as to make the common voltage polarity inversion period in the moving picture smaller than the common voltage inversion period on the still picture. The method according to claim 6, The gate drive circuit includes: Sequentially supplying the scan pulse to the gate lines in the moving picture; Sequentially supplying the scan pulses to the odd gate lines of the gate lines, and then sequentially supplying the scan pulses to the odd gate lines arranged between the odd gate lines. 2. The liquid crystal display device of claim 1, . 8. The method of claim 7, The gate drive circuit includes: A shift register array including a plurality of stages connected in a dependent fashion to shift an input signal according to a gate shift clock; A level shift array for level shifting an output voltage of the shift register array; A buffer array formed between the level shift array and the gate lines; And (N is a positive integer equal to or greater than 3) stage output of the shift register array in the moving picture is supplied as an N-th stage input signal, and an N-2 < th > And a multiplexer array for supplying the input signal as an input signal. 9. The method of claim 8, The polarity control signal in the moving picture is polarized in a period of one horizontal period; Wherein the polarity control signal on the still image is inverted in polarity at a half time point of one frame period and is maintained at the same polarity during the one frame period. 10. The method of claim 9, The data driving circuit includes: And supplies a data voltage having a polarity reversed to the data lines in a period of one horizontal period in synchronization with a scan pulse supplied to the gate lines according to a polarity control signal in the moving picture. 10. The method of claim 9, The data driving circuit includes: And supplying the data voltages of the first polarity to the data lines in synchronization with the scan pulses supplied to the odd gate lines during the odd frame period according to the polarity control signal on the still picture, Supplying a data voltage of a second polarity to the data lines in synchronization with the scan pulses; After the data voltages of the second polarity are supplied to the data lines in synchronization with the scan pulses supplied to the odd gate lines during the odd frame period, the data voltages are supplied to the odd gate lines in synchronization with the scan pulses supplied to the even gate lines And supplies the data voltage of the first polarity to the lines. A liquid crystal display panel in which a plurality of gate lines, a plurality of data lines intersecting the gate lines, a common electrode, and pixel electrodes are formed, and a driving method of a liquid crystal display device having driving circuits for driving the liquid crystal display panel In this case, Generating a polarity control signal for controlling the operation timing of the driving circuits and for controlling a polarity of a data voltage to be supplied to the data lines; A scan pulse is sequentially supplied to a first group of gate lines including first gate lines for each frame period and a second group of gate lines including a gate line arranged for each of the first gate lines, ; After supplying a data voltage of the first polarity to the data lines in synchronization with the scan pulses supplied to the first gate line group, the data lines are supplied to the data lines in synchronization with the scan pulses supplied to the second gate line group Supplying a data voltage of a second polarity; And Generating a high potential common voltage and a low potential common voltage to supply a common voltage having a polarity opposite to the polarity of the high and low potential data voltages to the common electrode . A liquid crystal display panel in which a plurality of gate lines, a plurality of data lines intersecting the gate lines, a common electrode, and pixel electrodes are formed, and a driving method of a liquid crystal display device having driving circuits for driving the liquid crystal display panel In this case, Analyzing the input data to detect whether the moving image data and the still image data are input; Generating a polarity control signal for controlling the operation timing of the driving circuits and for controlling a polarity of a data voltage to be supplied to the data lines; Supplying a scan pulse to the gate lines and making a scan pulse supply order in a moving picture different from a scan pulse supply order on a still picture; Supplying a data voltage to the data lines and making the data voltage polarity inversion period in the moving image shorter than the data voltage inversion period on the still image; And And supplying a common voltage having a polarity opposite to the data voltage to the common electrode so as to make the common voltage polarity inversion period in the moving picture to be shorter than the common voltage inversion period in the still picture mode .

Images