KR20080111318A - Liquid crystal display and driving method thereof - Google Patents

Abstract

A liquid crystal display device driven by an inversion method is provided to reduce the number of swing of common voltage by supplying common voltage to the common electrode which is contrary to the polarity of data voltage. An LCD panel(140) has a common electrode(Ec) and a pixel electrode(Ep). A gate driving circuit(130) sequentially supplies scan pulse to the second gate line group. A data driving circuit supplies data voltage to the second polarity to data lines after supplying data voltage of a first polarity to the data lines. A timing controller(110) generates the polarity control signal for controlling polarity of data voltage which is provided to the data lines. A common voltage generation part(150) supplies the common voltage(Vcom) to the common electrode.

Description

Liquid Crystal Display and Driving Method Thereof

1 is a view schematically showing a liquid crystal cell included in a conventional liquid crystal display panel.

2 is a view showing a part of a liquid crystal display panel driven by a conventional line inversion method.

3 is a waveform diagram of a common voltage supplied in synchronization with a data voltage in a conventional line inversion scheme.

4 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a diagram illustrating an internal configuration of the timing controller of FIG. 4.

6 is a diagram illustrating an internal configuration of the gate driving circuit of FIG. 4.

7 is a waveform diagram of a scan pulse generated through FIG. 6.

8 is a diagram illustrating an internal configuration of the data driving circuit of FIG. 4.

FIG. 9 is a circuit diagram illustrating the digital-to-analog converter of FIG. 8. FIG.

10 is a waveform diagram of a polarity control signal supplied to the data driving circuit of FIG. 8; FIG.

11 is a view showing a charging sequence of liquid crystal cells for each horizontal line in the liquid crystal display device driven in a line inversion method according to an embodiment of the present invention.

12 is a waveform diagram for explaining that the number of swings of a common voltage is significantly reduced.

13 is a block diagram illustrating a liquid crystal display according to another exemplary embodiment of the present invention.

14 is a diagram illustrating an internal configuration of the timing controller of FIG. 13.

FIG. 15 is a waveform diagram of a polarity control signal supplied to the data driving circuit of FIG.

FIG. 16 is a diagram illustrating an internal configuration of the gate driving circuit of FIG. 13.

17A and 17B are waveform diagrams of scan pulses generated when an input image is a moving image and a still image, respectively.

18 is a flowchart illustrating a method of driving a liquid crystal display according to another embodiment of the present invention.

<Description of Major Symbols in Drawing>

110,210: Timing controller 112,212: Data alignment unit

114,214: control signal generator 120,220: data driving circuit

122: shift register 123: first latch array

124: second latch array 125: gamma compensation voltage generator

126: digital-to-analog converter 127: charge share circuit

128: output circuit 130,230: gate driving circuit

132,234: shift register array 134,236: level shift array

136,238 Buffer Array 232 Multiplexer Array

260: image analysis unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof. In particular, in a liquid crystal display device driven by a line inversion method, a liquid crystal display device and a driving method for reducing the number of swings of a common voltage and reducing power consumption of a data driving circuit It is about a method.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. The liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix and driving circuits for driving the liquid crystal display panel.

1, a thin film for driving the liquid crystal cell Clc at the intersection of the gate line GL and the data line DL and crossing the gate line GL and the data line DL as shown in FIG. 1. A transistor (Thin Film Transistor: TFT) is formed. The thin film transistor TFT supplies the data voltage Vd supplied through the data line to the pixel electrode Ep of the liquid crystal cell Clc in response to a scan pulse from the gate line GL. To this end, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc. The liquid crystal cell Clc is charged with a potential difference between the data voltage Vd supplied to the pixel electrode Ep and the common voltage Vcom supplied to the common electrode Ec, and the liquid crystal molecules are charged by an electric field formed by the potential difference. As the arrangement changes, it controls the amount of light transmitted or blocks the light. The common electrode Ec is formed on the upper substrate or the lower substrate of the liquid crystal display panel according to a method of applying an electric field to the liquid crystal cell Clc, and the storage line to which the common voltage Vcom is supplied and the pixels of the liquid crystal cell Clc. A storage capacitor Cst is formed between the electrodes Ep to maintain the charging voltage of the liquid crystal cell Clc for one frame.

The liquid crystal display panel is driven in an inversion manner in which the polarity of the liquid crystal cell Clc is inverted by a predetermined unit in order to prevent deterioration of the liquid crystal cell Clc and to improve display quality. In the Inversion method, Frame Inversion, which reverses the polarity of the liquid crystal cell in units of frames, Line Inversion, which reverses the polarity of the liquid crystal cells in units of horizontal lines, and Polarity of the liquid crystal cell in units of vertical lines. Column inversion for inversion, and Dot Inversion for inverting the polarity of the liquid crystal cell in units of liquid crystal cells.

In particular, the line inversion method inverts the polarity of the liquid crystal cell in units of horizontal lines and inverts the polarity of the liquid crystal cell in units of frames as shown in FIG. 2. In the line inversion scheme, as shown in FIG. 3, the data voltage Vd and the common voltage Vcom supplied to the common electrode are alternately driven in opposite phases, so that the driving voltage range of the data voltage Vd is lower than that of the other inversion schemes. It has the advantage of being lowered. When the driving voltage range of the data voltage Vd is lowered, power consumption of the data driving circuit is also reduced.

However, in order to lower the driving voltage range of the data voltage Vd, the common voltage Vcom must be swinged every horizontal line unit. Therefore, the liquid crystal display device driven by the conventional line inversion method uses the common voltage Vcom. It requires a large power consumption to swing.

In addition, the liquid crystal display device driven by the conventional line inversion method may reduce power consumption of the data driving circuit to some extent by using the common voltage Vcom swinging in a phase opposite to the polarity of the data voltage Vd. Since the data voltages Vd having opposite polarities must be supplied to the liquid crystal cells every time period 1H, there is a limit in drastically reducing the power consumption of the data driving circuit.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of driving the same, which reduce the number of swings of a common voltage and reduce power consumption of a data driving circuit in a liquid crystal display device driven by a line inversion method.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel including a plurality of gate lines, a plurality of data lines crossing the gate lines, a common electrode, and a pixel electrode; The scan pulses are sequentially supplied to the first gate line group including the first gate lines during every frame period, and the scan pulses are sequentially applied to the second gate line group including the gate lines arranged one by one between the first gate lines. A gate driving circuit for supplying to the circuit; After supplying a data voltage having a first polarity to the data lines in synchronization with the scan pulses supplied to the first gate line group, the data lines in synchronization with the scan pulses supplied to the second gate line group. A data driving circuit for supplying a data voltage having a second polarity to the second voltage; A timing controller configured to control an operation timing of the driving circuits and to generate a polarity control signal for controlling a polarity of data voltages to be supplied to the data lines; And a common voltage generator supplying a common voltage to the common electrode at a polarity opposite to that of the data voltage.

The gate driving circuit includes a shift register array including a plurality of stages connected in cascade to shift an input signal according to a gate shift clock; A level shift array for level shifting the output voltage of the shift register array; And a buffer array formed between the level shift array and the gate lines; The N-2 (N is positive integer) th stage output of the shift register array is supplied as an input signal of the N th stage.

The polarity control signal is inverted at one half of one frame period and is maintained at the same polarity for one frame period.

The data driving circuit synchronizes with scan pulses supplied to the even gate lines after supplying a data voltage having a first polarity to the data lines in synchronization with the scan pulses supplied to the odd gate lines during an odd frame period. Supplying a data voltage of a second polarity to the data lines; The data lines are supplied in synchronization with the scan pulses supplied to the even gate lines after the data voltage of the second polarity is supplied to the data lines in synchronization with the scan pulses supplied to the odd gate lines during the even frame period. The data voltage of the first polarity is supplied to the.

The common voltage generator is configured to supply the common voltage of the second polarity to the common electrode in synchronization with the data voltage of the first polarity, and to the common electrode in synchronization with the data voltage of the second polarity. Supply common voltage.

In accordance with another aspect of the present invention, a liquid crystal display device includes: a liquid crystal display panel in which a plurality of gate lines, a plurality of data lines intersecting the gate lines, a common electrode, and pixel electrodes are formed; An image analyzer for analyzing input data to detect whether video data and still image data are input; A gate driving circuit which supplies a scan pulse to the gate lines and makes a scan pulse supply order different from the scan pulse supply order in the still image; A data driving circuit which supplies a data voltage to the data lines and makes the data voltage polarity inversion period in the moving image shorter than the data voltage inversion period in the still image; A timing controller for controlling an operation timing of the driving circuits and generating a polarity control signal for controlling the polarity of the data voltage; And a common voltage generator for supplying a common voltage having a polarity opposite to that of the data voltage to the common electrode, and making the common voltage polarity inversion period in the moving image shorter than the common voltage inversion period in the still image.

According to an embodiment of the present invention, a plurality of gate lines, a plurality of data lines intersecting the gate lines, a common electrode, and a pixel electrode are formed to achieve the above object, the liquid crystal display panel A driving method of a liquid crystal display device having drive circuits for driving a light source includes: generating a polarity control signal for controlling an operation timing of the drive circuits and controlling a polarity of data voltages to be supplied to the data lines; The scan pulses are sequentially supplied to the first gate line group including the first gate lines during every frame period, and the scan pulses are sequentially applied to the second gate line group including the gate lines arranged one by one between the first gate lines. And supplying a data voltage having a first polarity to the data lines in synchronization with the scan pulses supplied to the first gate line group, and then in synchronization with the scan pulses supplied to the second gate line group. Supplying data voltages of a second polarity to the data lines; And supplying a common voltage to the common electrode with a polarity opposite to that of the data voltage.

According to another exemplary embodiment of the present invention, a plurality of gate lines, a plurality of data lines intersecting the gate lines, a common electrode, and a pixel electrode are formed, a liquid crystal display panel. A driving method of a liquid crystal display device having drive circuits for driving the

Analyzing input data to detect whether video data and still image data are input; Generating a polarity control signal for controlling the operation timing of the driving circuits and for controlling the polarity of the data voltages to be supplied to the data lines; Supplying a scan pulse to the gate lines and changing a scan pulse supply order in the moving picture from a scan pulse supply order in the still image; Supplying a data voltage to the data lines and making the data voltage polarity inversion period in the moving image shorter than the data voltage inversion period in the still image; And supplying a common voltage having a polarity opposite to that of the data voltage to the common electrode, and making the common voltage polarity inversion period in the video shorter than the common voltage inversion period in the still image.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 18.

4 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is an internal configuration diagram of the timing controller of FIG. 4.

Referring to FIG. 4, a liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of gate lines GL1 to GLn; n is a positive integer, and a plurality of data lines DL1 to DLm; m is a positive integer. ) Cross each other and are formed at the intersections of the liquid crystal cells Clc and the gate lines GL1 to GLn and the data lines DL1 to DLm formed in the pixel regions defined by the intersections, respectively. The liquid crystal display panel 140 including thin film transistors TFT driving the Clc, and the liquid crystal cells Clc disposed in the odd horizontal lines through the data lines DL1 through DLm. After the data voltages of the first polarity are supplied, the data driver circuit 120 sequentially supplies the data voltages of the second polarity to the liquid crystal cells Clc disposed on even-numbered horizontal lines, and the odd-numbered gate lines ( Excellent after supplying scan pulse sequentially to GL1, GL3, GL5, ... GLn-1) The gate driving circuit 130 which sequentially supplies scan pulses to the first gate lines GL2, GL4, GL6,..., And GLn and the driving circuits 120, 130 are controlled, and the input digital video data RiGiBi is controlled. ) And a timing controller 110 for rearranging and dividing the odd data into the odd-numbered horizontal liquid crystal cells Clc and the odd-numbered data LCDs supplied to the even-numbered horizontal liquid crystal cells Clc. The common voltage generator 150 supplies a common voltage to the common electrode at a polarity opposite to that of the data voltage.

The liquid crystal display panel 140 has a structure in which an upper substrate and a lower substrate are bonded to each other.

Gate lines GL1 to GLn and data lines DL1 to DLm cross each other on the lower substrate of the liquid crystal display panel 140. The thin film transistors TFT formed at the intersections of the odd gate lines GL1, GL3, GL5, ... GLn-1 and the data lines DL1 through DLm are respectively the odd gate lines GL1, GL3. The data voltages of the first polarity supplied through the data lines DL1 through DLm are sequentially turned on in response to the scan pulses from GL5, ... GLn-1, and the odd horizontal liquid crystal cells Clc. It supplies to the pixel electrodes Ep formed in the. The thin film transistors TFT formed at the intersections of the even-numbered gate lines GL2, GL4, GL6,... GLn and the data lines DL1 to DLm are the even-numbered gate lines GL2, GL4, GL6, respectively. Pixels formed on the even-numbered horizontal liquid crystal cells Clc by sequentially turning on in response to a scan pulse from GLn to supply data voltages having the second polarity supplied through the data lines DL1 to DLm. Supply to the electrodes Ep. Here, the gate electrodes of the thin film transistors TFT are connected to any one of the gate lines GL1 to GLn, the source electrode is connected to any one of the data lines DL1 to DLm, and the thin film transistors TFT. ) Is connected to any one of the pixel electrodes Ep of the liquid crystal cells Clc. The second polarity is opposite to the first polarity. The liquid crystal cell Clc is charged with a potential difference between the data voltage supplied to the pixel electrode Ep and the common voltage Vcom supplied to the common electrode Ec, and the arrangement of liquid crystal molecules is changed by an electric field formed by the potential difference. The amount of light transmitted is controlled. The common electrode Ec is formed on the upper substrate or the lower substrate according to a method of applying an electric field to the liquid crystal cell. The common electrode Ec is supplied with a common voltage Vcom having a polarity opposite to that of the data voltage supplied to the pixel electrode Ep. For maintaining the charging voltage of the liquid crystal cell Clc for one frame between the pixel electrode Ep of the liquid crystal cell Clc and the front gate line or between the pixel electrode Ep of the liquid crystal cell Clc and a separate storage line. The storage capacitor is formed.

A color filter for realizing color and a black matrix for reducing optical interference between adjacent liquid crystal cells Clc are formed on the upper substrate of the liquid crystal display panel 140. In addition, polarizing plates having optical axes orthogonal to each other are attached to the upper substrate and the lower substrate, and alignment layers for setting the pretilt angle of the liquid crystal are formed on the inner surfaces of the substrates.

The timing controller 110 rearranges and supplies the digital video data RiGiBi from the system (not shown) to the data driving circuit 120 and controls the driving circuits 120 and 130 using timing signals from the system. Generate control signals for To this end, the timing controller 110 includes a data alignment unit 112 and a control signal generator 114 as shown in FIG. 5.

The data aligning unit 112 rearranges the digital video data RiGiBi from the system to the odd-numbered horizontal lines and the odd-numbered data lines DHLo supplied to the liquid crystal cells Clc disposed on the odd-numbered horizontal lines. Separated into even data (DHLe) supplied to the liquid crystal cells (Clc) arranged. The data aligning unit 112 sequentially supplies the odd data DHLo to the data driving circuit 120, and then sequentially supplies the even data DHLe to the data driving circuit 120.

The control signal generator 114 uses the timing signals from the system, that is, the vertical / horizontal synchronization signals Hsync and Vsync, the dot clock DCLK, the data enable signal DE, and the like. A data control signal DDC for controlling the control signal and a gate control signal GDC for controlling the gate driving circuit 130 are generated. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity control signal POL, and the gate control signal GDC is a gate start. A pulse GSP, a gate shift clock GSC, a gate output signal GOE, and the like.

The source start pulse SSP indicates the start point of data, that is, the first liquid crystal cell Clc, in one horizontal period. The source sampling clock SSC instructs the latch operation of data in the data driving circuit 120 based on the rising or falling edge. The source output signal SOE indicates the output of the data driving circuit 120. The polarity control signal POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 140. The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock GSC is a timing control signal input to the shift register in the gate driving circuit 130 to sequentially shift the gate start pulse GSP, and corresponds to a ON period of the thin film transistor TFT. Occurs in width. The gate output signal GOE indicates the output of the gate driving circuit 130.

The data driving circuit 120 uses the odd data DHLo from the timing controller 110 by using gamma reference voltages GMA supplied from a gamma reference voltage generator (not shown). The data voltages of the first polarity are sequentially supplied to the pixel electrodes Ep of the odd horizontal liquid crystal cells Clc via the data lines DL1 to DLm. Subsequently, the data driving circuit 120 converts the even data DHLe from the timing controller 110 into data voltages of the second polarity using the gamma reference voltages GMA supplied from the gamma reference voltage generator. The data voltages of the second polarity are sequentially supplied to the pixel electrodes Ep of even-numbered horizontal liquid crystal cells Clc via the data lines DL1 to DLm. To this end, the data driving circuit 120 includes a shift register, first and second latch arrays, a digital / analog converter, a multiplexer, an output buffer, and the like. The data driving circuit 120 will be described later with reference to FIGS. 8 to 10.

The gate driving circuit 130 sequentially supplies scan pulses to the odd-numbered gate lines GL1, GL3, GL5, ... GLn-1 to select horizontal lines to which data voltages of a first polarity are supplied, and then Scan pulses are sequentially supplied to the first gate lines GL2, GL4, GL6, ... GLn to select horizontal lines to which data voltages of a second polarity are supplied. To this end, the gate driving circuit 130 includes a shift register array, a level shift array, an output buffer array, and the like. The gate driving circuit 130 will be described later with reference to FIGS. 6 and 7.

The common voltage generator 150 generates a high potential common voltage (+ Vcom) and a low potential common voltage (-Vcom) to have opposite polarities of data voltages supplied to the pixel electrode Ep of the liquid crystal cell Clc. The common voltage is supplied to the common electrode Ec of the liquid crystal cell Clc. For example, assuming that the first polarity is positive and the second polarity is negative, the common voltage generator 150 may include pixel electrodes of the liquid crystal cells Clc disposed on odd-numbered horizontal lines. In the period in which the data voltage is supplied to Ep, the low potential common voltage (-Vcom) is supplied to the common electrode Ec of the liquid crystal cells Clc, and the liquid crystal cells Clc of the even horizontal line are provided. In the period where the data voltage is supplied to the pixel electrodes Ep, the high potential common voltage + Vcom is supplied to the common electrode Ec of the liquid crystal cells Clc. In other words, the common voltage generating unit 150 supplies the low potential common voltage (-Vcom) to the common electrode during approximately one half frame period within one frame period, and the high potential common voltage ( + Vcom) is supplied to the common electrode.

6 is a diagram illustrating an internal configuration of the gate driving circuit 130, and FIG. 7 is a waveform diagram of scan pulses generated through FIG. 6.

Referring to FIG. 6, the gate driving circuit 130 includes a shift register array 132, a level shift array 134, and an output buffer array 136.

The shift register array 132 shifts an input signal by one horizontal period (1H) according to the gate shift clock GSC supplied from the timing controller 110 to generate a plurality of stages, that is, a plurality of stages sequentially. Shift registers S / R1 to S / Rn. The shift registers S / R1 to S / Rn sequentially shift the shift output signal shifted by one horizontal period 1H in response to the gate shift clock GSC during the first sub frame period SF1 within one frame period. 1 shifted in response to the generated shift registers S / R1, S / R3, ... S / Rn-1 and the gate shift clock GSC during the second sub frame period SF2 within one frame period. And even shift registers S / R2, S / R4, ... S / Rn which sequentially generate the shifted shift output signal during the period 1H. To this end, the first radix shift register S / R1 receives the gate start pulse GSP as an input signal, and the second and subsequent radix shift registers S / R3, ... S / Rn-1 Respectively, the outputs of the front radix shift registers S / R1, ... S / Rn-3 are supplied as input signals. Also, the first even shift register S / R2 receives the output of the last odd shift register S / Rn-1 as an input signal, and the second and subsequent even shift registers S / R4, ... S / Rn) receives the outputs of the front-end even shift registers S / R2, ... S / Rn-2 as input signals, respectively.

The level shift array 134 includes level shifts L / S1 to L / Sn connected one-to-one to the output terminals of the shift registers S / R1 to S / Rn. The level shifts L / S1 to L / Sn gate shift the shift output signals supplied from the shift registers S / R1 to S / Rn in response to the gate output signal GOE from the timing controller 110. The level shift is performed to the scan pulses SP1 to SPn swinging between the voltage Vgl and the gate high voltage Vgh. Here, the gate high voltage Vgh is a voltage higher than or equal to the threshold voltages of the TFTs of the liquid crystal display panel 140, that is, a gate-on voltage, and the gate low voltage Vgl is lower than the threshold voltages of the TFTs. That is, the gate-off voltage.

The output buffer array 136 is disposed between the level shifters L / S1 to L / Sn and the gate lines GL1 to GLn to scan pulses supplied from the level shifts L / S1 to L / Sn. (SP1 to SPn) are stabilized and output.

Through this configuration, the gate driving circuit 130 sequentially generates the odd scan pulses SP1, SP3, ... SPn-1 during the first sub frame period SF1 within one frame period as shown in FIG. After supplying to the first gate lines GL1, GL3, ... GLn-1, the even scan pulses SP2, SP4, ... SPn are sequentially performed during the second sub frame period SF2 within one frame period. Is generated and supplied to even-numbered gate lines GL2, GL4, ... GLn.

8 is a diagram illustrating an internal configuration of the data driving circuit 120, and FIG. 9 is a circuit diagram illustrating the digital-to-analog converter of FIG.

Referring to FIG. 8, the data driving circuit 120 includes a plurality of integrated circuits (ICs), each integrated circuit having a shift register 122 and a first latch array that are connected dependently between an input line and a data line. 123, the second latch array 124, the gamma compensation voltage generator 125, the digital-to-analog converter (hereinafter referred to as "DAC") 126, the charge share circuit (127) and An output circuit 128.

The shift register 122 shifts the source start pulse SSP from the timing controller 110 according to the source shift clock SSC to generate a sampling signal. In addition, the shift register 122 shifts the source start pulse SSP to transfer the carry signal CAR to the next stage shift register 122.

The first latch array 123 samples the digital video data DHLo and DHLe from the timing controller 110 in response to a sampling signal sequentially input from the shift register 122, and the data DHLHo and DHLe. ) Is latched by one horizontal line, and then data for one horizontal line is output at the same time.

The second latch array 124 latches one horizontal line of data input from the first latch array 123 and then the second latch array 124 of other data ICs during the low logic period of the source output signal SOE. And latched digital video data (DHLo, DHLe) at the same time.

The gamma compensation voltage generator 125 further subdivides a plurality of gamma reference voltages supplied from the gamma reference voltage generator (not shown) by the number of grays that can be expressed as the number of bits of the digital video data DHLo and DHLe. Positive gamma compensation voltages VGH and negative gamma compensation voltages VGL are generated.

As shown in FIG. 9, the DAC 126 includes a P-decoder (PDEC) 1261 to which a positive gamma compensation voltage (VGH) is supplied, and an N-decoder (NDEC) 1262 to a negative gamma compensation voltage (VGL). And a multiplexer 1263 that selects the output of the P-decoder 1261 and the output of the N-decoder 1262 in response to the polarity control signals POL. The P-decoder 1261 decodes the digital video data DHLo, DHLe input from the second latch array 124, and outputs a positive gamma compensation voltage VGH corresponding to the grayscale value of the data. The decoder 122 decodes the digital video data DHLO and DHLe input from the second latch array 94 and outputs a negative gamma compensation voltage VGL corresponding to the gray value of the data. The multiplexer 103 selects the positive gamma compensation voltage VGH and the negative gamma compensation voltage VGL in response to the polarity control signal POL. Here, as shown in FIG. 10, the polarity control signal POL is reversed in polarity at one half of one frame period and maintained at the same polarity for one frame period.

The charge share circuit 127 shorts the neighboring data output channels during the high logic period of the source output signal SOE to output the average value of the neighboring data voltages as the charge share voltage, or to determine the source output signal SOE. The common voltage Vcom is supplied to the data output channels during the high logic period to reduce the sudden change of the positive data voltage and the negative data voltage.

The output circuit 128 includes a buffer to minimize signal attenuation of the data voltage supplied to the data lines DL1 to DLk.

FIG. 11 is a view illustrating a charging sequence of liquid crystal cells for each horizontal line in a liquid crystal display device driven in a line inversion method according to an embodiment of the present invention, and FIG. 12 illustrates that the number of swings of the common voltage is significantly reduced. It is a waveform diagram for. In FIG. 11, only a part of the LCD panel is illustrated for convenience of description. The serial numbers in FIGS. 11 and 12 indicate the supply order of data voltages for each horizontal line.

11 and 12, a liquid crystal display according to an exemplary embodiment of the present invention sequentially supplies a positive data voltage to liquid crystal cells disposed on odd-numbered horizontal lines for driving line inversion. Subsequently, negative data voltages are sequentially supplied to liquid crystal cells arranged in even-numbered horizontal lines. Here, the low potential common voltage (-Vcom) is supplied to the common electrode during the period in which the positive data voltage is supplied to the liquid crystal cells arranged on the odd horizontal lines. The common electrode is supplied with the high potential common voltage (+ Vcom) as shown in FIG. 12 during the period in which the positive data voltage is supplied to the liquid crystal cells arranged in even-numbered horizontal lines. Accordingly, the common voltage Vcom according to the exemplary embodiment of the present invention swings in one frame period, unlike the conventional swing in one horizontal period, and the number of swings of the common voltage Vcom is significantly reduced. Since the number of swings of the common voltage Vcom is reduced, power consumption in the common voltage generator is also drastically reduced. In addition, the liquid crystal display according to the exemplary embodiment of the present invention significantly increases the load of the output buffer of the data driving circuit by sequentially supplying data voltages having the same polarity to the liquid crystal cells for approximately one frame period as shown in FIG. 12. In other words, the power consumed by the data driving circuit can be greatly reduced.

On the other hand, in the above-described liquid crystal display according to an embodiment of the present invention, since the liquid crystal cells disposed on the odd horizontal lines are sequentially charged first, the liquid crystal cells disposed on the even horizontal lines are sequentially charged. There is a possibility that the video characteristic is deteriorated as compared with the conventional art. Accordingly, when the input image is a video, all of the liquid crystal cells are sequentially driven as in the prior art, and when the input image is a still image, the liquid crystal cells are divided by odd / excellent horizontal lines as in the exemplary embodiment of the present invention. You can also drive. This will be described later through another embodiment of the present invention.

FIG. 13 is a block diagram illustrating a liquid crystal display according to another exemplary embodiment. FIG. 14 is an internal configuration diagram of the timing controller of FIG. 13.

Referring to FIG. 13, in a liquid crystal display according to another exemplary embodiment, a plurality of gate lines GL1 through GLn and a plurality of data lines DL1 through DLm cross each other and are defined as intersections thereof. Thin film transistors TFT formed at the intersections of the liquid crystal cells Clc and the gate lines GL1 to GLn and the data lines DL1 to DLm formed in the light emitting diodes to drive the respective liquid crystal cells Clc. A liquid crystal display panel 240 including an image, an image analyzer 260 detecting an input of a still image and a moving image by analyzing input digital video data RiGiBi, and a detection signal from the image analyzer 260. The driving circuits 220 and 230 are controlled to align the digital video data RiGiBi differently according to the property of the image in response to the DS1 and DS2 and to display the aligned data RGB on the liquid crystal display panel 240. The timing controller 210 and the aligned data RGB. The data driving circuit 220 converts the data voltage and supplies the data lines DL1 to DLm and scans according to the attributes of the input image in response to the detection signals DS1 and DS2 from the image analyzer 260. A gate driving circuit 230 for changing a pulse supply order and a common voltage generator 250 supplying a common voltage to the common electrode with a polarity opposite to that of the data voltage.

The liquid crystal display panel 240 is substantially the same as FIG. 4.

The image analyzer 260 analyzes the digital video data RiGiBi input from a system (not shown) to detect whether the input image is a still image or a moving image, and outputs the detected signals DS1 and DS2 to the timing controller. Supply to 210. To this end, the image analyzer 260 alternately stores input digital video data RiGiBi in units of frames using a frame memory, and compares the stored inter-frame data to determine whether the input image is a video or a still image. Detect. The image analyzer 260 supplies the first detection signal DS1 to the timing controller 210 when the input image is a moving image and the second detection signal DS2 when the input image is a still image. Meanwhile, the image analyzer 260 may use another known image detection method such as the use of a motion factor to detect the property of the input image. The image analyzer 260 may be built in the timing controller 210.

The timing controller 210 arranges the digital video data RiGiBi differently according to the property of the image in response to the detection signals DS1 and DS2 from the image analyzer 260, and arranges the aligned data RGB. The driving circuits 220 and 230 are controlled to be displayed on the liquid crystal display panel 240. To this end, the timing controller 110 includes a data alignment unit 212 and a control signal generator 214 as shown in FIG. 14.

When the first detection signal DS1 is input, the data aligning unit 212 sequentially sorts the input digital video data RiGiBi without division of odd data / excellent data, and sorts the sorted data RGB. Supply to the driving circuit 220.

When the second detection signal DS2 is input, the data aligning unit 212 rearranges the input digital video data RiGiBi and supplies radix data supplied to the liquid crystal cells Clc disposed on the odd horizontal lines. DHLo) and rainfall data supplied to the liquid crystal cells Clc arranged on the even-numbered horizontal lines are separated into DHL data. The data aligning unit 212 sequentially supplies the odd data DHLo to the data driving circuit 220, and then sequentially supplies the even data DHLe to the data driving circuit 220.

When the first detection signal DS1 is input, the control signal generator 214 uses the first detection signal DS1 and timing signals Hsync, Vsync, DCLK, and DE from the system, and the like. The first data control signal DDC1 (POL1) for controlling the 220 and the gate control signal GDC for controlling the gate driving circuit 230 are generated. The first data control signal DDC1 (POL1) includes the first polarity control signal POL1 as shown in FIG. 15. The polarity of the first polarity control signal POL1 is inverted every one horizontal period 1H, and its polarity is inverted every one frame period.

When the second detection signal DS2 is input, the control signal generator 214 uses the second detection signal DS2 and timing signals Hsync, Vsync, DCLK, and DE from the system, and the like. A second data control signal DDC2 (POL2) for controlling the 220 and a gate control signal GDC for controlling the gate driving circuit 230 are generated. The second data control signal DDC2 (POL2) includes the second polarity control signal POL2 as shown in FIG. 15. The second polarity control signal POL2 has a polarity that is inverted from the half vertical period (1/2 V), that is, the half frame period, within one frame period. In addition, the polarity of the second polarity control signal POL2 is reversed every one frame period.

The control signal generator 214 links the first or second detection signals DS1 and DS2 input from the image analyzer 260 to the gate driving circuit 230. Details of the plurality of control signals SSP, SSC, SOE, GDC, GSP, GSC, and GOE generated from the control signal generator 214 are substantially the same as those described with reference to FIG. 5.

If the input image is a moving image, the data driving circuit 220 uses the data RGB from the timing controller 210 using gamma reference voltages GMA supplied from a gamma reference voltage generator (not shown). The data voltages are sequentially supplied to the pixel electrodes Ep of the liquid crystal cells Clc via the data lines DL1 to DLm. Here, the data voltages have different polarities for each horizontal line by the first polarity control signal POL1.

If the input image is a still image, the data driving circuit 220 uses the gamma reference voltages GMA supplied from the gamma reference voltage generator (not shown) to the odd data DHLo from the timing controller 210. Convert the data voltages of the first polarity and sequentially supply the data voltages of the first polarity to the pixel electrodes Ep of the odd horizontal liquid crystal cells Clc via the data lines DL1 to DLm. do. Subsequently, the data driving circuit 220 converts the even data DHLe from the timing controller 210 into data voltages of the second polarity using the gamma reference voltages GMA supplied from the gamma reference voltage generator. The data voltages of the second polarity are sequentially supplied to the pixel electrodes Ep of even-numbered horizontal liquid crystal cells Clc via the data lines DL1 to DLm. Here, the first and second polarities of the data voltages are controlled by the second polarity control signal POL2.

As illustrated in FIGS. 8 and 9, the data driving circuit 220 includes a shift register, first and second latch arrays, a digital / analog converter, a multiplexer, an output buffer, and the like. Detailed description thereof will be omitted.

When the input image is a moving image, the gate driving circuit 230 sequentially supplies scan pulses to the gate lines GL1 to GLn in response to the first detection signal DS1 to select horizontal lines to which data voltages are supplied.

If the input image is a still image, the gate driving circuit 230 sequentially supplies scan pulses to the odd-numbered gate lines GL1, GL3, GL5, ... GLn-1 in response to the second detection signal DS2. After selecting the horizontal lines to which the data voltages of the first polarity are supplied, the scan pulses are sequentially supplied to even-numbered gate lines GL2, GL4, GL6, ... GLn to supply horizontal data voltages of the second polarity. Select the lines. To this end, the gate driving circuit 230 includes a shift register array, a level shift array, an output buffer array, and the like. The gate driving circuit 230 will be described later with reference to FIGS. 16 and 17.

The common voltage generator 250 generates a high potential common voltage (+ Vcom) and a low potential common voltage (-Vcom) to be opposite to the polarity of the data voltage supplied to the pixel electrode Ep of the liquid crystal cell Clc. The common voltage having the same is supplied to the common electrode Ec of the liquid crystal cell Clc.

16 is an internal configuration diagram of the gate driving circuit 230, and FIGS. 17A and 17B are waveform diagrams of scan pulses generated when the input image is a moving image and a still image, respectively.

Referring to FIG. 16, the gate driving circuit 230 includes a multiplexer array 232, a shift register array 234, a level shift array 236, and an output buffer array 238.

The multiplexer array 232 selects any one of the shift output signal from the front-end shift register and the shift output signal from the front-end shift register in response to the detection signals DS1 and DS2 to supply the current shift register to the current shift register. And multiplexers (MUX). The multiplexers MUX sequentially connect the plurality of shift registers S / R1 to S / Rn by inputting the output of the front end shift register to the current stage shift register in response to the first detection signal DS1. The multiplexers MUX input the output of the front shift register to the current shift register in response to the second detection signal DS2 to output the odd shift registers S / R1, S / R3, ... S /. Rn-1 is cascaded, and even shift registers S / R2, S / R4, ... S / Rn are cascaded. The front end of the first even shift register S / R2 becomes the last odd shift register S / Rn-1.

The shift register array 234 shifts an input signal by one horizontal period (1H) according to the gate shift clock GSC supplied from the timing controller 210 to generate a plurality of stages, that is, a plurality of stages sequentially. Shift registers S / R1 to S / Rn.

When the first detection signal DS1 is input, the plurality of shift registers S / R1 to S / Rn receive the input signal in one horizontal period according to the gate shift clock GSC supplied from the timing controller 210. 1H) Shift to generate shift output signal sequentially.

On the other hand, when the second detection signal DS2 is input, the odd shift registers S / R1, S / R3, ... S / Rn-1 are applied during the first sub frame period SF1 within one frame period. The shift output signal shifted by one horizontal period (1H) is sequentially generated in response to the gate shift clock GSC. Subsequently, the even shift registers S / R2, S / R4, ... S / Rn correspond to one horizontal period 1H in response to the gate shift clock GSC during the second sub frame period SF2 within one frame period. ) Generates shifted shift output signal sequentially. To this end, the first radix shift register S / R1 receives the gate start pulse GSP as an input signal, and the second and subsequent radix shift registers S / R3, ... S / Rn-1 Respectively, the outputs of the front radix shift registers S / R1, ... S / Rn-3 are supplied as input signals. Also, the first even shift register S / R2 receives the output of the last odd shift register S / Rn-1 as an input signal, and the second and subsequent even shift registers S / R4, ... S / Rn) receives the outputs of the front-end even shift registers S / R2, ... S / Rn-2 as input signals, respectively.

The level shift array 236 includes level shifts L / S1 to L / Sn connected one-to-one to the output terminals of the shift registers S / R1 to S / Rn. The level shifts L / S1 to L / Sn gate-shift the shift output signal supplied from the shift registers S / R1 to S / Rn in response to the gate output signal GOE from the timing controller 210. The level shift is performed to the scan pulses SP1 to SPn swinging between the voltage Vgl and the gate high voltage Vgh. Here, the gate high voltage Vgh is a voltage above the threshold voltage of the TFTs of the liquid crystal display panel 240, that is, the gate-on voltage, and the gate low voltage Vgl is the threshold of the TFTs. Voltage below the voltage, ie the gate-off voltage.

The output buffer array 238 is disposed between the level shifters L / S1 to L / Sn and the gate lines GL1 to GLn to scan pulses supplied from the level shifts L / S1 to L / Sn. (SP1 to SPn) are stabilized and output.

Through this configuration, when the first detection signal DS1 is input, the gate driving circuit 230 generates scan pulses SP1 to SPn and sequentially supplies them to the gate lines GL1 to GLn as shown in FIG. 17A.

When the second detection signal DS2 is input, the gate driving circuit 230 has the odd scan pulses SP1, SP3,... SPn− during the first sub frame period SF1 within one frame period as shown in FIG. 17B. 1) are sequentially generated and sequentially supplied to the odd-numbered gate lines GL1, GL3, ... GLn-1, and then even scan pulses SP2 are performed during the second sub frame period SF2 within one frame period. , SP4, ... SPn are sequentially generated and sequentially supplied to even-numbered gate lines GL2, GL4, ... GLn.

18 is a flowchart illustrating a method of driving a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 18, in the driving method of the liquid crystal display according to another exemplary embodiment of the present invention, the attribute of the input digital video data is detected to determine whether the input image is a video (S10).

If the input image is a moving image as a result of the determination in step S10, the driving method of the liquid crystal display device sequentially arranges the input digital video data without division of odd data / excellent data (SGB).

The driving method of the liquid crystal display apparatus sequentially scans all the gate lines and displays data RGB arranged in the liquid crystal cells arranged on the corresponding horizontal lines in this scanning order. The polarities of the liquid crystal cells are controlled by using the first polarity control signal POL1 whose polarity is inverted at a period of (1H) (S30 and S40).

The driving method of the liquid crystal display device swings the polarity of the common voltage at intervals of one horizontal period (1H) as shown in FIG.

On the other hand, if the determination result in step S10 the input image is a still image, the driving method of the liquid crystal display device is to separate the input digital video data into odd data and even data to align sequentially (DHLo, DHLe) (S60). )

The driving method of the liquid crystal display device sequentially scans the odd gate lines, and then sequentially scans the even gate lines. In addition, data (DHLo, DHLe) arranged in the liquid crystal cells arranged on the horizontal lines are displayed in this scanning order, and the polarities of the liquid crystal cells are inverted at 1/2 of one frame period as shown in FIG. 15. In addition, the polarities of the liquid crystal cells are maintained at the same polarity for one frame period (S70 and S80).

The driving method of the liquid crystal display device swings the polarity of the common voltage at one frame period as shown in FIG. 12 so that the common voltage has the opposite polarity with the liquid crystal cells (S90).

As described above, when the input image is a moving picture, the driving method of the liquid crystal display according to another embodiment of the present invention sequentially drives all liquid crystal cells as in the prior art to prevent display quality deterioration in the moving picture. In the case of a still image, the liquid crystal cells may be driven by dividing the odd / excellent horizontal lines as in the exemplary embodiment of the present invention to reduce the number of swings of the common voltage and reduce the power consumption of the data driving circuit.

As described above, the liquid crystal display and the driving method thereof according to the present invention are supplied to the even-numbered gate line group after supplying the data voltage of the first polarity to the data lines in synchronization with the scan pulses supplied to the odd-numbered gate line group. By supplying a data voltage having a second polarity to the data lines in synchronization with the scan pulses and supplying a common voltage to the common electrode at a polarity opposite to that of the data voltage, the swing frequency of the common voltage can be greatly reduced. . In addition, by supplying data lines of the same polarity to the data lines for approximately one frame period, power consumed in the data driving circuit can be greatly reduced.

Furthermore, the liquid crystal display and the driving method thereof according to the present invention add a device for detecting the property of the input image and drive the liquid crystal cells by dividing each of the odd and excellent horizontal lines only when the input image is a still image. In addition to reducing the number of times, the power consumption of the data driving circuit is reduced, and when the input image is a moving image, all liquid crystal cells may be sequentially driven as in the prior art to prevent display quality degradation in the moving image.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

A liquid crystal display panel including a plurality of gate lines, a plurality of data lines crossing the gate lines, a common electrode, and a pixel electrode; The scan pulses are sequentially supplied to the first gate line group including the first gate lines during every frame period, and the scan pulses are sequentially applied to the second gate line group including the gate lines arranged one by one between the first gate lines. A gate driving circuit for supplying to the circuit; After supplying a data voltage of a first polarity to the data lines in synchronization with the scan pulses supplied to the first gate line group, the data lines are synchronized with the scan pulses supplied to the second gate line group. A data driving circuit for supplying a data voltage of a second polarity; A timing controller configured to control an operation timing of the driving circuits and to generate a polarity control signal for controlling a polarity of data voltages to be supplied to the data lines; And And a common voltage generator for supplying a common voltage to the common electrode at a polarity opposite to that of the data voltage. The method of claim 1, The gate driving circuit, A shift register array including a plurality of stages cascaded to shift an input signal according to a gate shift clock; A level shift array for level shifting the output voltage of the shift register array; And A buffer array formed between the level shift array and the gate lines; And an N-2th stage output of the shift register array is supplied as an input signal of an Nth stage. The method of claim 2, And wherein the polarity control signal is inverted at one half of one frame period and maintained at the same polarity for one frame period. The method of claim 3, wherein The data driving circuit, After a data voltage having a first polarity is supplied to the data lines in synchronization with the scan pulses supplied to the odd gate lines during the odd frame period, the data lines are synchronized with the scan pulses supplied to the even gate lines. Supply a data voltage of a second polarity; After supplying the data voltage of the second polarity to the data lines in synchronization with the scan pulses supplied to the odd gate lines during the even frame period, the data lines in synchronization with the scan pulses supplied to the even gate lines. And a data voltage of the first polarity to be supplied to the liquid crystal display. The method of claim 4, wherein The common voltage generator, Supplying the common voltage of the second polarity to the common electrode in synchronization with the data voltage of the first polarity, and supplying the common voltage of the first polarity to the common electrode in synchronization with the data voltage of the second polarity. A liquid crystal display device. A liquid crystal display panel including a plurality of gate lines, a plurality of data lines crossing the gate lines, a common electrode, and a pixel electrode; An image analyzer for analyzing input data to detect whether video data and still image data are input; A gate driving circuit which supplies a scan pulse to the gate lines and makes a scan pulse supply order different from the scan pulse supply order in the still image; A data driving circuit which supplies a data voltage to the data lines and makes the data voltage polarity inversion period in the moving image shorter than the data voltage inversion period in the still image; A timing controller for controlling an operation timing of the driving circuits and generating a polarity control signal for controlling the polarity of the data voltage; And And a common voltage generator for supplying a common voltage having a polarity opposite to that of the data voltage to the common electrode and shortening a common voltage polarity inversion period in the moving picture to a common voltage inversion period in the still image. Device. The method of claim 6, The gate driving circuit, Sequentially supplying the scan pulses to the gate lines in the video; The scan pulse is sequentially supplied to odd gate lines among the gate lines in the still image, and then sequentially supplied to even gate lines arranged one by one between the odd gate lines. . The method of claim 7, wherein The gate driving circuit, A shift register array including a plurality of stages cascaded to shift an input signal according to a gate shift clock; A level shift array for level shifting the output voltage of the shift register array; A buffer array formed between the level shift array and the gate lines; And The N-1 (N is positive integer) stage output of the shift register array in the moving image is supplied as an input signal of the N stage, and the N-2 stage output of the still image is input signal of the N stage. And a multiplexer array to be supplied to the liquid crystal display. The method of claim 8, The polarity control signal in the video is inverted in polarity every one horizontal period; The polarity control signal of the still image is characterized in that the polarity is reversed at the time half of one frame period, and is maintained at the same polarity for the one frame period. The method of claim 9, The data driving circuit, And a data voltage whose polarity is inverted at intervals of one horizontal period to the data lines in synchronization with the scan pulses supplied to the gate lines according to the polarity control signal in the moving image. The method of claim 9, The data driving circuit, According to the polarity control signal in the still image, after supplying the data voltage of the first polarity to the data lines in synchronization with the scan pulses supplied to the odd gate lines during the odd frame period to the even gate lines Supplying data voltages of a second polarity to the data lines in synchronization with scan pulses to be generated; After supplying the data voltage of the second polarity to the data lines in synchronization with the scan pulses supplied to the odd gate lines during the even frame period, the data in synchronization with the scan pulses supplied to the even gate lines. And supplying a data voltage of the first polarity to lines. A method of driving a liquid crystal display device having a plurality of gate lines, a plurality of data lines crossing the gate lines, a common electrode, and a pixel electrode, and driving circuits for driving the liquid crystal display panel. To Generating a polarity control signal for controlling the operation timing of the driving circuits and for controlling the polarity of the data voltages to be supplied to the data lines; The scan pulses are sequentially supplied to the first gate line group including the first gate lines during every frame period, and the scan pulses are sequentially applied to the second gate line group including the gate lines arranged one by one between the first gate lines. Supplying; The data lines are supplied in synchronization with the scan pulses supplied to the second gate line group after supplying a data voltage having a first polarity to the data lines in synchronization with the scan pulses supplied to the first gate line group. Supplying a data voltage of a second polarity to the second polarity; And And supplying a common voltage to the common electrode with a polarity opposite to that of the data voltage. A method of driving a liquid crystal display device having a plurality of gate lines, a plurality of data lines crossing the gate lines, a common electrode, and a pixel electrode, and driving circuits for driving the liquid crystal display panel. To Analyzing input data to detect whether video data and still image data are input; Generating a polarity control signal for controlling the operation timing of the driving circuits and for controlling the polarity of the data voltages to be supplied to the data lines; Supplying a scan pulse to the gate lines and changing a scan pulse supply order in the moving picture from a scan pulse supply order in the still image; Supplying a data voltage to the data lines and making the data voltage polarity inversion period in the moving image shorter than the data voltage inversion period in the still image; And And supplying a common voltage having a polarity opposite to that of the data voltage to the common electrode, and making the common voltage polarity inversion period in the moving image shorter than the common voltage inversion period in the still image. Driving method.

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