KR101311677B1 - Driving liquid crystal display and apparatus for driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof to improve the display quality of a liquid crystal display device driven by a 2-dot inversion method.

A liquid crystal display according to the present invention comprises: a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; Converts the digital video data into an analog data voltage to be displayed on the liquid crystal panel, and inverts the polarity of the analog data voltage in units of N (N is a positive integer of 2 or more) horizontal period, and analog data voltages of the same polarity generated continuously A data driver for supplying the analog data voltages and the modulated data voltages to the data lines by inserting modulation data voltages having opposite polarities between them; And a controller for supplying the digital video data to the data driver and supplying control signals to the data driver to control the polarity of the analog data voltage and the generation of the modulated data voltage.

Description

Liquid crystal display and its driving method {DRIVING LIQUID CRYSTAL DISPLAY AND APPARATUS FOR DRIVING THE SAME}

1 is a view schematically showing the data polarity of a liquid crystal panel driven in a one dot inversion scheme.

FIG. 2 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a two dot inversion scheme. FIG.

3 is a block diagram schematically illustrating a liquid crystal display device driven in a two dot inversion method.

FIG. 4 is an enlarged view of a 4x4 liquid crystal cell matrix vertically arranged side by side in the liquid crystal panel of FIG.

FIG. 5 is a waveform diagram illustrating data of a 2-dot inversion method filled in a liquid crystal cell matrix as shown in FIG. 4.

6 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

7 shows a Cdm generating circuit according to the first embodiment of the present invention.

8 is a waveform diagram illustrating an input signal and an output signal of a Cdm generator according to a first embodiment of the present invention.

9 is a block diagram showing a data driver according to a first embodiment of the present invention.

10 is a detailed view of a modulation voltage supply unit according to a first embodiment of the present invention.

11 is a signal waveform diagram of a data voltage supplied to a data line according to the first embodiment of the present invention.

12 is a block diagram illustrating a liquid crystal display according to a second embodiment of the present invention.

13 is a view showing a Ccs generating unit according to a second embodiment of the present invention.

14 is a waveform diagram illustrating an input signal and an output signal of a Ccs generator according to a second exemplary embodiment of the present invention.

15 is a block diagram showing a data driver according to a second exemplary embodiment of the present invention.

16 is a view showing in detail the charge share voltage supply and modulation voltage supply according to a second embodiment of the present invention.

17 is a signal waveform diagram of a data voltage supplied to a data line according to a second embodiment of the present invention.

Description of the Related Art

61,161: timing controller 62,162: data driver

63,163: gate driver 64,164: liquid crystal panel

65,165: Cdm generator 166: Ccs generator

81,181: first latch 82,182: shift register

83,183: second latch 84,184: digital-to-analog converter

85,185: modulation voltage supply unit 86: buffer

186: Charge share voltage supply unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for improving display quality of a liquid crystal display device driven by a 2-dot inversion method.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal cells according to a video signal. In an active matrix type liquid crystal display, switching elements are formed in each liquid crystal cell, which is advantageous for displaying a moving image. A thin film transistor (hereinafter referred to as "TFT") is mainly used as a switching element.

The LCD is driven in an inversion manner to reduce flicker and afterimage by periodically inverting the polarity of data charged in the liquid crystal cell. The inversion method includes a line inversion method of inverting the polarity of data between adjacent liquid crystal cells in the vertical line direction, a version method of inverting the polarity of data between adjacent liquid crystal cells in the horizontal line direction, a vertical line direction and a horizontal line direction There is a dot inversion method in which the polarity of data between adjacent liquid crystal cells is reversed. Of these inversion methods, the dot inversion method is mainly selected because flicker hardly appears in the vertical and horizontal directions.

In the dot inversion scheme, as illustrated in FIG. 1, polarities of data supplied to adjacent liquid crystal cells in the vertical direction are opposite to each other, and polarities of data supplied to adjacent liquid crystal cells in the horizontal direction are opposite to each other. The polarity of the data is inverted every frame (Fn-1, Fn). The dot inversion method is most widely used in liquid crystal display devices because flicker is minimized in both the vertical and horizontal directions.

In the dot inversion scheme of FIG. 2, the polarity of data is inverted in units of two dots in the horizontal and vertical directions. The two-dot inversion method as shown in FIG. 2 has the advantage of lower power consumption than the one-dot inversion method as shown in FIG.

3 schematically shows a conventional liquid crystal display device driven in a two dot inversion method.

Referring to FIG. 3, a conventional liquid crystal display device includes a liquid crystal panel 34 in which data lines D1 to Dm and gate lines G1 to Gn cross each other, and TFTs for driving the liquid crystal cell Clc are formed at the intersections thereof. ), A data driver 32 for supplying data to the data lines D1 to Dm of the liquid crystal panel 34, and a gate for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 34. The driver 33 and the timing controller 31 for controlling the data driver 32 and the gate driver 33 are provided.

The data driver 32 includes a shift register for sampling a clock, a register for temporarily storing data, and a latch for storing data one line at a time in response to a clock signal from the shift register and simultaneously outputting one line of data. A digital / analog converter for selecting a positive / negative gamma voltage corresponding to the digital data value from the latch, and a data line (D1 to Dm) to which analog data converted by the positive / negative gamma voltage is supplied. It consists of a multiplexer for selecting and an output buffer connected between the multiplexer and the data line. The data driver 32 inverts the polarity of the data voltages supplied to the data lines D1 to Dm in units of two horizontal periods according to the two dot inversion method, and uses the data voltage as a source output enable signal. The supply lines are supplied to the data lines D1 to Dm of the liquid crystal panel 34 according to SOE.

The gate driver 33 includes a shift register that sequentially generates scan pulses, and a level shifter for shifting the voltage of the scan pulses to a level suitable for driving the liquid crystal cell Clc. The gate driver 33 sequentially supplies scan pulses to the gate lines G1 to Gn under the control of the timing controller 31.

The timing controller 31 uses the vertical / horizontal synchronization signals V and H and the clock CLK to control the gate control signal GDC for controlling the gate driver 33 and the data for controlling the data driver 32. Generate a control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, a polarity signal POL, and the like. Here, the source output signal SOE is a signal indicating the output time of the data. The gate control signal GDC includes a gate shift clock (GSC), a gate output signal (GOE), a gate start pulse (GSP), and the like. Here, the gate output signal GOE is a control signal indicating an output time point of the gate driver 33.

FIG. 4 is an enlarged view of a 4x4 liquid crystal cell matrix vertically arranged side by side in the liquid crystal panel, and FIG. 5 shows a data voltage of a 2-dot inversion type supplied to four liquid crystal cells shown in FIG. .

4 and 5, the liquid crystal display of the two dot inversion method inverts the polarity of the data voltage every two horizontal line periods. Therefore, the positive polarity voltage higher than the common voltage Vcom is applied to the liquid crystal cell A of the first horizontal line HL1 and the liquid crystal cell B of the second horizontal line HL2 connected to the first data line DL1. On the other hand, the liquid crystal cell C of the third horizontal line HL3 connected to the first data line DL1 and the liquid crystal cell D of the fourth horizontal line HL4 are connected to the common voltage Vcom. Low negative voltage is applied.

However, in the two-dot inversion system, a liquid crystal cell to which a positive voltage (or negative voltage) rising (or falling) from a negative voltage (or positive voltage) is applied, and from the positive voltage (or negative voltage) The amount of charge of data charged in the liquid crystal cell is different between the liquid crystal cells to which the variable positive voltage (or negative voltage) is applied. This is because the rising time (or falling time) of the positive voltage (or negative voltage) rising (or falling) from the negative voltage (or positive voltage) is long, whereas from the positive voltage This is because the rising time of the changing positive voltage is relatively short. Due to such a difference in charging characteristics, the second and fourth horizontal lines HL2, even though the data voltages of the same gray level, are compared with the liquid crystal cells A and C of the first and third horizontal lines HL1 and HL3. The liquid crystal cells B and D of HL4 appear brighter, and as a result, a luminance difference occurs between neighboring horizontal lines. As the line resistance increases, that is, the liquid crystal cell moves away from the data integrated circuit, the problem becomes more prominent due to the increase in the RC delay time.

Accordingly, it is an object of the present invention to provide a liquid crystal display device and a driving method thereof to improve the display quality of a liquid crystal display device driven by a 2-dot inversion method.

In order to achieve the above object, the liquid crystal display according to the first embodiment of the present invention comprises a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are arranged; Converts the digital video data into an analog data voltage to be displayed on the liquid crystal panel, and inverts the polarity of the analog data voltage in units of N (N is a positive integer of 2 or more) horizontal period, and analog data voltages of the same polarity generated continuously A data driver for supplying the analog data voltages and the modulated data voltages to the data lines by inserting modulation data voltages having opposite polarities between them; And a controller for supplying the digital video data to the data driver and supplying control signals to the data driver to control the polarity of the analog data voltage and the generation of the modulated data voltage.

The control signal includes a first control signal indicating a generation period of the modulated data voltage; And a second control signal indicating a polarity inversion period of the analog data voltage.

The liquid crystal display according to the first embodiment of the present invention further includes a gate driver for supplying scan signals synchronized with the analog data voltages to the gate lines; The controller further generates a third control signal for controlling the digital data shifting of the data driver and an output of the analog data voltages, and a fourth control signal for controlling the gate driver.

The controller may include a timing controller configured to supply the digital video data to the data driver and to control an operation timing of the data driver and the gate driver using the second to fourth control signals; And a data modulation signal generator for generating the first control signal.

The data modulation signal generator may be embedded in the timing controller.

The third control signal includes a source output signal indicating an output period of the analog data voltage.

The first control signal is generated as a pulse swinging between a first logic value and a second logic value; The first logic section is generated as the first logic value in the even-numbered first logic section of the source output signal, and the second logic value is generated during the odd-numbered first logic section and the other second logic section.

The data driver inverts the polarity of the analog data voltage in units of two horizontal periods in response to the second control signal.

In response to the first logic value of the first control signal, the data driver inserts a modulated data voltage having an opposite polarity between the continuously generated analog data voltages of the same polarity and the analog data voltages. And a modulation voltage supply unit supplying the modulation data voltage to the data lines.

The modulation voltage supply unit may include: a first multiplex for selectively outputting a positive analog data voltage and a negative analog data voltage in response to the second control signal; A second multiplex for selectively outputting a positive modulation data voltage and a negative modulation data voltage in response to the second control signal in which the logic value is inverted; And a switch switched according to a logic value of the first control signal so that either one of the first multiplex output or the second multiplex output is supplied to the data line.

The switch connects the first multiplex to the data line in response to a second logic value of the first control signal, and transmits the data to the second multiplex in response to a first logic value of the first control signal. Connect to the line.

A liquid crystal display according to a second embodiment of the present invention comprises: a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; Converts the digital video data into an analog data voltage to be displayed on the liquid crystal panel, and inverts the polarity of the analog data voltage in units of N (N is a positive integer of 2 or more) horizontal period, and analog data voltages of the same polarity generated continuously Inserting a modulation data voltage having a polarity opposite to that between them, and inserting a charge share voltage between analog data voltages of different polarities that are generated in succession, so that the analog data voltages, the modulation data voltage, and the charge share voltage A data driver for supplying the data lines to the data lines; A controller for supplying the digital video data to the data driver, controlling the polarity of the analog data voltage, and supplying control signals to the data driver to control generation of the modulated data voltage and supply of the charge share voltage. do.

The charge share voltage is an intermediate voltage between the positive analog data voltage and the negative analog data voltage which are continuously generated.

The control signal comprises: a 1-1 control signal indicating a generation period of the modulated data voltage; A 1-2 control signal indicating a supply period of the charge share voltage; And a second control signal indicating a polarity inversion period of the analog data voltage.

A liquid crystal display according to a second embodiment of the present invention further includes a gate driver for supplying scan signals synchronized with the analog data voltages to the gate lines; The controller further generates a third control signal for controlling the digital data shifting of the data driver and an output of the analog data voltages, and a fourth control signal for controlling the gate driver.

The controller may include a timing controller configured to supply the digital video data to the data driver and to control an operation timing of the data driver and the gate driver using the second to fourth control signals; A data modulation signal generator for generating the first-first control signal; A charge share control signal generator for generating the 1-2 control signal is provided.

The data modulation signal generator and the charge share control signal generator may be embedded in the timing controller.

The third control signal includes a source output signal indicating an output period of the analog data voltage.

The 1-1 control signal is generated as a pulse swinging between a first logic value and a second logic value; The first logic section is generated as the first logic value in the even-numbered first logic section of the source output signal, and the second logic value is generated during the odd-numbered first logic section and the other second logic section.

The 1-2 control signal is generated as a pulse swinging between a first logic value and a second logic value; The first logic value is generated in the odd-numbered first logic section of the source output signal, and the second logic value is generated during the even-numbered first logic section and the other second logic section.

The data driver inverts the polarity of the analog data voltage in units of two horizontal periods in response to the second control signal.

In response to the first logic value of the first-first control signal, the data driver inserts a modulation data voltage having an opposite polarity among the analog data voltages of the same polarity that is generated continuously and the analog data. A modulation voltage supply unit supplying voltages and the modulated data voltages to the data lines; In response to the first logic value of the 1-2 control signal, a charge share voltage is inserted between the consecutively generated analog data voltages of different polarities, and the analog data voltages and the charge share voltage are converted into the charge share voltage. A charge share voltage supply unit is provided to supply data lines.

The modulation voltage supply unit may include: a first multiplex for selectively outputting a positive analog data voltage and a negative analog data voltage in response to the second control signal; A second multiplex for selectively outputting a positive modulation data voltage and a negative modulation data voltage in response to the second control signal in which the logic value is inverted; And a switch switched according to a logic value of the first-first control signal to supply either the first multiplex output or the second multiplex output to the data line.

The switch connects the first multiplex to the data line in response to a second logic value of the first-first control signal and the second multiplier in response to a first logic value of the first-one control signal. Connect a flex to the data line.

The charge share voltage supply unit includes a power supply unit for generating the charge share voltage;

And a switch for controlling supply of the generated charge share voltage to the data line by switching according to a logic value of the 1-2 control signal.

The switch connects the power supply unit to the data line in response to the first logic value of the 1-2 control signal and connects the power supply unit to the data line in response to the second logic value of the 1-2 control signal. Disconnect the connection.

The driving method of the liquid crystal display according to the first embodiment of the present invention converts the digital video data into an analog data voltage to be displayed on the liquid crystal panel, and N (N is a positive integer of 2 or more). A first step of controlling the polarity inversion period and generating control signals for controlling the modulation data voltage of the opposite polarity interposed between successively generated analog data voltages of the same polarity; And supplying the analog data voltages and the modulated data voltages generated in response to the control signals to a data line.

A method of driving a liquid crystal display according to a second exemplary embodiment of the present invention converts digital video data into an analog data voltage to be displayed on a liquid crystal panel, wherein N (N is a positive integer of 2 or more). Controls the polarity inversion period and controls the modulation data voltage of the opposite polarity inserted between successive analogue voltages of the same polarity, or inserts between analog data voltages of the different polarity which are continuously generated A first step of generating control signals to control the charge share contact voltage; And supplying the analog data voltages, the modulated data voltage, and the charge share voltage generated in response to the control signals to a data line.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 17.

6 to 11 illustrate a liquid crystal display and a driving method thereof according to the first embodiment of the present invention.

Referring to FIG. 6, in the liquid crystal display according to the first exemplary embodiment of the present invention, a data modulation control for outputting a modulated data voltage having a polarity opposite to that of an output data voltage during a high logic period of an even-numbered source output signal SOE. The signal generator 65 (hereinafter referred to as a "Cdm generation circuit") and the data voltage whose polarity is inverted in a 2-dot inversion scheme in response to the source output signal SOE are applied to the data lines D1 to 1 of the liquid crystal panel 64. Data driver 62 for supplying Dm), gate driver 63 for supplying scan pulses to gate lines G1 to Gn of liquid crystal panel 64, data driver 62 and gate driver 63 ) And a timing controller 61 for controlling the Cdm generator 65.

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 154 is formed such that the data lines D1 to Dm and the gate lines G1 to Gn are orthogonal to each other on the lower glass substrate. TFTs formed at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn receive data on the data lines D1 to Dm in response to scan pulses from the gate lines G1 to Gn. Supply to the liquid crystal cell (Clc). For this purpose, the gate electrodes of the TFTs are connected to the gate lines G1 to Gn, and the source electrodes are connected to the data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. A common voltage (Vcom) is supplied to the common electrode facing the pixel electrode.

The Cdm generator 65 includes a plurality of logic gates and generates a data modulation control signal Cdm using the input source output signal SOE and the trigger signal Tout. The Cdm generator 65 may be embedded in the timing controller 61, and a detailed description thereof will be described in detail with reference to FIGS. 7 and 8.

The data driver 62 receives the digital data RGB input from the timing controller 61, the control signal DDC input from the timing controller 61, and the data modulation control signal Cdm input from the Cdm generator 65. In response, the data lines are supplied to the data lines D1 to Dm of the liquid crystal panel 64. That is, the data driver 62 generates data having the same polarity for two horizontal periods according to the polarity control signal POL included in the control signal DDC from the timing controller 61, and then reverses the polarity of the data. Invert the polarities of neighboring data with each other. In addition, the data driver 62 supplies a negative voltage to a section of the positive voltage that changes from the positive voltage according to the data modulation control signal Cdm input from the Cdm generator 65 for a predetermined time. A positive voltage is supplied for a period of time to a negative voltage range that varies from the voltage to match the charge amount of the liquid crystal cells positioned in the even horizontal lines and the liquid crystal cells located in the even horizontal lines. The data driver 62 will be described in detail with reference to FIGS. 9 to 11.

The gate driver 63 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signal GDC from the timing controller 61.

The timing controller 61 is configured to control the gate control signal GDC for controlling the gate driver 63 and the data driver 622 by using the vertical / horizontal synchronization signals V and H and the clock CLK. Generate a data control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity signal POL, and the like. The gate control signal GDC includes a gate shift clock GSC, a gate output signal GOE, a gate start pulse GSP, and the like.

In addition, the timing controller 61 supplies the trigger signal Tout generated from the trigger circuit included therein to the Cdm generation circuit 65 together with the source output signal SOE.

7 shows a Cdm generation circuit, and FIG. 8 is a waveform diagram showing an input signal and an output signal of the Cdm generation circuit.

Referring to FIG. 7, the Cdm generator 65 may perform an exclusive OR operation on the source output signal SOE: A and the trigger signal Tout: B input from the timing controller 61. 71 and an AND gate 72 for performing an AND operation on the output signal C and the source output signal A of the exclusive OR gate 71. Here, the trigger unit for generating the trigger signal Tout is incorporated in the timing controller 61, and the data modulation control signal Cdm, which is an output signal of the A waveform, the B waveform, the C waveform, and the Cdm generator 65, is used. The waveform is as shown in FIG. The data modulation control signal Cdm generated by the Cdm generation unit 65 changes its logic value to high only during the high logical section of the even-numbered source output signal SOE, thereby causing the polarity opposite to the output data. The modulated data of is outputted. That is, during the high logic period of the even-numbered source output signal SOE, the logic value of the data modulation control signal Cdm changes to high, whereby the data output voltage from the data driver 62 changes from positive polarity to positive polarity. When changed, the data modulation control signal Cdm controls to output a negative modulation data voltage during the high logic period. In addition, when the data output voltage from the data driver 62 changes from negative polarity to negative polarity, the data modulation control signal Cdm controls to output a positive modulation data voltage during the high logic period.

9 is a block diagram illustrating a data driver according to a first exemplary embodiment of the present invention.

Referring to FIG. 9, the data driver 62 includes a plurality of integrated circuits (ICs), each integrated circuit having a shift register 82 and a first latch 81 connected in a dependent manner between an input line and a data line. ), A second latch 83, a digital-to-analog converter (hereinafter referred to as a "DAC") 84, a modulation voltage supply unit 85, and a buffer 86.

The shift register 82 shifts the source start pulse SSP from the timing controller 61 in accordance with the source shift clock signal SSC to generate a sampling signal. In addition, the shift register 82 shifts the source start pulse SSP to transfer a carry signal CAR to the next stage shift register 82.

The first latch 81 samples and stores the digital data RGB according to the sampling signal input from the shift register 82, and supplies the stored digital data to the second latch 83.

The second latch 83 latches the data EFD and RGB input from the first latch 81 and then a second latch in another integrated circuit in response to the source output signal SOE from the timing controller 61. The digital data for one horizontal line latched together with 83 is simultaneously output. At this time, the source output signal SOE is generated approximately every one horizontal period, and each pulse width is constant.

The DAC 84 converts the digital data RGB from the second latch 83 to the positive analog data voltage VPG or the negative analog data voltage VNG according to the polarity signal POL from the timing controller 61. Convert to In addition, the voltage generated from the DAC 84 controls the polarity of the data in accordance with an inversion scheme such as a dot inversion, N dot inversion, line inversion, column inversion scheme, etc. in response to the polarity signal POL.

The modulation voltage supply unit 85 is driven in accordance with the polarity signal POL from the timing controller 61 and the data modulation control signal Cdm from the Cdm generator 65 so that the analog data voltage as the data output voltage is positive in polarity. A negative modulation data voltage is generated when changing to a positive polarity, and a positive modulation data voltage is generated when an analog data voltage as a data output voltage is changed from negative to negative polarity. The modulation voltage supply unit 85 will be described in detail with reference to FIG. 10.

The buffer 186 outputs the analog data voltages VPG and VNG input from the DAC 184 and the modulated data voltages input from the modulation voltage supply unit 85 to the data lines D1 to Dm without signal attenuation. .

In Fig. 9, reference numeral 'R' denotes a line resistance between the output terminal of the data driver 62 and the data lines D1 to Dm.

10 is a detailed view of a modulation voltage supply unit, and FIG. 11 is a signal waveform diagram of a data voltage supplied to a data line.

Referring to FIG. 10, the modulation voltage supply unit 85 selectively outputs a positive analog data voltage VPG and a negative analog data voltage VNG in response to a polarity signal POL. Switching according to the MUX1, the second multiplex MUX2 for selectively outputting the positive modulation data voltage and the negative modulation data voltage in response to the polarity signal POL, and the data modulation control signal Cdm. And a switching unit SW1 for alternately outputting the analog data voltage and the modulated data voltage.

The first multiplex MUX1 is connected to terminal 1, which is an input terminal of the switching unit SW1, and the second multiplex MUX2 is connected to terminal 2, which is an input terminal of the switching unit SW1. Polar signals POLs having opposite polarities are applied to each of the first and second multiplexes MUX1 and MUX2. The first multiplex MUX1 alternates the positive analog data voltage VPG and the negative analog data voltage VNG in units of two horizontal periods according to the polarity signal POL supplied from the timing controller 61. The selected gamma voltages VPG and VNG are supplied to the switching unit SW1. The second multiplex MUX2 alternately selects a positive modulation data voltage and a negative modulation data voltage in units of two horizontal periods according to the polarity signal POL supplied from the timing controller 61 and selects the selected modulation data voltage. It supplies to the switching part SW1. In this case, since the polarity signal POL having the opposite polarity is supplied to the second multiplex MUX2 simultaneously with the polarity signal POL supplied to the first multiplex MUX1, the polarity of the selected modulation data voltage is the first multiplex. The polarity of the gamma voltage selected at (MUX1) is reversed. That is, when the positive polarity signal POL is supplied to the first multiplex MUX1 and the positive analog data voltage VPG is selected, the second polarity MUX2 has the negative polarity signal POL. Is supplied to select the negative modulation data voltage.

The switching unit SW1 includes a terminal 1 connected to the first multiplex MUX1, a terminal 2 connected to the second multiplex MUX2, and a terminal 3 connected to the data line. The switching unit SW1 is switched according to the data modulation control signal Cdm and the modulated data voltages supplied from the analog data voltages VPG and VNG supplied from the first multiplex MUX1 and the second multiplex MUX2. Select alternately. That is, the switching unit SW1 switches so that the input terminal (terminal 1) connected to the first multiplex MUX1 is connected to the output terminal (terminal 3) while the data modulation control signal Cdm is LOW. The analog data voltage according to the 2-dot inversion scheme is output to the data lines D1 to Dm. In addition, the switching unit SW1 is configured such that the input terminal (terminal 2) connected to the second multiplex MUX2 is connected to the output terminal (terminal 3) while the data modulation control signal Cdm maintains the high logic state. When the analog data voltage according to the 2-dot inversion method is changed from positive polarity to positive polarity, the negative modulation data voltage is changed while the analog data voltage is changed from negative polarity to negative polarity. Output to the data lines D1 to Dm.

As described above, in the liquid crystal display according to the first exemplary embodiment of the present invention, as shown in FIG. Is applied. Accordingly, the rising time of the positive voltage that changes from the positive voltage increases, and the polling time of the negative voltage that changes from the negative voltage increases, thereby reducing the amount of charge Qe charged in the liquid crystal cells of the even-numbered horizontal line. do. As a result, the liquid crystal display and the driving method according to the first exemplary embodiment of the present invention reduce the amount of charge Qe charged in the liquid crystal cells of the even-numbered horizontal line, and thus the amount of charge Qo charged in the liquid crystal cells of the odd-numbered horizontal line. ), The display quality of the liquid crystal display device driven by the 2-dot inversion method can be improved.

12 to 17 illustrate a liquid crystal display and a driving method thereof according to the second embodiment of the present invention.

Referring to FIG. 12, in the liquid crystal display according to the second exemplary embodiment of the present invention, data modulation control is performed such that a modulated data voltage having a polarity opposite to that of an output data voltage is output during a high logic period of an even-numbered source output signal SOE. Charge share control signal generation unit 166 (hereinafter referred to as "Ccs generation") for outputting the charge share voltage during the high logic section of the signal generation unit 165 and the odd-numbered source output signal SOE. And a data driver 162 for supplying a data voltage whose polarity is inverted in a 2-dot inversion scheme in response to the source output signal SOE to the data lines D1 to Dm of the liquid crystal panel 164. ), A gate driver 163 for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 164, a data driver 162, a gate driver 163, a Cdm generator 165, and a Ccs. Timing controller 1 for controlling the generator 166. 61).

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 154 is formed such that the data lines D1 to Dm and the gate lines G1 to Gn are orthogonal to each other on the lower glass substrate. TFTs formed at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn receive data on the data lines D1 to Dm in response to scan pulses from the gate lines G1 to Gn. Supply to the liquid crystal cell (Clc). For this purpose, the gate electrodes of the TFTs are connected to the gate lines G1 to Gn, and the source electrodes are connected to the data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. A common voltage (Vcom) is supplied to the common electrode facing the pixel electrode.

The Cdm generator 165 includes a plurality of logic gates and generates a data modulation control signal Cdm using the input source output signal SOE and the trigger signal Tout. The Cdm generating unit 165 may be embedded in the timing controller 161, and a detailed description thereof has been described in detail with reference to FIGS. 7 and 8.

The Ccs generating unit 166 is composed of one AND gate and generates the charge share control signal Ccs using the input source output signal SOE and the trigger signal Tout. The Ccs generator 166 may be embedded in the timing controller 161, and a detailed description thereof will be described in detail with reference to FIGS. 13 and 14.

The data driver 162 receives the digital data RGB input from the timing controller 161, the control signal DDC input from the timing controller 161, and the data modulation control signal Cdm input from the Cdm generator 165. And in response to the charge share control signal Ccs input from the Ccs generating unit 166, to the data lines D1 to Dm of the liquid crystal panel 64. That is, the data driver 162 generates data having the same polarity for two horizontal periods according to the polarity control signal POL included in the control signal DDC from the timing controller 161, and then reverses the polarity of the data. Invert the polarities of neighboring data with each other. In addition, the data driver 162 generates a negative voltage for a predetermined time in a section of the positive voltage that changes from the positive voltage according to the data modulation control signal Cdm input from the Cdm generator 165. A positive voltage is generated for a predetermined time in a section of the negative voltage that changes from the voltage to match the charging amount of the liquid crystal cells positioned in the even-numbered horizontal lines and the liquid crystal cells positioned in the even-numbered horizontal lines. In addition, the data driver 162 supplies a charge share voltage (Charge-Share-Voltage) to the data line according to the charge share control signal Ccs input from the Ccs generator 166. The data driver 162 will be described in detail with reference to FIGS. 15 to 17.

The gate driver 163 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signal GDC from the timing controller 161.

The timing controller 61 is configured to control the gate control signal GDC for controlling the gate driver 163 and the data driver 162 by using the vertical / horizontal synchronization signals V and H and the clock CLK. Generate a data control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity signal POL, and the like. The gate control signal GDC includes a gate shift clock GSC, a gate output signal GOE, a gate start pulse GSP, and the like.

In addition, the timing controller 161 supplies the trigger signal Tout generated from the trigger circuit included therein to the Cdm generator 165 and the Ccs generator 166 together with the source output signal SOE.

FIG. 13 shows a Ccs generating unit, and FIG. 14 is a waveform diagram showing an input signal and an output signal of the Ccs generating unit.

Referring to FIG. 13, the Ccs generator 166 may perform an AND operation on a source output signal SOE: A and a trigger signal Tout: B inputted from the timing controller 161. 171). Here, the trigger unit for generating the trigger signal Tout is incorporated in the timing controller 161. The waveform of the charge share control signal Ccs, which is an output signal of the A waveform, the B waveform, and the Ccs generator 166, is shown in FIG. As shown in 14. The charge share control signal Ccs generated by the Ccs generating unit 166 changes the logic value to high only during the high logical section of the odd-numbered source output signal SOE, thereby causing the charge share voltage to be output. do.

15 is a block diagram illustrating a data driver according to a second exemplary embodiment of the present invention.

Referring to FIG. 15, the data driver 162 includes a plurality of integrated circuits (ICs), each of which includes a shift register 182 and a first latch 181 connected in cascade between an input line and a data line. ), A second latch 183, a digital-to-analog converter (hereinafter referred to as a "DAC") 184, a modulation voltage supply unit 185, a charge share voltage supply unit 186, and a buffer 187. It is provided.

The shift register 182 shifts the source start pulse SSP from the timing controller 161 according to the source shift clock signal SSC to generate a sampling signal. In addition, the shift register 182 shifts the source start pulse SSP to transfer the carry signal CAR to the next stage shift register 182.

The first latch 181 samples and stores the digital data RGB according to the sampling signal input from the shift register 182, and supplies the stored digital data to the second latch 183.

The second latch 183 latches the data EFD and RGB input from the first latch 181, and then a second latch in another integrated circuit in response to the source output signal SOE from the timing controller 161. The digital data of one horizontal line latched together with 183 is simultaneously output. At this time, the source output signal SOE is generated approximately every one horizontal period, and each pulse width is constant.

The DAC 184 outputs the digital data RGB from the second latch 183 to the positive analog data voltage VPG or the negative analog data voltage VNG according to the polarity signal POL from the timing controller 161. Convert to In addition, the voltage generated from the DAC 184 controls the polarity of the data in accordance with an inversion scheme such as a dot inversion, N dot inversion, line inversion, column inversion scheme, etc. in response to the polarity signal POL.

The modulation voltage supply unit 185 is driven according to the polarity signal POL from the timing controller 161 and the data modulation control signal Cdm from the Cdm generation unit 165 so that the analog data voltage as the data output voltage is positive in polarity. A negative modulation data voltage is generated when changing to a positive polarity, and a positive modulation data voltage is generated when an analog data voltage as a data output voltage is changed from negative to negative polarity.

The charge share voltage supply unit 186 buffers the charge share voltage during the high logic period of the charge share control signal Ccs generated from the Ccs generator 166, that is, the high logic period of the odd-numbered source output signal SOE. 187) to the data line. Here, the charge share voltage is an intermediate voltage between the positive data voltage and the negative data voltage and is equal to or similar to the common voltage Vcom supplied to the common electrode of the liquid crystal cell. The charge share voltage may be generated by a switch circuit that supplies a voltage supplied from a power supply circuit disposed outside the data integrated circuit to the data line during the high logic period of the odd-numbered source output signal SOE.

The charge share voltage supply unit 186 and the modulation voltage supply unit 185 will be described in detail with reference to FIG. 16.

The buffer 187 attenuates the analog data voltages VPG and VNG input from the DAC 184, the modulation data voltage input from the modulation voltage supply unit 185, and the charge share voltage input from the charge share voltage supply unit 186. It serves to output to the data lines (D1 to Dm) without.

In FIG. 15, reference numeral 'R' denotes a line resistance between the output terminal of the data driver 162 and the data lines D1 to Dm.

FIG. 16 illustrates the charge share voltage supply unit and the modulation voltage supply unit in detail, and FIG. 17 is a signal waveform diagram of the data voltage supplied to the data line.

Referring to FIG. 16, the modulation voltage supplying unit 185 may selectively output a positive analog data voltage VPG and a negative analog data voltage VNG in response to the polarity signal POL. MUX3), a fourth multiplex MUX4 for selectively outputting a positive modulation data voltage and a negative modulation data voltage in response to the polarity signal POL, and a data modulation control signal Cdm. And a switching unit SW2 for alternately outputting the analog data voltage and the modulated data voltage. In addition, the charge share voltage supply unit 186 is composed of a switching unit SW3 for outputting a voltage Vcom supplied from a power supply circuit disposed outside the data integrated circuit by switching according to the charge share control signal Ccs. .

The third and fourth multiplexes MUX3 and MUX4 are respectively connected to the terminal 4 and the terminal 5, which are input terminals of the switching unit SW2, and the polarity signals POL having opposite polarities are applied to each other. The third multiplex MUX3 alternates the positive analog data voltage VPG and the negative analog data voltage VNG in units of two horizontal periods according to the polarity signal POL supplied from the timing controller 161. The selected gamma voltages VPG and VNG are supplied to the switching unit SW2. The fourth multiplex MUX4 alternately selects a positive modulation data voltage and a negative modulation data voltage in units of two horizontal periods according to the polarity signal POL supplied from the timing controller 161 and selects the selected modulation data voltage. Supply to switching unit SW2. In this case, since the polarity signal POL having the opposite polarity is supplied to the fourth multiplex MUX4 simultaneously with the polarity signal POL supplied to the third multiplex MUX3, the polarity of the selected modulation data voltage is the third multiplex. The polarity of the analog data voltage selected by (MUX3) is reversed. That is, when the positive polarity signal POL is supplied to the third multiplex MUX3 and the positive analog data voltage VPG is selected, the fourth multiplex MUX4 has the negative polarity signal POL. Is supplied to select the negative modulation data voltage.

The switching unit SW2 includes a terminal 4 connected to the third multiplex MUX3, a terminal 5 connected to the fourth multiplex, and a terminal 6 commonly connected to the data line and the charge share voltage supply unit. The switching unit SW2 is switched according to the data modulation control signal Cdm, and the modulated data voltages supplied from the analog data voltages VPG and VNG supplied from the third multiplex MUX3 and the fourth multiplex MUX4. Select alternately. That is, the switching unit SW2 switches so that the input terminal (terminal 4) connected to the third multiplex MUX3 is connected to the output terminal (terminal 6) while the data modulation control signal Cdm is low. The analog data voltage according to the 2-dot inversion scheme is output to the data lines D1 to Dm. In addition, the switching unit SW2 is connected to the fourth multiplex MUX4 while the data modulation control signal Cdm maintains the high logic state, that is, during the high logic section of the even source output signal SOE. The terminal (terminal 5) is switched to be connected to the output terminal (terminal 6). Accordingly, the switching unit SW2 has a negative modulation data voltage in a period in which the analog data voltage according to the 2-dot inversion method changes from positive polarity to positive polarity, and in a period in which the analog data voltage changes from negative polarity to negative polarity. The positive modulation data voltage is output to the data lines D1 to Dm.

The switching unit SW3 constituting the charge share voltage supply unit 186 includes a terminal 7 connected to a power supply circuit disposed outside the data integrated circuit, and a terminal 8 commonly connected to the data line and the terminal 6. The switching unit SW3 is switched according to the charge share control signal Ccs to supply the charge share voltage to the data line. That is, the switching unit SW3 buffers the charge share voltage during the high logic period of the charge share control signal Ccs generated from the Ccs generator 166, that is, the high logic period of the odd-numbered source output signal SOE. 187) to the data line.

As described above, the liquid crystal display according to the second exemplary embodiment of the present invention supplies a charge share voltage during the high logic period of the odd-numbered source output signal SOE, as shown in FIG. During the high logic period of the signal SOE, a modulated data voltage having a polarity opposite to the output data voltage is applied. Accordingly, the rising time of the positive voltage that changes from the positive voltage increases, and the polling time of the negative voltage that changes from the negative voltage increases, thereby reducing the charge amount Qe charged in the liquid crystal cells of the even-numbered horizontal line. do. However, even if the amount of charge Qe charged to the liquid crystal cells of the even-th horizontal line is reduced to some extent, the amount of charge Qe is not sufficiently reduced in a region having a large RC delay (a region far from the data integrated circuit) to compensate for this. The amount of charge Qo charged in the liquid crystal cells of the odd horizontal line is increased. That is, the charging amount charged in the liquid crystal cells of the odd horizontal line is reduced by reducing the rising time of the positive voltage which changes from the negative voltage through the supply of the charge share voltage and reducing the polling time of the negative voltage which changes from the positive voltage. Let Qo increase. As a result, the liquid crystal display and the driving method according to the second embodiment of the present invention are charged in the liquid crystal cells of the odd horizontal line by applying a charge share voltage in a region having a large RC delay (a region far from the data integrated circuit). A liquid crystal display driven in a 2-dot inversion manner by increasing the charge amount Qo and thereby balancing the charge amount Qe charged in the liquid crystal cells of the even-th horizontal line which is not sufficiently reduced due to the RC delay. The display quality of the device can be improved.

As described above, the liquid crystal display device and the driving method thereof according to the first embodiment of the present invention insert a positive polarity voltage by inserting modulation data voltages of opposite polarities between analog data voltages of the same polarity that are continuously generated. It is possible to reduce the charging amount Qe charged in the liquid crystal cells of the even-th horizontal line by increasing the rising time of the positive voltage which changes from and increasing the polling time of the negative voltage which changes from the negative voltage. Accordingly, the liquid crystal display device and the driving method thereof according to the first embodiment of the present invention are driven by the two-dot inversion method by the same amount of charge to be filled in the liquid crystal cells of the odd and even horizontal line The display quality of the device can be improved.

In addition, the liquid crystal display device and the driving method thereof according to the second embodiment of the present invention insert a modulation data voltage of opposite polarity between analog data voltages of the same polarity which are generated continuously, and change the positive data from the positive polarity voltage. By increasing the rising time of the polarity voltage and increasing the polling time of the negative voltage which varies from the negative voltage, the amount of charge (Qe) charged to the liquid crystal cells of the even horizontal line is reduced, and analog data of different polarities generated continuously The amount of charge charged in the liquid crystal cells of the odd horizontal line by inserting a charge share voltage between the voltages to reduce the polling (or rising) time of the negative (or positive) voltage that changes from the positive (or negative) voltage. Increase (Qo). Accordingly, the liquid crystal display device and the driving method thereof according to the second embodiment of the present invention have an even horizontal line even if the amount of charges charged in the liquid crystal cells of the even horizontal line is increased due to the RC delay caused by the increase in the line resistance. The amount of charges charged in the liquid crystal cells is increased to balance the two, thereby improving the display quality of the liquid crystal display device driven by the 2-dot inversion method.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, although the embodiment of the present invention has been described based on the two dot inversion method, N (where N is a positive integer of 2 or more) may also be applied to the dot inversion method. In addition, embodiments disclosed in the detailed description of the invention may be used in combination. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (43)

A liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; Converts the digital video data into an analog data voltage to be displayed on the liquid crystal panel, and inverts the polarity of the analog data voltage in units of N (N is a positive integer of 2 or more) horizontal period, and analog data voltages of the same polarity generated continuously A data driver for supplying the analog data voltages and the modulated data voltages to the data lines by inserting modulation data voltages having opposite polarities between them; A controller for supplying the digital video data to the data driver and supplying control signals to the data driver to control the polarity of the analog data voltage and the generation of the modulated data voltage; A gate driver configured to supply scan signals synchronized with the analog data voltages to the gate lines; The control signal may include a first control signal indicating a generation period of the modulated data voltage; A second control signal indicating a polarity inversion period of the analog data voltage; The controller generates a third control signal for controlling digital data shifting of the data driver and an output of the analog data voltages, and a fourth control signal for controlling the gate driver. The controller may include a timing controller configured to supply the digital video data to the data driver and to control operation timing of the data driver and the gate driver using the second to fourth control signals; And a data modulation signal generator for generating the first control signal. delete delete delete The method of claim 1, And the data modulation signal generator is embedded in the timing controller. The method of claim 1, The third control signal, And a source output signal indicative of an output period of the analog data voltage. The method of claim 6, The first control signal is, A pulse swinging between the first logic value and the second logic value; The first logical value in the even-numbered first logic section of the source output signal, and the second logical value in the odd-numbered first logic section and the second logic section other than that; Device. The method of claim 7, wherein The data driver may include: And inverting the polarity of the analog data voltage in units of two horizontal periods in response to the second control signal. 9. The method of claim 8, The data driver may include: In response to a first logic value of the first control signal, inserting a modulation data voltage having an opposite polarity between the successively generated analog data voltages of the same polarity and the analog data voltages and the modulated data And a modulation voltage supply unit for supplying a voltage to the data lines. The method of claim 9, The modulation voltage supply unit, A first multiplex for selectively outputting a positive analog data voltage and a negative analog data voltage in response to the second control signal; A second multiplex for selectively outputting a positive modulation data voltage and a negative modulation data voltage in response to the second control signal in which the logic value is inverted; And a switch switched according to a logic value of the first control signal to supply either the first multiplex output or the second multiplex output to the data line. 11. The method of claim 10, The switch, Connect the first multiplex to the data line in response to a second logic value of the first control signal, and connect the second multiplex to the data line in response to a first logic value of the first control signal. And a liquid crystal display device. A liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; Converts the digital video data into an analog data voltage to be displayed on the liquid crystal panel, and inverts the polarity of the analog data voltage in units of N (N is a positive integer of 2 or more) horizontal period, and analog data voltages of the same polarity generated continuously Inserting a modulation data voltage having a polarity opposite to that between them, and inserting a charge share voltage between analog data voltages of different polarities that are generated in succession, so that the analog data voltages, the modulation data voltage, and the charge share voltage A data driver for supplying the data lines to the data lines; A controller for supplying the digital video data to the data driver, controlling the polarity of the analog data voltage, and supplying control signals to the data driver to control generation of the modulated data voltage and supply of the charge share voltage. Liquid crystal display characterized in that. 13. The method of claim 12, The charge share voltage is, And an intermediate voltage between the positively generated analog data voltage and the negatively shaped analog data voltage. 14. The method of claim 13, Wherein the control signal comprises: A 1-1 control signal indicating a generation period of the modulated data voltage; A 1-2 control signal indicating a supply period of the charge share voltage; And a second control signal for indicating a polarity inversion period of the analog data voltage. 15. The method of claim 14, A gate driver for supplying scan signals synchronized with the analog data voltages to the gate lines; And the controller is further configured to generate a third control signal for controlling digital data shifting of the data driver and an output of the analog data voltages, and a fourth control signal for controlling the gate driver. 16. The method of claim 15, The control unit, A timing controller configured to supply the digital video data to the data driver and to control an operation timing of the data driver and the gate driver using the second to fourth control signals; A data modulation signal generator for generating the first-first control signal; And a charge share control signal generator for generating the 1-2 control signal. 17. The method of claim 16, And the data modulation signal generator and the charge share control signal generator are embedded in the timing controller. 17. The method of claim 16, The third control signal, And a source output signal indicative of an output period of the analog data voltage. The method of claim 18, The 1-1 control signal is, A pulse swinging between the first logic value and the second logic value; The first logical value in the even-numbered first logic section of the source output signal, and the second logical value in the odd-numbered first logic section and the second logic section other than that; Device. The method of claim 18, The 1-2 control signal is, A pulse swinging between the first logic value and the second logic value; And a second logic value generated in the first logic section of the source output signal in the odd-numbered first logic section, and generated in the second logic value during the even-numbered first logic section and the other second logic section. Device. 21. The method according to claim 19 or 20, The data driver may include: And inverting the polarity of the analog data voltage in units of two horizontal periods in response to the second control signal. 22. The method of claim 21, The data driver may include: In response to the first logic value of the first-first control signal, inserting a modulation data voltage having an opposite polarity between the continuously generated analog data voltages of the same polarity and A modulation voltage supply unit supplying a modulation data voltage to the data lines; In response to the first logic value of the 1-2 control signal, a charge share voltage is inserted between the continuously generated analog data voltages having different polarities, and the analog data voltages and the charge share voltage are converted into the charge share voltage. And a charge share voltage supply unit for supplying the data lines. 23. The method of claim 22, The modulation voltage supply unit, A first multiplex for selectively outputting a positive analog data voltage and a negative analog data voltage in response to the second control signal; A second multiplex for selectively outputting a positive modulation data voltage and a negative modulation data voltage in response to the second control signal in which the logic value is inverted; And a switch switched according to a logic value of the first-first control signal to supply either the first multiplex output or the second multiplex output to the data line. . 24. The method of claim 23, The switch, Connect the first multiplex to the data line in response to a second logic value of the first-1 control signal, and connect the second multiplex to the first logic value in response to a first logic value of the first-1 control signal. And a data line. 23. The method of claim 22, The charge share voltage supply unit, A power supply unit for generating the charge share voltage; And a switch for controlling supply of the generated charge share voltage to the data line by switching according to a logic value of the 1-2 control signal. 26. The method of claim 25, The switch, Connecting the power supply unit to the data line in response to the first logic value of the 1-2 control signal, and disconnecting the power supply unit and the data line in response to the second logic value of the 1-2 control signal. And a liquid crystal display device. Converts digital video data into analog data voltage to be displayed on the liquid crystal panel, controls the polarity inversion period of the analog data voltage in units of N (N is a positive integer of 2 or more) horizontal period, and analog data of the same polarity generated continuously A first step of generating control signals to control a modulated data voltage of opposite polarity inserted between the voltages; Supplying the analog data voltages and the modulated data voltages generated in response to the control signals to a data line; The control signal may include a first control signal indicating a generation period of the modulated data voltage; And a second control signal indicative of a polarity inversion period of the analog data voltage, and supplying a scan signal synchronized with the analog data voltages to gate lines; The control signal includes a third control signal for controlling the digital data shifting and the output of the analog data voltages, and a fourth control signal for controlling the output of the scan signal. The third control signal includes a source output signal indicating an output period of the analog data voltage, The first control signal is generated as a pulse swinging between a first logic value and a second logic value; The first logical value in the even-numbered first logic section of the source output signal, and the second logical value in the odd-numbered first logic section and the second logic section other than that; Method of driving the device. delete delete delete delete 28. The method of claim 27, The second step, And inverting the polarity of the analog data voltage in units of two horizontal periods in response to the second control signal. 33. The method of claim 32, The second step, A step 2-1 of selectively outputting a positive analog data voltage and a negative analog data voltage in response to the second control signal; A second step of selectively outputting a positive modulation data voltage and a negative modulation data voltage in response to the second control signal in which the logic value is inverted; And a step 2-3 of selecting one of the step 2-1 output or the step 2-2 output according to a logic value of the first control signal to supply the data line to the data line. Method of driving display device. Converts digital video data into analog data voltage to be displayed on the liquid crystal panel, controls the polarity inversion period of the analog data voltage in units of N (N is a positive integer of 2 or more) horizontal period, and analog data of the same polarity generated continuously A first step of generating control signals for controlling a modulated data voltage of opposite polarity inserted between the voltages, or for controlling a charge share voltage inserted between successively generated analog data voltages of different polarities; Wow; And supplying the analog data voltages, the modulated data voltage, and the charge share voltage generated in response to the control signals to a data line. 35. The method of claim 34, The charge share voltage is, A method of driving a liquid crystal display device, characterized in that it is an intermediate voltage between a positively generated analog data voltage and a negatively analog data voltage. 36. The method of claim 35, Wherein the control signal comprises: A 1-1 control signal indicating a generation period of the modulated data voltage; A 1-2 control signal indicating a supply period of the charge share voltage; And a second control signal for indicating a polarity inversion period of the analog data voltage. 37. The method of claim 36, Supplying a scan signal synchronized with the analog data voltages to gate lines; The control signal may further include a third control signal for controlling the digital data shifting and the output of the analog data voltages, and a fourth control signal for controlling the output of the scan signal. Driving method. 39. The method of claim 37, The third control signal, And a source output signal indicative of an output period of the data voltage. 39. The method of claim 38, The 1-1 control signal is, A pulse swinging between the first logic value and the second logic value; The first logical value in the even-numbered first logic section of the source output signal, and the second logical value in the odd-numbered first logic section and the second logic section other than that; Method of driving the device. 39. The method of claim 38, The 1-2 control signal is, A pulse swinging between the first logic value and the second logic value; And a second logic value generated in the first logic section of the source output signal in the odd-numbered first logic section, and generated in the second logic value during the even-numbered first logic section and the other second logic section. Method of driving the device. 41. The method of claim 39 or 40 wherein The second step, And inverting the polarity of the analog data voltage in units of two horizontal periods in response to the second control signal. 42. The method of claim 41, The second step, A step 2-1 of selectively outputting a positive analog data voltage and a negative analog data voltage in response to the second control signal; A second step of selectively outputting a positive modulation data voltage and a negative modulation data voltage in response to the second control signal in which the logic value is inverted; And a step 2-3 of selecting one of the step 2-1 output or the step 2-2 output according to a logic value of the first control signal to supply the data line to the data line. Method of driving display device. 43. The method of claim 42, The second step, Generating the charge share voltage and supplying the charge share voltage to the data line intermittently according to a logic value of the 1-2 control signal.

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