KR101415686B1 - Source driving circuit and driving method thereof - Google Patents

Abstract

The present invention relates to a source driver circuit and a driving method thereof, and more particularly, to a source driver circuit and a driving method thereof for a display device, including a shift register unit receiving a start pulse signal and a clock signal from an external circuit unit and outputting a new start pulse signal; A first data register unit and a second data register unit for alternately receiving, storing, and outputting video data input from the external circuit unit by one horizontal line; A latch unit for receiving, storing, and outputting the video data output from the first data register unit and the second data register unit; A digital-to-analog converter converting the video data output from the latch unit into an analog voltage signal and outputting the analog voltage signal; And an output buffer unit for improving a current driving force of the analog voltage signal output from the digital-analog converter and outputting the analog voltage signal to the liquid crystal panel. In addition, the present invention provides a source driver circuit for a liquid crystal display, The charging deviation that is classified into the strong charging condition and the weak charging condition is reduced, and the quality of the display image quality is improved.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a source driving circuit and a driving method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a source driver circuit of a display device and a driving method thereof, and more particularly, to a liquid crystal display device capable of improving liquid crystal charging characteristics in a specific driving mode to enhance image quality and a driving method thereof.

Among display devices, liquid crystal display devices have advantages of small size, thinness and low power consumption and are used in notebook computers, office automation devices, audio / video devices, and the like. In particular, an active matrix type liquid crystal display device using a thin film transistor (hereinafter referred to as "TFT") as a switching element is suitable for displaying dynamic images.

1 is a block diagram showing a basic configuration of a general liquid crystal display device, which is largely divided into a liquid crystal panel 2 and an LCM driving circuit portion 26. [

The interface 10 receives data (RGB Data) and a control signal (input clock, horizontal synchronizing signal, vertical synchronizing signal, and data signal) input from the driving system such as a personal computer to the LCM driving circuit 26 And supplies it to the timing controller 12. LVDS (Low Voltage Differential Signal) interface and TTL interface are mainly used for data and control signal transmission from the drive system. These interface functions may be collected and used together with the timing controller 12 as a single chip.

2, the liquid crystal panel 2 includes a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn intersecting each other on a substrate using a glass to form a plurality of pixel regions, A thin film transistor (TFT) and a liquid crystal (LC) are formed in the region to display a screen.

The timing controller 12 drives a gate driver 20 composed of a plurality of gate driver ICs and a source driver 18 composed of a plurality of drive ICs by using a control signal inputted through the interface 10 Lt; / RTI > And also transmits the data input through the interface 10 to the source driver 18. [

The reference voltage generator 16 generates reference voltages of a digital to analog converter (DAC) used in the source driver 18. The reference voltages are set by the manufacturer based on the transmittance-voltage characteristics of the panel.

The source driver 18 selects the reference voltages of the input data in response to the control signals input from the timing controller 12 and supplies the selected reference voltage to the liquid crystal panel 2 to control the rotation angle of the liquid crystal molecules.

The gate driver 20 performs on / off control of thin film transistors (TFTs) arranged on the liquid crystal panel 2 in response to control signals input from the timing controller 12, The thin film transistors TFT on the liquid crystal panel 2 are sequentially driven for one line by sequentially enabling the gate lines GL1 to GLn on the liquid crystal panel 2 in synchronization with one horizontal synchronization time, So that the analog video signals supplied from the TFTs are applied to the pixels connected to the TFTs.

The power supply voltage generating unit 14 supplies the operating power of each of the components and generates and supplies the common electrode voltage of the liquid crystal panel 2.

And a back-light unit (not shown), which includes at least one lamp to supply light to the liquid crystal panel 2.

The configuration and operation of the source driver 18 in the above configuration will be described in detail with reference to the configuration diagram of FIG.

The source driver 18 generally includes a shift register section 18a, a data register section 18b, a latch section 18c, a digital-analog conversion section (DAC) 18d, an output buffer section 18e ).

The shift register 18a receives the start pulse signal STHR, the clock signal CLK and the source start pulse SSP from the timing controller 12 and generates a new start pulse signal STHR) to the next shift register sequentially. At this time, the start pulse signal STHR is a signal synchronized with the video data RGB Data.

The data register unit 18b is a data latch memory for temporarily storing video data (RGB data) input from the timing controller 12, and is connected to the output signal of each stage of the shift register 18a (RGB Data) transmitted in a time division manner and stores the sampled video data. At this time, the video data (RGB Data) stored in the data latch memory is, for example, a digital video signal of 6 bits each of R, G, and B.

The latch unit 18c receives and stores the video data sampled by the data register unit 18b. When the video data of one horizontal period is input to the latch unit 18c, the latch unit 18c receives the video data from the timing controller 12 (Output) by the signal SOE. Therefore, the latch unit 18c holds video data of one horizontal period inputted until the new video data (RGB Data) is input from the data register unit 18b, and the latch unit 18c holds the video data The video data of one new horizontal period is input to the data register unit 18b.

The video data output from the latch unit 18c is input to a digital-analog converter (DAC) 18d and the digital-analog converter (DAC) 18d inputs video data generated by the reference voltage generator 16 And converts the analog voltage to be output to the liquid crystal panel 2 using a plurality of reference voltages VGMAs.

The analog video data output from the digital-analog converter (DAC) 18d improves the current driving force in the output buffer unit 18e, and at the same time, the polarity control signal POL controls the pixel- And outputs it. At this time, the data polarity inversion by the polarity control signal POL may be performed by the latch unit 18c, and the output buffer unit 18e is usually configured by using an operational amplifier (OP-AMP).

4 is a signal timing chart for explaining the operation of the source driver 18 having the above configuration. The source start pulse (SSP) and the source output enable (SOE) shown in FIG. ) Signal is selectively shown.

The source start pulse SSP is generated in units of one horizontal period and indicates the start point or the first pixel of the data in the application of one horizontal data. The source start pulse SSP causes the data register unit 18b ), And then a new source start pulse (SSP) is inputted again, the existing video data is deleted and new video data is stored.

The SOE (Source Output Enable) is generated in units of one horizontal period, latches video data input to the latch unit 18c at a rising edge at the same time, and latches the latched And instructs the liquid crystal panel 2 to output the video data.

However, in the operation of the liquid crystal panel of the structure in which the vertical two-dot drive or one data line is shared by two pixels adjacent to the left and right, for example, the above operation of the source driver 18, There is a problem that horizontal stripes are generated due to the luminance variation between the horizontal pixel rows.

Referring to the data input diagram of FIG. 5, in the case of vertical two-dot driving, positive polarity (+) -> positive polarity (-) -> negative polarity (- The data is sequentially input in the order of negative polarity (-) -> positive polarity (+) -> positive polarity (+).

However, since the data of the polarities opposite to the data input to the data line at the previous timing are inputted, the data of the first, third, and fifth data are inputted to the liquid crystal pixel completely And a 'drug charging condition' that can not be charged.

On the contrary, in the case of data input of 2, 4, and 6, since the data of the same polarity is inputted at the previous timing, the charge level is relatively decreased due to the pre-charging effect, Smooth 'strong charging condition'.

If a gray pattern or the like is produced under such a driving condition, there arises a problem that the horizontal stripe phenomenon is recognized by the arrangement of the horizontal pixel column of the weak charging condition and the horizontal pixel column of the strong charging condition.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to improve the quality of the display quality of a liquid crystal panel by reducing the charging deviation of video data charged in the same line.

According to an aspect of the present invention, there is provided a semiconductor memory device including: a shift register unit receiving a start pulse signal and a clock signal from an external circuit unit and outputting a start pulse signal; A first data register unit and a second data register unit for alternately receiving, storing, and outputting video data input from the external circuit unit by one horizontal line; A latch unit for receiving, storing, and outputting the video data output from the first data register unit and the second data register unit; A digital-to-analog converter converting the video data output from the latch unit into an analog voltage signal and outputting the analog voltage signal; And an output buffer unit for improving the current driving force of the analog voltage signal output from the digital-analog converter and outputting the analog voltage signal to the liquid crystal panel.

And a data register selection circuit unit for designating a data register unit in which the video data is to be stored, from among the first data register unit and the second data register unit.

The first data register unit and the second data register unit may receive video data of odd-numbered horizontal lines and even-numbered horizontal lines, respectively, or the first data register unit and the second data register unit may receive video data of even- And the video data of the horizontal line is received.

The first data register unit and the second data register unit alternately output video data with a period of a first time and a second time, respectively.

And the first time and the second time are different from each other.

And the external circuit portion is a timing controller.

According to another aspect of the present invention, Outputting video data of odd-numbered horizontal lines of the video data at a first time interval; Outputting video data of even-numbered horizontal lines of the video data at a second time interval; Receiving and latching video data of each horizontal line; Converting the latched video data into an analog voltage signal; And outputting the analog voltage signal to the liquid crystal panel.

In the driving method, the first time and the second time are different from each other.

In the driving method, video data of the odd-numbered horizontal lines and video data of the even-numbered horizontal lines are alternately output.

According to the present invention, there is an advantage of reducing a charging deviation divided into a strong charging condition and a weak charging condition when the video data is charged by using the same line. In particular, vertical two-dot driving or one data line There is an advantage that the quality of the display quality of the liquid crystal panel is improved in the driving of the liquid crystal panel having a structure shared by two pixels.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

6 is a configuration diagram showing the configuration of a source driver circuit (hereinafter, referred to as a 'source driver') 100 of a liquid crystal display according to the present invention. The shift register unit 101, the first data register unit 102a And a second data register unit 102b, a latch unit 103, a digital-analog converter (DAC) 104, and an output buffer unit 105. [

The shift register unit 101 receives a start pulse signal STHR, a clock signal CLK and a source start pulse SSP from a timing controller (not shown). The shift register unit 101 generates a start pulse And sequentially shifts (outputs) the signal STHR to the next stage shift register. At this time, the start pulse signal STHR is a signal synchronized with the video data RGB Data.

The first data register unit 102a and the second data register unit 102b are both data latch memories for temporarily storing video data (RGB data) input from the timing controller, (RGB Data) transmitted in time division by the output signals of the respective stages of the unit 101 and stores the sampled data. At this time, the video data (RGB Data) stored in the data latch memory is, for example, a digital video signal of 6 bits each of R, G, and B.

The first data register unit 102a and the second data register unit 102b alternately receive, store, and output video data input from the timing controller for each horizontal line, and output the video data. For example, Video data of the (2n-1, n is a natural number) horizontal line is stored in the data register unit 102a, and (2n, n is a natural number) video data is stored in the second data register 102b In this case, the output of the second data register 102b is generated after the output of the video data first occurs in the first data register unit 102a. Of course, if the video data of the next horizontal line is input to both the first data register unit 102a and the second data register unit 102b, the previous video data is deleted.

7, the data register selection circuit portion 106 for controlling the input of video data to the first data register portion 102a or the second data register portion 102b is preferably constituted so that the video data 1 data register unit 102a and the second data register unit 102b alternately. Of course, the data register selection circuit portion 106 may be configured in the source driver 100 or may be configured in an external circuit portion such as a timing controller.

The first data register unit 102a and the second data register unit 102b receive the video data of the odd (or even) and the even (or odd) horizontal lines, respectively, At this time, the video data output timings of the first data register unit 102a and the second data register unit 102b are different.

That is, the first data register unit 102a outputs video data at an interval of a first time, and the second data register unit 102b outputs video data at an interval of a second time different from the first time This output time can be performed through adjustment of the SOE (Source Output Enable) signal and the scan signal output from the gate driver. The data input time of the strong charge condition is partially divided into the data input time of the approximate charge condition And thus the data charging time in the approximate charging condition can be further secured without changing the total driving time by the allocation of the driving time, and will be described in detail in the signal timing chart of FIG. 8 to be described later.

The latch unit 103 receives and stores video data to be alternately output in the first data register unit 102a and the second data register unit 102b and outputs video data of one horizontal line to the latch unit 103), the signal is down-latched (output) by the SOE signal input from the timing controller. The latch unit 103 holds the input video data of one horizontal line until the new video data RGB data is input from the first data register 102a or the second data register unit 102b and a new one horizontal line of video data is input to the first data register unit 102a or the second data register unit 102b during the data holding time.

At this time, the timing of outputting the video data input from the first data register 102a and the second data register unit 102b is adjusted asymmetrically by adjusting the timing of the rising edge of the SOE signal in the latch unit 103 It is possible to assign the mutual video data charging time between the strong charging condition and the both charging conditions in the liquid crystal panel.

The video data output from the latch unit 103 is input to a digital-to-analog converter (DAC) 104. The digital-to-analog converter (DAC) 104 is generated by a reference voltage generator And converts the analog voltage to be outputted to the liquid crystal panel using the plurality of reference voltages VGMAs.

The analog video data output from the digital-to-analog converter (DAC) 104 is supplied to the output buffer unit 105 so as to improve the current driving force and, at the same time, And outputs it. At this time, the data polarity inversion by the polarity control signal POL is also performed by the latch unit 103, and the output buffer unit 105 is usually configured using an operational amplifier (OP-AMP).

FIG. 8 is a signal timing chart for explaining a method of driving a source driver of a liquid crystal display according to the present invention, in which vertical two-dot driving in which video data of the same polarity is input twice to one data line, Fig.

It can be seen from the signal timing diagram that the charging time of the video data of (1), (3), (5), and (7) is longer than that of the video data of (2), (4), (6) and (8) It can be seen that the scan signals G1 to G8 applied to the thin film transistor TFT for controlling the data input are also given in proportion to the ON time.

This driving method is a method in which a portion of the charging time of the video data of (2), (4), (6), and (8) corresponding to the 'strong charging condition' So that the video data having the " weakly charged condition " is sufficiently charged to the pixels of the liquid crystal panel through the time of one horizontal period (1H) or longer, It is possible to improve the horizontal stripe phenomenon seen due to the car. The sum of the charging time t2 of the 'strong charging condition' and the charging time t1 of the 'weak charging condition' corresponds to two horizontal periods 2H.

In order to sufficiently secure the charging time of the video data in the 'weak charging condition' as described above, the driving method (100 in FIG. 6) of the source driver (100 in FIG. 6) Therefore, in the present invention, the configuration of the source driver as shown in FIG. 6 to FIG. 7 described above is required.

That is, in performing screen display on the liquid crystal panel, the total driving time is not changed, and the video data of the strong charging condition is divided into (t2 And the video data of the weak charging condition is outputted to the liquid crystal panel for a time longer than the time t2. The charging time t1 of the charging condition is one horizontal period (1H) is erased due to the input of the video data of the next strong charging condition before the video data of the weak charging condition is completely charged by the source start pulse SSP applied by the timing controller To this end, as shown in Figs. 6 to 7, the video data of the strong charging condition and the video data of the weak charging condition are different from each other (102a, 102b), thereby preventing data erasure by the source start pulse (SSP).

Of course, although not shown, in the timing controller for generating a control signal such as a source output enable (SOE), in the timing controller in which the first data register unit 102a and the second data register unit 102b in FIG. 6 to FIG. A source output enable (SOE) signal in which a rising edge and a polling edge are generated in accordance with the time intervals of (t1) and (t2) (100).

1 is a block diagram showing a basic configuration of a general liquid crystal display device

Fig. 2 is a view schematically showing the configuration of the liquid crystal panel in the configuration of Fig. 1

3 is a diagram for explaining the configuration of the source driver 18 in the configuration of FIG. 1

4 is a timing chart for explaining the operation of the source driver 18 having the above-

FIG. 5 is a data input diagram for explaining a horizontal stripe phenomenon occurring in a specific pattern display driving of a liquid crystal panel according to the related art.

6 is a diagram showing the configuration of the source driver circuit 100 of the liquid crystal display device according to the present invention

7 is an application configuration diagram showing the application of the configuration of the source driver circuit 100 of the liquid crystal display device according to the present invention

8 is a signal timing diagram for explaining a method of driving a source driver of a liquid crystal display according to the present invention

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

100: Source driver 101: Shift register unit

102a and 102b: first and second data register units

103: latch unit 104: digital-analog conversion unit

105: output buffer section 106: data register selection circuit section

Claims (9)

A shift register unit receiving a start pulse signal, a clock signal, and a source start pulse from the external circuit unit and outputting a new start pulse signal; A first data register unit and a second data register unit for alternately receiving, storing, and outputting video data input from the external circuit unit in units of one horizontal line in accordance with the source start pulse input in one horizontal period unit; A latch unit for receiving, storing, and outputting the video data output from the first data register unit and the second data register unit; A digital-to-analog converter converting the video data output from the latch unit into an analog voltage signal and outputting the analog voltage signal; An output buffer unit for improving the current driving force of the analog voltage signal outputted from the digital- The source driver circuit of the liquid crystal display device The method according to claim 1, And a data register selection circuit portion for designating a data register portion in which the video data is to be stored among the first data register portion and the second data register portion, The source driver circuit of the liquid crystal display device further includes: The method according to claim 1, The first data register unit and the second data register unit may receive video data of odd-numbered horizontal lines and even-numbered horizontal lines, respectively, or the first data register unit and the second data register unit may receive video data of even- And the video data of the horizontal line is inputted to the source driver circuit of the liquid crystal display device The method according to claim 1, Wherein the first data register unit and the second data register unit alternately output video data with a period of a first time and a second time, respectively, The method according to claim 4, Wherein the first time and the second time are different from each other. The method according to claim 1, And the external circuit portion is a timing controller. Receiving video data alternately by one horizontal line in the first and second data register units in accordance with a source start pulse input in one horizontal period unit; Outputting video data of odd-numbered horizontal lines of the video data at a first time interval in the first data register unit; Outputting video data of even-numbered horizontal lines of the video data at a second time interval in the second data register unit; Receiving and latching video data of each horizontal line; Converting the latched video data into an analog voltage signal; Outputting the analog voltage signal to the liquid crystal panel A driving method of a source driving circuit of a liquid crystal display device The method of claim 7, Wherein the first time and the second time are different from each other. The method of claim 7, And the video data of the odd-numbered horizontal lines and the video data of the even-numbered horizontal lines are alternately outputted.

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