KR20090041181A - Source driving circuit and driving method thereof - Google Patents

Abstract

A source driving circuit and a driving method of a liquid crystal display are provided to improve the dignity of the liquid crystal panel display definition by reducing the charging deviation of video data. A shift transistor part(101) receives the start pulse signal and the clock signal from the outside circuit unit, and outputs the new start pulse signal. The first data register part(102a) and the second data register part(102b) stores the video data inputted from the outside circuit unit, and outputs. A latch unit(103) receives the video data outputted in the first data register part and the second data register part, and stores and outputs. A digital-to-analog conversion section(104) converts the video data from the latch unit into the analog voltage signal and outputs. An output buffer part(105) improves the current driving force of the analog voltage signal and outputs.

Description

Source driving circuit and driving method thereof of liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a source driving circuit of a display device and a driving method thereof. More particularly, the present invention relates to a liquid crystal display device and a driving method thereof capable of improving a liquid crystal charging characteristic in a specific driving mode to improve image quality.

Among the display devices, in particular, liquid crystal displays have advantages of small size, thinness, and low power consumption, and are used as notebook computers, office automation devices, and audio / video devices. In particular, an active matrix liquid crystal display device using a thin film transistor (hereinafter referred to as "TFT") as a switch element is suitable for displaying a dynamic image.

FIG. 1 is a block diagram showing a basic configuration of a general liquid crystal display device, and is largely divided into a liquid crystal panel 2 and an LCM driving circuit unit 26.

In each configuration, the interface 10 includes data (RGB Data) and control signals (input clock, horizontal synchronous signal, vertical synchronous signal, data input) input from the drive system such as a personal computer to the LCM drive circuit unit 26. Able signal, etc.) are input and supplied to the timing controller 12. Low voltage differential signal (LVDS) interface and TTL interface are mainly used for data and control signal transmission from the drive system. In addition, the interface function may be collected and used together with the timing controller 12 in a single chip.

As illustrated in FIG. 2, the liquid crystal panel 2 forms a plurality of pixel regions by crossing a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn on a glass substrate. In the region, a thin film transistor TFT and a liquid crystal LC are configured to display a screen.

The timing controller 12 drives a source driver 18 composed of a plurality of drive integrated circuits and a gate driver 20 composed of a plurality of gate driver integrated circuits using a control signal input through the interface 10. Generate a control signal for In addition, the data input through the interface 10 is transmitted to the source driver 18.

The reference voltage generator 16 generates reference voltages of a digital to analog converter (DAC) used in the source driver 18. Reference voltages are set by the producer based on the transmittance-voltage characteristics of the panel.

The source driver 18 selects reference voltages of the input data in response to control signals input from the timing controller 12, and supplies the selected reference voltage to the liquid crystal panel 2 to control the rotation angle of the liquid crystal molecules.

The gate driver 20 performs on / off control of thin film transistors TFTs arranged on the liquid crystal panel 2 in response to control signals input from the timing controller 12. Source driver 18 by sequentially driving thin film transistors TFT on the liquid crystal panel 2 by one line by sequentially enabling the gate lines GL1 to GLn by one horizontal synchronizing time. The analog image signals supplied from the plurality of pixels are applied to the pixels connected to the respective TFTs.

The power supply voltage generator 14 supplies operating power of each component and generates and supplies a common electrode voltage of the liquid crystal panel 2.

Although not shown, the apparatus further includes a backlight unit having one or more lamps to supply light to the liquid crystal panel 2.

Referring to the configuration and operation of the source driver 18 in the above configuration with reference to the configuration of Figure 3 as follows.

The source driver 18 generally includes a shift register section 18a, a data register section 18b, a latch section 18c, a digital-to-analog converter (DAC) 18d, and an output buffer section 18e, as shown. It is composed of

The shift register 18a receives a start pulse signal STHR, a clock signal CLK, and a source start pulse SSP from the timing controller 12. The shift register 18a receives a new start pulse signal in accordance with the clock signal CLK. STHR) is sequentially shifted (output) to the next shift register. At this time, the start pulse signal STHR is a signal synchronized with video data RGB data.

The data register unit 18b is a data latch memory that temporarily stores video data (RGB data) input from the timing controller 12. The data register unit 18b is used to output signals of each stage of the shift register 18a. The video data (RGB Data) transmitted by the time division by the sampling is stored and stored. At this time, the video data (RGB Data) stored in the data latch memory is, for example, a digital video signal of 6 bits each of R, G, and B.

The latch unit 18c receives and stores video data sampled by the data register unit 18b, and is input from the timing controller 12 when video data of one horizontal period is input to the latch unit 18c. The falling latch (output) is performed by the signal SOE. Accordingly, the latch unit 18c holds video data for one horizontal period received until new video data (RGB Data) is input from the data register unit 18b, and the data holding is performed. During the time, new data of one horizontal period is inputted to the data register 18b.

The video data output from the latch unit 18c is input to a digital-to-analog converter (DAC) 18d, and the digital-to-analog converter (DAC) 18d is generated by the reference voltage generator 16. A plurality of reference voltages VGMAs are used to convert the analog voltages to be output to the liquid crystal panel 2 and output the converted analog voltages.

The analog video data output from the digital-to-analog converter (DAC) 18d improves the current driving force at the output buffer unit 18e, and the data polarity for each pixel or line for each frame by the polarity control signal POL. Invert the output. In this case, the data polarity inversion by the polarity control signal POL may be performed by the latch unit 18c, and the output buffer unit 18e is usually configured using an operational amplifier OP-AMP.

FIG. 4 is a signal timing diagram illustrating the operation of the source driver 18 having the above-described configuration. The source start pulse (SSP) and the source output enable (SOE) shown in FIG. 3 are illustrated. ) Signal is selectively shown.

The source start pulse SSP is generated in units of one horizontal period. The source start pulse SSP indicates the start point of the data, that is, the first pixel in application of one horizontal data, and the data register unit 18b is provided by the source start pulse SSP. ), Video data is sequentially stored, and when a new source start pulse (SSP) is input again, existing video data is deleted and new video data is stored.

The source output enable (SOE) is generated in units of one horizontal period, and simultaneously latches video data input to the latch unit 18c at a rising edge, and also latches the falling edge at a falling edge. Instructs the video data to be outputted to the liquid crystal panel 2.

However, the above-described operation of the source driver 18 is, for example, a vertical two-dot drive or a liquid crystal panel in which two pixels adjacent to each other share one data line. There is a problem in that horizontal stripes are generated due to luminance deviation between horizontal pixels.

Referring to the data input diagram of FIG. 5, for example, in the case of vertical two-dot driving, positive polarity (+)-> positive polarity (+)-> negative polarity (-) as one data line as shown in FIG. 5. -> Negative polarity (-)-> positive polarity (+)-> positive polarity (+)

However, the data of ①, ③, and ⑤ in which data of polarity opposite to the data input to the data line at the previous timing is input is filled with liquid crystal pixels because the charging level is increased due to the data of the opposite polarity previously input. It will have a 'charge condition' that can not be charged.

On the contrary, in case of ②, ④, ⑥ data input, the same polarity data input is performed at the previous timing. Therefore, due to the pre-charging effect, the data level is relatively reduced and the data input to the liquid crystal pixel is reduced. It will have a smooth 'strong charging condition'.

When gray patterns are produced under such driving conditions, horizontal streaks may be recognized by vertically arranging the horizontal pixel rows of the weak charging condition and the horizontal pixel rows of the strong charging condition.

The present invention has been made to solve the above problems, and an object of the present invention is to improve the quality of liquid crystal panel display quality by reducing the charging deviation of video data charged in the same line.

In order to achieve the above object, the present invention includes a shift register unit for receiving a start pulse signal and a clock signal from an external circuit unit, and outputting a new start pulse signal; A first data register unit and a second data register unit configured to alternately receive and store video data input from the external circuit unit by one horizontal line; A latch unit for receiving and storing the video data output from the first and second data registers; A digital-analog converter for receiving the video data output from the latch unit and converting the video data into an analog voltage signal; A source driving circuit of a liquid crystal display device including an output buffer unit for improving a current driving force of an analog voltage signal output from the digital-analog converter and outputting the same to a liquid crystal panel is proposed.

And a data register selection circuit unit which designates a data register unit in which the video data is to be stored among the first data register unit and the second data register unit.

The first data register part and the second data register part receive video data of an odd-numbered horizontal line and an even-numbered horizontal line, respectively, or the first data register part and the second data register part respectively have an even-numbered horizontal line and an odd-numbered number. And receiving video data of a horizontal line.

The first data register unit and the second data register unit may output video data alternately with periods of a first time and a second time, respectively.

The first time and the second time may be different times.

The external circuit unit is a timing controller.

In addition, the present invention comprises the steps of receiving video data; Outputting video data of an odd-numbered horizontal line of the video data at first time intervals; Outputting video data of even-numbered horizontal lines of the video data at second time intervals; Receiving and latching video data of each horizontal line; Converting the latched video data into an analog voltage signal; A method of driving a source driving circuit of a liquid crystal display device comprising the step of outputting the analog voltage signal to a liquid crystal panel.

In the driving method, the first time and the second time are different times.

In the driving method, the video data of the odd horizontal lines and the video data of the even horizontal lines are alternately output.

According to the present invention, in charging video data using the same line, there is an advantage of reducing the charging deviation that is divided into a strong charging condition and a weak charging condition. In particular, a vertical two-dot drive or one data line adjacent to the left and right In driving a liquid crystal panel having a structure in which two pixels are shared, the quality of the liquid crystal panel display quality is improved.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram showing the configuration of a source driving circuit (hereinafter referred to as a "source driver") 100 of the liquid crystal display according to the present invention. The shift register unit 101 and the first data register unit 102a are shown in FIG. And a second data register section 102b, a latch section 103, a digital-to-analog converter (DAC) 104, and an output buffer section 105.

The shift register unit 101 receives a start pulse signal STHR, a clock signal CLK, and a source start pulse SSP from a timing controller (not shown). The shift register unit 101 receives a new start pulse in accordance with the clock signal CLK. The signal STHR is sequentially shifted (outputted) to the next shift register. At this time, the start pulse signal STHR is a signal synchronized with video data RGB data.

The first data register 102a and the second data register 102b are both data latch memories that temporarily store video data (RGB data) input from the timing controller. The video data (RGB Data) transmitted in time division by the output signal of each stage of the unit 101 is sampled and stored. At this time, the video data (RGB Data) stored in the data latch memory is, for example, a digital video signal of 6 bits each of R, G, and B.

In addition, the first data register unit 102a and the second data register unit 102b alternately receive and store video data inputted from the timing controller by one horizontal line, and then output the stored data, for example, the first data register unit 102a. Video data of (2n-1, n is natural number) th horizontal line is stored in the data register unit 102a, and (2n, n is natural number) second video data is stored in the second data register 102b. In this case, first output of video data occurs in the first data register 102a, and then output of the second data register 102b occurs. Of course, if video data of the next horizontal line is input to both the first data register 102a and the second data register 102b, the previous video data is deleted.

In this case, preferably, as shown in FIG. 7, the data data is selected by configuring the data register selection circuit section 106 for controlling the input of the video data to the first data register section 102a or the second data register section 102b. The first data register 102a and the second data register 102b are alternately stored. Of course, the data register selection circuit unit 106 may be configured in the source driver 100 or in an external circuit unit such as a timing controller.

As such, the first data register unit 102a and the second data register unit 102b each receive video data of an odd (or even) horizontal line and an even (or odd) horizontal line, and then output the sample data. In this case, the video data output timing of the first data register unit 102a and the second data register unit 102b is different.

That is, the first data register unit 102a outputs video data at intervals of a first time, and the second data register unit 102b outputs video data at intervals of a second time different from the first time. This output time can be performed by adjusting the SOE (Source Output Enable) signal and the scan signal output from the gate driver. The purpose of the allocation is to further secure the data charging time under the weak charging condition without changing the overall driving time, which will be described in detail later with reference to the signal timing diagram of FIG. 8.

The latch unit 103 receives and stores video data alternately outputted from the first data register unit 102a and the second data register unit 102b, and one horizontal line of video data is stored in the latch unit ( When inputted to 103, the latches (outputs) down by the SOE signal inputted from the timing controller. At this time, the latch unit 103 holds the video data corresponding to one horizontal line received until the new video data (RGB Data) is input from the first data register 102a or the second data register 102b. The first data register 102a or the second data register 102b is inputted with a new one horizontal line of video data during the data holding time.

In this case, the latch unit 103 asymmetrically adjusts the timing at which video data input from the first data register 102a and the second data register 102b is output by adjusting the timing of the rising edge of the SOE signal. By adjusting, it is possible to allocate mutual video data charging time between the strong charging condition and the positive charging condition in the liquid crystal panel.

The video data output from the latch unit 103 is input to a digital-to-analog converter (DAC) 104, and the digital-to-analog converter (DAC) 104 is generated by a reference voltage generator (not shown). By converting the analog voltage to be output to the liquid crystal panel by using the plurality of reference voltages (VGMAs).

The analog video data output from the digital-to-analog converter (DAC) 104 improves the current driving force in the output buffer unit 105 and the data polarity for each pixel or line for each frame by the polarity control signal POL. Invert the output. In this case, the data polarity inversion by the polarity control signal POL may be performed by the latch unit 103, and the output buffer unit 105 is generally configured using an operational amplifier OP-AMP.

8 is a signal timing diagram illustrating a method of driving a source driver of a liquid crystal display according to an exemplary embodiment of the present invention. An example of signal timing is shown.

From the signal timing, it can be seen that the charging time of the first, third, fifth, and seventh video data is set longer than that of the second, fourth, sixth, and eighth video data. It can be seen that the scan signals G1 to G8 applied to the thin film transistor TFT to control the data input are also given with an on time.

The driving method includes a portion of the charging time of the video data of ②, ④, ⑥, and ⑧ corresponding to the 'strong charging condition' of the first, ③, ⑤, ⑦th video data corresponding to the 'weak charging condition'. This is because the video data having the 'weak charging condition' is sufficiently charged in the pixels of the liquid crystal panel through a time period of more than one horizontal period (1H), thereby charging the video data in a gray pattern or the like. This can improve the horizontal streaks seen by the difference. At this time, the sum of the charging time t2 of the 'strong charging condition' and the charging time t1 of the 'weak charging condition' corresponds to two horizontal periods (2H).

In addition, in order to sufficiently secure the charging time of the video data under the 'weak charging condition' as described above, the driving method in the source driver (100 in FIG. 6) similarly to the on time of the scan signals G1 to G2. An appropriate change is required, and thus, in the present invention, the configuration of the source driver as shown in FIGS. 6 to 7 is required.

That is, in performing the screen display on the liquid crystal panel, the total driving time is not changed and the video data of the strong charging condition is allocated to the charging time distribution of the weak charging condition and the strong charging condition as shown in FIG. The video data of the weak charging condition should be output to the liquid crystal panel for a longer time (t1) than the (t2), and one horizontal period is equal to the charging time (t1) of the weak charging condition. In the case of time exceeding (1H), the weak start condition video data is erased by the next strong charge video data input before the weak charging condition video data is completely charged by the source start pulse (SSP) applied by the timing controller. For this purpose, as shown in FIGS. 6 to 7, the video data of the strong charging condition and the video data of the weak charging condition are different from each other (FIGS. 6 to 7). By storing the data at 102a and 102b of 7, the data deletion by the source start pulse SSP is prevented.

Although not shown, in the timing controller for generating a control signal such as a source output enable (SOE), the first data register 102a and the second data register 102b of FIGS. 6 to 7 are different from each other. In order to drive a video data charging time, the source driver is newly generated by generating a source output enable signal (SOE) signal having a rising edge and a falling edge generated at the time intervals of FIGS. It would be natural to apply it to (100).

1 is a block diagram showing the basic configuration of a general liquid crystal display device

FIG. 2 is a view schematically illustrating a configuration of a liquid crystal panel among the components of FIG. 1.

3 is a configuration diagram illustrating the configuration of the source driver 18 among the components of FIG. 1.

4 is a signal timing diagram for explaining the operation of the source driver 18 having the above configuration.

5 is a data input diagram illustrating a horizontal stripe phenomenon generated in a specific pattern display driving of a liquid crystal panel according to the related art.

6 is a block diagram showing the configuration of the source driving circuit 100 of the liquid crystal display according to the present invention.

7 is an application configuration diagram showing the application of the configuration of the source driving circuit 100 of the liquid crystal display according to the present invention;

8 is a signal timing diagram illustrating a method of driving a source driver of a liquid crystal display according to the present invention.

<Brief description of the main parts of the drawing>

100: source driver 101: shift register unit

102a and 102b: first and second data register units

103 latch portion 104 digital-to-analog conversion portion

105: output buffer section 106: data register selection circuit section

Claims (9)

A shift register unit receiving a start pulse signal and a clock signal from an external circuit unit and outputting a new start pulse signal; A first data register unit and a second data register unit configured to alternately receive and store video data input from the external circuit unit by one horizontal line; A latch unit for receiving and storing the video data output from the first and second data registers; A digital-analog converter for receiving the video data output from the latch unit and converting the video data into an analog voltage signal; Output buffer unit for improving the current driving force of the analog voltage signal output from the digital-analog converter to output to the liquid crystal panel Source driving circuit of the liquid crystal display comprising a The method according to claim 1, A data register selection circuit section for designating a data register section in which the video data is to be stored among the first data register section and the second data register section; Source driving circuit of the liquid crystal display further comprising The method according to claim 1, The first data register part and the second data register part receive video data of an odd-numbered horizontal line and an even-numbered horizontal line, respectively, or the first data register part and the second data register part respectively have an even-numbered horizontal line and an odd-numbered number. Source driving circuit of the liquid crystal display characterized in that the video data of the horizontal line is received The method according to claim 1, The first data register unit and the second data register unit alternately output video data with a period of first time and second time, respectively, characterized in that the source driving circuit of the liquid crystal display device The method according to claim 4, Wherein the first time and the second time are different time periods. The method according to claim 1, The external circuit unit is a source driving circuit of the liquid crystal display device, characterized in that the timing controller Receiving video data; Outputting video data of an odd-numbered horizontal line of the video data at first time intervals; Outputting video data of even-numbered horizontal lines of the video data at second time intervals; Receiving and latching video data of each horizontal line; Converting the latched video data into an analog voltage signal; Outputting the analog voltage signal to a liquid crystal panel Method of driving a source driving circuit of the liquid crystal display comprising a The method of claim 7, wherein The first time and the second time is a different time driving method of the source driving circuit of the liquid crystal display device The method of claim 7, wherein The video data of the odd horizontal lines and the video data of the even horizontal lines are alternately output.

Images