KR102135635B1 - Data driving integrated circuit and liquid crystal display device including the same - Google Patents

Abstract

The present invention provides a data driving integrated circuit to reduce power consumption by selectively changing a charge sharing mode according to a mode signal. The data driving integrated circuit according to the present invention sequentially inputs a plurality of input digital data signals. A digital processor which samples and outputs a plurality of sampled sampled data signals simultaneously; An analog processing unit converting each of the plurality of sampling data signals output from the digital processing unit into a positive data voltage or a negative data voltage according to a polarity control signal and outputting the data through a plurality of output channels; And performing the first charge-sharing mode according to the first mode signal to electrically connect two adjacent output channels to which data voltages of different polarities are output, or to operate according to the second mode signal different from the first mode signal. It may be configured to include a charge sharing unit that electrically connects two adjacent output channels to which data voltages of the same polarity are output by performing the 2 charge sharing mode.

Description

A data driving integrated circuit and a liquid crystal display device including the same{DATA DRIVING INTEGRATED CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of reducing power consumption.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal. The liquid crystal display device includes a liquid crystal panel for displaying an image, and a panel driver for driving the liquid crystal panel.

The liquid crystal panel includes a plurality of pixels formed in a pixel region defined by a plurality of gate lines and a plurality of data lines, and each of the plurality of pixels is connected to a thin film transistor and a thin film transistor connected to adjacent gate lines and data lines. It includes a pixel electrode and a pixel electrode, a common electrode facing or parallel to the pixel electrode, a liquid crystal capacitor formed by a liquid crystal layer between the pixel electrode and the common electrode, and a capacitor connected in parallel to the liquid crystal capacitor. The panel driver controls a gate driver supplying a scan signal to the plurality of gate lines, a data driver having a plurality of data driving integrated circuits supplying a data signal to the plurality of data lines, and each of the gate driver and the data driver It includes a timing control section.

In order to reduce deterioration of the liquid crystal, a general liquid crystal display device uses an inversion driving method in which polarities are inverted and driven.

The inversion driving method may be a frame inversion method, a line inversion method, a column inversion method, a horizontal 2 dot inversion method, a vertical 2 dot inversion method, or a dot in method depending on the polarity inverted unit. It can be classified by version method. Among these inversion driving methods, the column inversion method

A liquid crystal display using such an inversion driving method consumes a lot of power by a polarity transition of a data signal according to the inversion method.

Meanwhile, in Korean Patent Application Publication No. 10-2010-072632 (hereinafter referred to as "prior art document"), a charge share circuit for reducing power consumption by minimizing the voltage fluctuation between a plurality of data lines A liquid crystal display device comprising a.

The liquid crystal display device of the prior art document is consumed by applying or not applying a charge sharing method according to a comparison result of gradation of input data and reference gradation level data based on a charge sharing method for shorting all data lines. Reduce power.

However, the prior art document has the following problems.

First, there is a problem in that a reduction effect of power consumption is limited by applying or not applying a charge sharing method regardless of an inversion method.

Second, since a charge-sharing method that shortens all data lines is used, when a data signal of the same polarity is maintained, there is a problem in that power consumption is increased due to an increase in the polarity transition of the data signal due to unnecessary charge-sharing operation.

The present invention has been devised to solve the above-mentioned problems, and it is a technical problem to provide a data driving integrated circuit to selectively reduce a charge sharing mode according to a mode signal to reduce power consumption.

Another aspect of the present invention is to provide a data driving integrated circuit and a liquid crystal display device including the same to reduce power consumption by selectively changing a charge sharing mode based on an inversion method and/or input data. do.

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention are described below, or it will be clearly understood by those skilled in the art from the description and description.

The data driving integrated circuit according to the present invention for achieving the above-described technical problem is a digital processing unit for sequentially sampling a plurality of input digital data signals, and simultaneously outputting a plurality of sampled sampling data signals; An analog processing unit converting each of the plurality of sampling data signals output from the digital processing unit into a positive data voltage or a negative data voltage according to a polarity control signal and outputting the data through a plurality of output channels; And performing the first charge-sharing mode according to the first mode signal to electrically connect two adjacent output channels to which data voltages of different polarities are output, or to operate according to the second mode signal different from the first mode signal. It may be configured to include a charge sharing unit that electrically connects two adjacent output channels to which data voltages of the same polarity are output by performing the 2 charge sharing mode.

A liquid crystal display device according to the present invention for achieving the above technical problem is a display area having a plurality of pixels formed for each area defined by the intersection of a plurality of gate lines and a plurality of data lines and a non-display area excluding the display area A liquid crystal display panel comprising a first substrate comprising a, and a second substrate oppositely bonded to the first substrate; A gate driver driving the gate line; A data driving unit including the data driving integrated circuit for supplying a data voltage to each of the plurality of data lines; And a timing control unit controlling the driving of the gate driving unit and the data driving unit, arranging input image data into the plurality of digital data signals, supplying the data driving integrated circuit, and generating the first and second mode signals. It may be configured to include.

The timing control unit includes a mode signal generation unit generating the first and second mode signals based on the polarity control signal, wherein the mode signal generation units have opposite polarities of data voltages supplied to two pixels adjacent to each other vertically. In one case, when the first and second mode signals for operating the charge share unit in the first charge sharing mode are generated, and the polarities of the data voltages supplied to the two adjacent pixels are the same, the charge share First and second mode signals for operating the unit in the second charge sharing mode may be generated.

The timing control unit may include a data processor configured to generate a mode setting signal for analyzing the image data and setting the charge share unit to the first charge sharing mode or the second charge sharing mode; And a mode signal generator configured to generate the first and second mode signals according to the mode setting signal.

The charge share portion may be formed in a non-display area of the first substrate to be connected to the plurality of data lines.

According to the solving means of the said subject, this invention has the following effects.

First, the power consumption of the liquid crystal display may be reduced by selectively changing the charge sharing mode according to the mode signal based on the polarity control signal to reduce heat generation and power consumption of the data driving integrated circuit.

Second, it is possible to reduce the power consumption of the liquid crystal display by selectively changing the charge sharing mode according to the mode signal based on the analysis result of the input data to reduce heat generation and power consumption of the data driving integrated circuit.

1 is a block diagram illustrating a data driver according to an embodiment of the present invention.
FIG. 2 is a view for explaining an example of the analog processing unit shown in FIG. 1.
3 is a circuit diagram for explaining the charge share portion shown in FIG. 1.
4 and 5 are circuit diagrams for describing an operation state according to a charge sharing mode of the charge share unit illustrated in FIG. 3.
6 is a view for explaining a liquid crystal display device according to a first exemplary embodiment of the present invention.
FIG. 7 is a block diagram illustrating a first embodiment of the timing control unit illustrated in FIG. 6.
FIG. 8 is a block diagram illustrating a second embodiment of the timing controller illustrated in FIG. 6.
9 is a waveform diagram showing the swing of the data voltage according to the first and second mode signals and the charge sharing mode according to the present invention.
10 is a view for explaining a liquid crystal display device according to a second embodiment of the present invention,

The meaning of the terms described in this specification should be understood as follows.

It should be understood that a singular expression includes a plurality of expressions unless the context clearly defines otherwise, and the terms "first", "second", etc. are intended to distinguish one component from another component, The scope of rights should not be limited by these terms.

It should be understood that terms such as "include" or "have" do not preclude the presence or addition possibility of one or more other features or numbers, steps, actions, components, parts or combinations thereof.

Hereinafter, a preferred example of a data driving integrated circuit and a liquid crystal display device including the same according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a data driver according to an embodiment of the present invention.

Referring to FIG. 1, the data driving integrated circuit 100 according to an embodiment of the present invention includes a signal control unit 110, a gradation voltage generation unit 120, a digital processing unit 130, an analog processing unit 140, and a charge share. It comprises a portion 150.

The signal control unit 110 is a data control signal (DCS), a first mode signal (MS1), a second mode supplied from an external timing control unit (not shown) in charge of overall control for displaying an image on the liquid crystal display panel The signal MS2 and a plurality of digital data signals RGB are received, and the received signals are output to the corresponding digital processing unit 130, the analog processing unit 140, and the charge share unit 150. Here, the data control signal DCS may include a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, and a polarity control signal POL. In addition, the first and second mode signals MS1 and MS2 are signals for selectively changing different charge sharing modes to reduce power consumption and heat generation of the data driving integrated circuit 100. The signal controller 110 may be omitted according to a driving method of the data driving integrated circuit 100.

The gradation voltage generator 120 receives a plurality of positive polarity reference gamma voltages (PRGV) and a plurality of negative polarity reference gamma voltages (NRGV) from an external reference gamma voltage supply unit (not shown), and the plurality of positive polarities The reference gamma voltage PRGV is subdivided to generate a plurality of positive polarity grayscale voltages PGV, and at the same time, the plurality of negative polarity reference gamma voltages NRGV are subdivided to generate a plurality of negative polarity grayscale voltages NGV. Here, each of the plurality of positive and negative gradation voltages PGV and NGV has different voltage levels corresponding to the total number of gradations according to the number of bits of the digital data signal. In addition, the gradation voltage generator 120 may individually generate a plurality of positive and negative polarity gradation voltages PGV and NGV corresponding to each of the red, green, and blue digital data signals. The data driving integrated circuit 100 includes a red gradation voltage generator (not shown), a green gradation voltage generator (not shown), and a red gradation voltage generator (not shown).

The digital processing unit 130 generates a sequential sampling signal by using the source start pulse (SSP) and the source shift signal (SSC) supplied from the signal control unit 110, and in a horizontal line unit from the signal control unit 110 After sequentially supplying a plurality of supplied digital data signals R, G, and B according to the sampling signal, the sampled plurality of sampled data signals are simultaneously fed to the analog processing unit 140 according to the source output enable signal SOE. Output. To this end, the digital processing unit 130 according to an example sequentially samples the shift register unit (not shown) for sequentially outputting the sampling signal, and a plurality of digital data signals R, G, and B according to the sampling signal. It can be configured to include a latch (not shown) to output at the same time.

The analog processing unit 140 uses a plurality of positive and negative polarity gradation voltages (PGV, NGV) supplied from the gradation voltage generation unit 120 to output a plurality of sampling data signals simultaneously output from the digital processing unit 130. Each of (Sdata) is converted into a positive or negative data voltage according to a polarity control signal (POL) supplied from the signal controller 110 and then output through a plurality of output channels. The polarity of the data voltage Vdata output through each of the plurality of output channels may be reversed in units of output channels. For example, during an odd-numbered frame, a positive data voltage (+Vdata) may be output from an odd-numbered output channel of the plurality of output channels, and a negative-polarity data voltage (-Vdata) may be output from an even-numbered output channel. . During the even-numbered frame, a negative data voltage (-Vdata) may be output from the odd-numbered output channel of the plurality of output channels, and a positive data voltage (+Vdata) may be output from the even-numbered output channel. In addition, the polarities of the data voltages output from the plurality of output channels in one horizontal period unit may be inverted in a column inversion method or inverted in a vertical 2 dot inversion method according to the polarity control signal POL. It is not limited, and may be reversed in different inversion schemes according to the power consumption viewpoint and the image quality viewpoint of the data driving integrated circuit 100.

The analog processing unit 140 according to an example may include a plurality of digital-analog conversion units (not shown) connected to a plurality of output channels. Each of the plurality of digital-analog converters selects and outputs any one positive polarity gradation voltage (PGV) corresponding to the sampling data signal (Sdata) among the plurality of positive gradation voltages (PGV) and outputs it. (Not shown), and a negative polarity digital-to-analog converter (not shown) that selects and outputs any one negative polarity grayscale voltage NGV corresponding to the sampling data signal Sdata among a plurality of positive polarity grayscale voltages PGV (not shown) ), and one of the positive polarity gradation voltage (PGV) output from the positive-polarity digital-to-analog converter and the negative polarity gradation voltage (NGV) output from the negative-polarity digital-to-analog converter to the polarity control signal POL. It can be configured to include a multiplexer (not shown) to select and output accordingly.

The analog processing unit 140 according to another example, as shown in Figure 2, the first multiplexer unit 141, a plurality of positive digital to analog converters (PDAC), a plurality of negative polarity digital to analog converters (NDAC) , A second multiplexer unit 143 and an output amplifier unit 145.

The first multiplexer unit 141 includes a plurality of first multiplexers MUX1 selectively outputting two adjacent sampling data signals Sdata according to the polarity control signal POL.

Each of the plurality of positive polarity digital-to-analog converters PDAC uses an odd number of the plurality of first multiplexers MUX1 by using a plurality of positive polarity gradation voltages PGV supplied from the gradation voltage generator 120. The sampling data signal Sdata output from the second multiplexer is converted into a positive gradation voltage PGV and output.

The plurality of negative-polarity digital-to-analog converters (NDACs) are an even number of the plurality of first multiplexers (MUX1) by using a plurality of negative-polarity gradation voltages (NGV) supplied from the gradation voltage generator 120. The sampling data signal Sdata output from the multiplexer is converted into a negative polarity grayscale voltage NGV and output.

The second multiplexer unit 143 may be any one of a positive polarity grayscale voltage (PGV) and a negative polarity grayscale voltage (NGV) supplied from each of the adjacent positive polarity digital-analog converter (PDAC) and the negative polarity digital-analog converter (NDAC). It comprises a plurality of second multiplexer (MUX2) to select and output one of the data voltage (+Vdata/-Vdata) according to the polarity control signal (POL).

The output amplifier unit 145 buffers data voltages (+Vdata/-Vdata) output from each of the second multiplexers MUX2 of the second multiplexer unit 143, thereby corresponding output channels (CH _N , CH _{N + 1} , CH _{N +2} , CH _{N +3} , ...) and is configured to include a plurality of output amplifiers AMP output to the outside, that is, a liquid crystal display panel.

As described above, since the analog processing unit 140 according to the other example controls the output signals of the first and second multiplexers MUX1 and MUX2 according to the polarity control signal POL, a positive polarity digital-to-analog converter ( The number of each of the PDAC) and the negative polarity digital-to-analog converter (PDAC) may be reduced by half compared to the analog processing unit 140 according to the example.

Referring back to FIGS. 1 and 2, the charge share unit 150 has two adjacent output channels CH _N / where data voltages of different polarities (+Vdata/-Vdata, -Vdata/+Vdata) are output. CH _{N +1} , CH _{N +2} /CH _{N +3} , ...) are electrically connected to each other according to the first mode signal MS1 input from the signal control unit 110, or data of the same polarity. The two adjacent output channels (CH _N /CH _{N +2} , CH _N+1 /CH _N+3 , ...) on which voltages (+Vdata/+Vdata, -Vdata/-Vdata) are output, are signaled as above. According to the second mode signal MS2 input from the control unit 110, they are electrically connected to each other. Through this, the charge sharing unit 150 changes the charge sharing mode for the plurality of output channels according to the first or second mode signals MS1 and MS2 to reduce the driving and polarity transition levels of the output amplifier 145 By doing so, heat generation and power consumption of the data driving integrated circuit 100 are reduced. In the following description, two adjacent output channels (CH _N /CH _{N +1} , CH _{N +2} /CH _{N +} ) to which data voltages of different polarities (+Vdata/-Vdata, -Vdata/+Vdata) are output. ₃ , ...) will be defined as the first channel group, and two adjacent output channels (CH _N /CH _N ) to which data voltages (+Vdata/+Vdata, -Vdata/-Vdata) of the same polarity are output. ₊₂ , CH _{N +1} /CH _{N +3} , ...) will be defined as a second channel group. Here, the first channel group may include a 2N-1 (where N is a natural number) output channel and a 2N output channel among a plurality of output channels, that is, odd-numbered output channels and even-numbered output channels adjacent to each other. In addition, the second channel group may include two adjacent odd-numbered output channels and two adjacent even-numbered output channels among a plurality of output channels.

The first mode signal MS1 is a signal for driving the charge sharing unit 150 in a first charge sharing mode. According to the first mode signal MS1, the charge share unit 150 outputs channels included in the first output group (CH _N /CH _{N +1)} during a charge sharing period in which the voltage of the output channel is transitioned. , CH _{N +2} /CH _{N +3} , ...) are electrically connected to each other (short) to include data voltages (+Vdata/-Vdata, -Vdata/+Vdata) of opposite polarity in the first output group. Charged channels (CH _N /CH _{N +1} , CH _{N +2} /CH _{N +3} , ...).

The second mode signal MS2 is a signal for driving the charge sharing unit 150 to a second charge sharing mode different from the first charge sharing mode. According to the second mode signal MS2, the charge sharing unit 150 outputs channels CH _N /CH _{N +2} , CH _{N +1} / included in the second output group during the charge sharing period. CH _{N +3} , ...) are electrically connected to each other to output data channels of the same polarity (+Vdata/+Vdata, -Vdata/-Vdata) in the second output group (CH _N /CH _{N +2} , CH _{N +1} /CH _{N +3} , ...).

As described above, the data driving integrated circuit 100 according to an embodiment of the present invention includes first and second according to the first or second mode signals MS1 and M2 during a charge sharing period in which voltages of output channels are transitioned. By selectively performing the 2 charge sharing mode, heat generation and power consumption may be reduced.

FIG. 3 is a circuit diagram for explaining a charge sharing unit according to an embodiment of the present invention shown in FIG. 1, and FIGS. 4 and 5 are circuit diagrams for explaining an operating state according to a charge sharing mode of the charge sharing unit shown in FIG. 3 admit.

3 to 5, the charge sharing unit 150 according to an exemplary embodiment of the present invention may include first and second charge sharing circuits 151 and 153.

The first charge sharing circuit 151 is for performing the above-described first charge sharing mode CSM1 according to the first mode signal MS1, and a 2N-1 output channel included in the first channel group (CH _N , CH _{N +2} , ...) and the 2N output channels (CH _{N +1} , CH _{N +3} , ...) are electrically connected to each other so that data voltages of opposite polarities (+Vdata/-Vdata , -Vdata/+Vdata) is occupied by the 2N-1 output channels (CH _N , CH _{N +2} , ...) and the 2N output channels (CH _{N +1} , CH _{N +3} , ...). Share. To this end, the first charge sharing circuit 151 may include a plurality of first switching elements T1, a plurality of second switching elements T2, and a plurality of connection wirings CL. Each of the plurality of first and second switching elements T1 and T2 may be formed of an N-type transistor or a P-type transistor.

Each of the plurality of first switching elements T1 is turned on or off according to the first mode signal MS1, and corresponding 2N-1 output channels CH _N , CH _{N +2} , ... ) Is selectively connected to one end of the corresponding connection wiring CL1. To this end, each of the plurality of first switching elements M1 is a gate terminal connected to a first mode signal line MSL1 to which the first mode signal MS1 is supplied, and a corresponding 2N-1 output channel CH _N , CH _{N +2} , ...), and a drain terminal connected to one end of the corresponding first connection wiring CL1.

Each of the plurality of second switching elements T2 is turned on or off at the same time as the first switching element T1 according to the first mode signal MS1, thereby corresponding to the corresponding 2N output channel CH _{N + 1} , CH _{N +3} , ...) are selectively connected to the other end of the corresponding first connection wiring CL1. To this end, the second switching element T2 is a gate terminal connected to a first mode signal line MSL1 to which the first mode signal MS1 is supplied, and a corresponding 2N output channel (CH _{N +1} , CH _{N +3} , ...), and a drain terminal connected to the other end of the corresponding first connection wiring CL1.

Meanwhile, although the first charge sharing circuit 151 is described as being composed of the plurality of first and second switching elements T1 and T2, the first charge sharing circuit 151 is not limited thereto. Selectively select 2N-1 output channels (CH _N , CH _N+2 , ...) and 2N output channels (CH _{N +1} , CH _{N +3} , ...) according to the 1 mode signal (MS1) It may be made of only a plurality of first switching elements T1 connected to each other. In this case, each of the plurality of first switching elements T1 is a gate terminal connected to a first mode signal line MSL1 to which the first mode signal MS1 is supplied, and a corresponding 2N-1 output channel CH _N , CH _{N +2} , ...), and a drain terminal connected to a corresponding 2N output channel (CH _{N +1} , CH _{N +3} , ...).

The second charge sharing circuit 153 is for performing the above-described second charge sharing mode (CSM2) according to the second mode signal MS2, and two adjacent odd-numbered outputs included in the second channel group Channels (CH _N , CH _{N +2} , ...) are electrically connected to each other, and two adjacent even-numbered output channels (CH _{N +1} , CH _{N +3} , ...) are electrically connected to each other. By connecting the same polarity data voltages (+Vdata/+Vdata, -Vdata/-Vdata), two adjacent odd-numbered output channels (CH _N , CH _{N +2} , ...) included in the second channel group At the same time, charge sharing is performed on two adjacent even-numbered output channels (CH _{N +1} , CH _N+3 , ...). To this end, the second charge sharing circuit 153 includes a plurality of first and second switches SW1 and SW2. Here, each of the plurality of first and second switches SW1 and SW2 may be formed of the same N-type transistor or P-type transistor as each of the plurality of first and second switching elements T1 and T2.

Each of the plurality of first switches SW1 selectively _couples two adjacent odd-numbered output channels CH _N , CH _{N +2} , ... according to the second mode signal MS2. To this end, each of the plurality of first switches SW1 has a gate terminal connected to a second mode signal line MSL2 to which the second mode signal MS2 is supplied, and any one of two adjacent odd-numbered output channels can be performed by the second output channel (CH _N, ...) source terminal, and the two adjacent odd-numbered output the remaining odd-numbered output channel of the channel connected to a drain terminal connected to a (CH _{N +2,} ...) .

Each of the plurality of second switches SW2 selectively _couples two adjacent even-numbered output channels CH _{N +1} , CH _{N +3} , ... according to the second mode signal MS2. To this end, each of the plurality of second switches SW2 is a gate terminal connected to a second mode signal line MSL2 to which the second mode signal MS2 is supplied, and an even number of any one of two adjacent even-numbered output channels. It comprises a source terminal connected to the first output channel (CH _{N +1} , ...), and a drain terminal connected to the remaining even-numbered output channel (CH _{N +3} , ...) of two adjacent even-numbered output channels. Can.

In this way, the data driving integrated circuit according to the embodiment of the present invention generates and consumes heat by selectively changing the charge sharing modes CSM1 and CSM2 according to the first and second mode signals MS1 and MS2 provided from the timing controller. Power can be reduced.

6 is a view for explaining a liquid crystal display device according to a first exemplary embodiment of the present invention.

Referring to FIG. 6, the liquid crystal display device according to the first exemplary embodiment of the present invention includes a liquid crystal display panel 210, a gate driver 220, a data driver 230, a data printed circuit board 240, and a timing controller 250 ), and a control substrate 260.

The liquid crystal display panel 210 is configured to include first and second substrates 211 and 213 facing each other with a liquid crystal interposed therebetween.

The first substrate 211 is a thin film transistor array substrate, and includes a display area AA and a non-display area.

The display area AA of the first substrate 211 is a thin film transistor array substrate, and includes a plurality of pixels formed in regions defined by a plurality of gate lines GL and a plurality of data lines DL. Each pixel has a thin film transistor (not shown) connected to the gate line GL and the data line DL and a pixel electrode (not shown) connected to the thin film transistor, and is formed adjacent to the pixel electrode to supply a common voltage. It may be configured to include an electrode (not shown). In this case, the common electrode may be formed on the second substrate 213 according to the driving method of the liquid crystal.

The non-display area of the first substrate 211 is defined as a peripheral area of the display area AA, and the upper area of the non-display area includes a plurality of data link lines connected to each of the plurality of data lines, and a plurality of data link lines. A data pad portion formed of a plurality of data pads connected to each of the data link lines is formed.

The second substrate 213 is a color filter array substrate, and is formed to have a smaller area than the first substrate 211. The second substrate 313 is attached to the first substrate 211 with a liquid crystal layer (not shown) interposed therebetween by a sealing member (not shown), so that the data pad portion is formed. The remaining first substrate 211 except for the upper non-display area is covered.

The second substrate 213 includes a light blocking layer (not shown) that defines a pixel area corresponding to each pixel formed on the first substrate 211, and a color filter (not shown) formed for each pixel area. The common electrode (not shown) may be formed on the second substrate 213 according to the driving method of the liquid crystal.

The gate driver 220 is formed on the left and/or right non-display areas of the liquid crystal display panel 210, that is, the first substrate 213 and is connected to a plurality of gate lines GL. Here, the gate driver 220 may be directly formed on the first substrate 211 together with the process of forming the thin film transistor of each pixel and connected to one side and/or the right side of each of the plurality of gate lines GL. The gate driver 220 generates gate signals having a gate-on voltage level every one horizontal period under the control of the timing controller 250 and sequentially supplies them to a plurality of gate lines GL.

Meanwhile, the gate driver 220 is formed in an integrated circuit (IC) form and is formed in the left and/or right non-display areas of the first substrate 213 so as to be connected to each of the plurality of gate lines GL. It can be connected to the pad portion. In this case, the gate driver 220 of the integrated circuit type may be connected to the gate pad part by a chip on glass method or a chip on film method.

The data driving part 230 is connected to the data pad part formed on the liquid crystal display panel 210, that is, the first substrate 211 and connected to a plurality of data lines DL through the data pad part. The data driving part 230 includes a plurality of data circuit films 232 and a plurality of data driving integrated circuits 234.

Each of the plurality of data circuit films 232 is attached between the data pad portion and the data printed circuit board 240. The data circuit film 232 supplies various signals necessary for driving the data driving integrated circuit 234 supplied through the data printed circuit board 240 to the data driving integrated circuit 234, and the data driving integrated circuit The data voltage output from the output channel of 234 is supplied to the data pad unit.

Each of the plurality of data driving integrated circuits 234 is mounted on a corresponding data circuit film 232. Each of the plurality of data driving integrated circuits 234 receives data control signals, digital data signals, first and second mode signals, etc. from the timing control unit 250 through the data printed circuit board 240, In response to the data control signal, a digital data signal is generated to generate a data voltage having a polarity corresponding to an inversion method, and is supplied to a corresponding data line DL through a corresponding output channel, and the first or second mode for each charge sharing period The voltage of the output channel is charged-shared according to the signal-based charge-sharing mode. As described above, each of the plurality of data driving integrated circuits 234 has the same configuration as the data driving integrated circuit 100 described above with reference to FIGS. 1 to 5, and a duplicate description thereof will be omitted.

The timing control unit 250 is mounted on a control board 260 connected to the data printed circuit board 240 through a signal transmission member 265. The timing control unit 250 controls driving of each of the gate driving unit 220 and the plurality of data driving integrated circuits 234, and digital image data corresponding to each of the plurality of data driving integrated circuits 234 so as to be synchronized with the gate driving unit 220. A signal is provided, and in particular, the first and second mode signals described above are generated to control the charge sharing mode of each of the plurality of data driving integrated circuits 234.

The timing controller 250 according to the first embodiment includes a control signal generator 251, a data processor 253, and a mode signal generator 255, as shown in FIG.

The control signal generation unit 251 is a data enable (DE) signal, a data clock (DCLK) input from a driving system (or graphics card) (not shown) through a user connector 262 installed on the control board 260. , A gate control signal GCS and a plurality of data driving integrated circuits for controlling driving timing of the gate driver 220 based on a timing synchronization signal TSS such as a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync (234) A data control signal (DCS) for controlling each driving timing is generated. Here, the gate control signal GCS may be a gate start pulse, a gate shift clock, a gate output enable, or the like. Further, the data control signal DCS may be a source start pulse, a source sampling clock, a source output enable signal, and a polarity control signal. In particular, the control signal generator 251 generates a polarity control signal according to an inversion driving method of the liquid crystal display panel 210 set based on the vertical sync signal Vsync and the horizontal sync signal Hsync.

The data processing unit 253 arranges the image data Idata input from the driving system through the user connector 262 so as to correspond to the pixel arrangement structure of the liquid crystal display panel 210, and the digital data aligned according to the set data interface method. The data signal RGB is provided to each of the plurality of data driving integrated circuits 234.

The mode signal generation unit 255 is based on the polarity control signal generated by the control signal generation unit 251, as shown in Figure 9, the charge included in each of the plurality of data driving integrated circuit 234 The first and second mode signals MS1 and MS2 are generated to operate the share unit (150 of FIGS. 1 and 2) in the first charge sharing mode (CSM1) or the second charge sharing mode (CSM2), The generated first and second mode signals MS1 and MS2 are generated and provided to the charge share portion of each of the plurality of data driving integrated circuits 234.

As an example, when the liquid crystal display panel 210 is driven by a column inversion method, the mode signal generation unit 255 is set as a blank period of each horizontal period based on the polarity control signal according to the column inversion method. The charge share is generated by generating a first mode signal MS1 at an on level and a second mode signal MS2 at an off level for each charge sharing period CSPo, CSPe. It operates in mode (CSM1).

As another example, when the liquid crystal display panel 210 is driven in a vertical 2 dot inversion method, the mode signal generating unit 255 is based on the polarity control signal according to the vertical 2 dot inversion method in each horizontal period. A first mode signal MS1 having a switch-off level and a second mode signal MS2 having a switch-on level are generated for each odd-numbered charging sharing period CSPo set as a blank period, and the charge-sharing section is described above. Operated in one second charge sharing mode (CSM2), the first mode signal (MS1) at the switch-on level for every even-numbered charge sharing period (CSPe) and the second mode signal (MS2) at the switch-off level ) To operate the charge share unit in the first charge sharing mode (CSM1). As a result, when the polarities of the data voltages supplied to the two adjacent pixels up and down are opposite to each other, the mode signal generator 255 is configured to operate the charge share unit in the first charge sharing mode (CSM1). And second mode signals MS1 and MS2. In addition, when the polarities of the data voltages supplied to two vertically adjacent pixels are the same, the mode signal generation unit 255 is configured to operate the first and second charge sharing units in the second charge sharing mode (CSM2). 2 mode signals MS1 and MS2 are generated.

The timing control unit 250 according to the second embodiment, as shown in Figure 8, the control signal generation unit 351, the data processing unit 353, the mode signal generation unit 355, and the frame memory 357 Including.

Since the control signal generation unit 351 is the same as the control signal generation unit 251 of the timing control unit 250 according to the first embodiment described above, a duplicate description thereof will be omitted.

The data processing unit 353 stores the image data Idata input from the driving system in the frame memory 357 in units of frames, and liquid crystals of the image data Idata of one frame stored in the frame memory 357. Arranged to correspond to the pixel arrangement structure of the display panel 210, the digital data signal RGB aligned according to the set data interface method is provided to each of the plurality of data driving integrated circuits 234.

In addition, the data processing unit 353 analyzes the gradation pattern of the image data Idata stored in the frame memory 357, and generates a mode setting signal MSS according to the analysis result. Specifically, the data processing unit 353 compares and analyzes the image data Idata of adjacent pixels up and down in units of pixels, detects the number of transitions (or transition level) in units of horizontal lines, and detects the number of transitions and the reference value. A mode setting signal MSS in a high state or a low state is generated according to the comparison result of. Here, the number of transitions may be a total sum of gradation deviations for each pixel included in the same horizontal line. For example, when the detected number of transitions is greater than or equal to a reference value, the data processing unit 353 generates a high state mode setting signal (MSS) for operating the charge share unit in the first charge sharing mode. When the detected number of transitions is less than a reference value, a mode setting signal MSS in a low state for operating the charge share unit in the second charge sharing mode may be generated.

The power consumption of the liquid crystal display is affected by the number of transitions of image data according to an inversion method, and the more the number of transitions of image data to be supplied to each pixel included in the current horizontal line compared to the image data of the previous horizontal line, the data voltage The fluctuation range of is increased, thereby increasing the power consumption of the liquid crystal display device. Accordingly, it is advantageous from a viewpoint of reducing power consumption that the charge share is operated in the first charge sharing mode as the number of transitions is relatively large, and conversely, as the number of transitions is relatively small, the charge share is charged in the second. Operating in the sharing mode may be advantageous from a viewpoint of reducing power consumption. Therefore, the reference value is set to the number of transitions that does not affect the image quality while reducing power consumption through a simulation of measuring power consumption by changing the total number of transitions for the image data of each pixel included in the horizontal line.

The mode signal generation unit 355 according to the mode setting signal (MSS) provided from the data processing unit 353, as shown in FIG. 9, the charge share unit is the first charge sharing mode (CSM1) or the The first and second mode signals MS1 and MS2 for operating in the second charge sharing mode (CSM2) are generated and provided to each of the plurality of data driving integrated circuits 234.

The mode signal generating unit 355 is configured to charge the charging share during the charge sharing periods CSPo and CSPe in response to the high state mode setting signal MSS supplied from the data processing unit 353. A first mode signal MS1 having a switch-on level and a second mode signal MS2 having a switch-off level for operating in the charge sharing mode CSM1 may be generated.

The mode signal generating unit 355 is configured to charge the charging share during the charge sharing periods CSPo and CSPe in response to the low mode setting signal MSS supplied from the data processing unit 353. A first mode signal MS1 having a switch-off level and a second mode signal MS2 having a switch-on level may be generated to operate in the charge sharing mode CSM1.

As described above, in the liquid crystal display according to the first embodiment of the present invention, the charge sharing modes CSM1 and CSM2 are based on the inversion method or the first and second mode signals MS1 and MS2 based on the gradation pattern of image data. By selectively changing, heat generation and power consumption of the data driving integrated circuit 234 may be reduced. For example, when the embodiment of the present invention is applied to a full white image and is displayed on the liquid crystal display panel 210 according to the vertical 2 dot inversion method, the swing of the data voltage shown in FIG. 9 As in the (swing) waveform, the first charge sharing mode (CSM1) is performed when the polarity of the data voltage is inverted according to the first and second mode signals MS1 and MS2, and the second charge is maintained when the data voltage is the same polarity. It can be seen that the sharing mode (CSM2) is performed.

10 is a view for explaining a liquid crystal display device according to a second exemplary embodiment of the present invention, which is configured by changing a position where a charge share is formed. In the following description, redundant description of the same or corresponding components as in the previous embodiment will be omitted, and only the charge share unit will be described.

First, as illustrated in FIGS. 1 and 6, the charge share unit 150 of the liquid crystal display according to the first exemplary embodiment of the present invention is embedded in a plurality of data driving integrated circuits 234.

On the other hand, as shown in FIG. 10, the charge share unit 150 of the liquid crystal display according to the second exemplary embodiment of the present invention includes the liquid crystal display panel 210 described above, and more specifically, the first substrate 211. A non-display area between the upper data pad portion and the display area AA may be formed. In this case, each of the switching elements of the first charge-sharing circuit 151 and the switches of the second charge-sharing circuit 153 constituting the charge-sharing unit 150 includes a plurality of data lines along with a thin film transistor forming process of each pixel. It is to be formed directly in the non-display area of the first substrate 211. The charge share unit 150 is connected to each of a plurality of data link lines, the control board 260, the signal transmission member 265, the data printed circuit board 240, the data circuit film 232, and data The first charge sharing mode or the second charge sharing mode is performed according to the first and second mode signals MS1 and MS2 supplied from the timing controller 250 through the pad unit.

As described above, in the liquid crystal display device according to the second embodiment of the present invention, heat generation and power consumption of the data driving integrated circuit 234 may be reduced in the same manner as the liquid crystal display device according to the first embodiment of the present invention.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical details of the present invention. It will be clear to those who have the knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be interpreted to be included in the scope of the present invention.

100, 234: data driving integrated circuit 120: gradation voltage generator
130: digital processing unit 140: analog processing unit
150: charge sharing unit 151: first charge sharing circuit
153: second charge sharing circuit 210: liquid crystal display panel
220: gate driver 230: data driver
250: timing control unit 251, 351: control signal generation unit
253, 353: data processing unit 255, 355: mode signal generation unit

Claims (16)

A digital processing unit which sequentially samples a plurality of input digital data signals and simultaneously outputs a plurality of sampled sampling data signals;
An analog processing unit converting each of the plurality of sampling data signals output from the digital processing unit into a positive data voltage or a negative data voltage according to a polarity control signal and outputting the data through a plurality of output channels; And
When the first mode signal is input, the first charge sharing mode is performed to firstly connect the 2N-1 (however, N is a natural number) output channel and the 2N output channel to which data voltages of different polarities are output. The charging sharing circuit and the second charging sharing mode are performed according to the second mode signal different from the first mode signal to electrically connect and connect even two odd numbered output channels adjacent to which the same polarity data voltage is output. And a charge share portion having a second charge sharing circuit electrically connected to each other. delete According to claim 1,
The first charge sharing circuit is a plurality of switching selectively connecting the adjacent 2N-1 (where N is a natural number) output channel and the 2N output channel among the plurality of output channels according to the first mode signal. A data driven integrated circuit comprising a device. According to claim 1,
The second charge sharing circuit,
A plurality of first switches electrically connecting two adjacent odd-numbered output channels among the plurality of output channels according to the second mode signal; And
And a plurality of second switches electrically connecting two adjacent even-numbered output channels among the plurality of output channels according to the second mode signal. A first substrate including a display area having a plurality of pixels formed for each area defined by the intersection of a plurality of gate lines and a plurality of data lines, and a non-display area excluding the display area, and opposingly bonded to the first substrate A liquid crystal display panel including a second substrate;
A gate driver driving the gate line;
A data driver including a data driving integrated circuit according to any one of claims 1 and 3 and 4 for supplying a data voltage to each of the plurality of data lines; And
A timing control unit controlling the driving of the gate driving unit and the data driving unit, arranging input image data into the plurality of digital data signals, supplying the data to the data driving integrated circuit, and generating the first and second mode signals. Included, a liquid crystal display device. The method of claim 5,
The timing controlling part includes a mode signal generating part generating the first and second mode signals based on the polarity control signal,
The mode signal generation unit,
When the polarities of the data voltages supplied to the two adjacent pixels are opposite to each other, the first and second mode signals for operating the charge share unit in the first charge sharing mode are generated,
And when the polarities of data voltages supplied to the two adjacent pixels are the same, generate the first and second mode signals for operating the charge share unit in the second charge sharing mode. The method of claim 5,
The timing control unit,
A data processor that analyzes the image data and generates a mode setting signal for setting the charge share to the first charge sharing mode or the second charge sharing mode; And
And a mode signal generator configured to generate the first and second mode signals according to the mode setting signal. The method of claim 7,
The data processing unit compares and analyzes image data of adjacent pixels up and down in units of pixels, detects the number of transitions in units of horizontal lines, and generates the mode setting signal according to the comparison result of the detected number of transitions and a reference value. Display device. The method of claim 8,
The data processing unit,
When the detected number of transitions is greater than or equal to a reference value, a mode setting signal for setting the charge share to the first charge sharing mode is generated,
And a mode setting signal for setting the charge share to the second charge sharing mode when the detected number of transitions is less than a reference value. The method of claim 5,
The charge share portion is formed in a non-display area of the first substrate so as to be connected to the plurality of data lines. According to claim 1,
The analog processing unit,
A first multiplexer unit including a plurality of first multiplexers selectively outputting two adjacent sampling data signals according to the polarity control signal;
A digital-to-analog converter converting and outputting the sampling data signal into a positive polarity gradation voltage and a negative polarity gradation voltage according to the polarity control signal; And
And a second multiplexer unit including a plurality of second multiplexers for selecting and outputting one of the positive and negative grayscale voltages as a data voltage according to the polarity control signal. A first substrate including a display area having a plurality of pixels formed for each area defined by the intersection of a plurality of gate lines and a plurality of data lines, and a non-display area excluding the display area, and opposingly bonded to the first substrate A liquid crystal display panel including a second substrate;
A gate driver driving the gate line;
A 2N-1 (where N is a natural number) output channel that supplies a data voltage to each of the plurality of data lines, and performs a first charge sharing mode when a first mode signal is input, and outputs data voltages of different polarities. A first charge sharing circuit that electrically connects the 2N output channels with each other, and two adjacent charge output voltages of the same polarity by performing a second charge sharing mode according to the second mode signal different from the first mode signal. A data driver including a second charge sharing circuit electrically connecting odd-numbered output channels and electrically connecting even-numbered output channels; And
And a timing control unit controlling the driving of the gate driver and the data driver, arranging input image data into a plurality of digital data signals, supplying the data to the data driver, and generating the first and second mode signals. Liquid crystal display device. The method of claim 12,
The timing controlling part includes a mode signal generating part generating the first and second mode signals based on a polarity control signal,
The mode signal generation unit,
When the polarities of the data voltages supplied to the two adjacent pixels are opposite to each other, generate the first and second mode signals for operating the first charge sharing circuit in the first charge sharing mode,
A liquid crystal display generating the first and second mode signals for operating the second charge sharing circuit in the second charge sharing mode when the polarities of the data voltages supplied to the two adjacent pixels are the same. Device. The method of claim 12,
The timing control unit,
A data processor configured to analyze the image data and generate a mode setting signal for setting the first charge sharing mode or the second charge sharing mode; And
And a mode signal generator configured to generate the first and second mode signals according to the mode setting signal. The method of claim 14,
The data processing unit compares and analyzes image data of adjacent pixels up and down in units of pixels, detects the number of transitions in units of horizontal lines, and generates the mode setting signal according to the comparison result of the detected number of transitions and a reference value. Display device. The method of claim 15,
The data processing unit,
When the detected number of transitions is greater than or equal to a reference value, a mode setting signal for setting the first charge sharing mode is generated,
A liquid crystal display device for generating a mode setting signal for setting the second charge sharing mode when the detected number of transitions is less than a reference value.

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