KR20070080427A - Driving liquid crystal display and apparatus for driving the same - Google Patents

Abstract

A liquid crystal display device and an apparatus for driving the same are provided to uniformly charge liquid crystal cells by allowing the pulse width of even-numbered pulses to be different from that of odd-numbered pulses. A liquid crystal display device includes an LCD panel(134), a control signal generator, a data driving circuit(132), and a gate driving circuit(133). Plural liquid crystal cells are formed by plural data lines(D1~Dm) and plural gate lines(G1~Gn) arranged to cross with each other. The control signal generator generates a source output signal and generates a gate output signal with different pulse width every horizontal period. The data driving circuit inverts the polarity of a data voltage every N horizontal periods, and supplies the data voltage to the data lines in response to the source output signal. The gate driving circuit supplies a scan pulse to the gate line in response to the gate output signal.

Description

Liquid crystal display and its driving method {DRIVING LIQUID CRYSTAL DISPLAY AND APPARATUS FOR DRIVING THE SAME}

1 is a view schematically showing the data polarity of a liquid crystal panel driven in a one dot inversion scheme.

FIG. 2 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a two dot inversion scheme. FIG.

3 is a block diagram schematically illustrating a liquid crystal display device driven in a two dot inversion method.

FIG. 4 is an enlarged view of a 4x4 liquid crystal cell matrix vertically arranged side by side in the liquid crystal panel of FIG.

FIG. 5 is a waveform diagram illustrating data of a 2-dot inversion method filled in a liquid crystal cell matrix as shown in FIG. 4.

6 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

7 is a waveform diagram showing waveforms of first and second gate output signals generated from a timing controller.

8 is a circuit diagram showing in detail the GOE generation circuit shown in FIG.

FIG. 9 is a block diagram showing in detail the data driving circuit shown in FIG. 6; FIG.

FIG. 10 is a detailed block diagram illustrating the gate driving circuit of FIG. 6. FIG.

Fig. 11 is a waveform diagram showing waveforms of scan pulses output in accordance with a gate output signal.

FIG. 12 is a waveform diagram showing charging characteristics of data supplied to a liquid crystal cell matrix as shown in FIG. 4 according to a gate output signal according to the present invention; FIG.

FIG. 13 is a block diagram illustrating a virtually partitioned liquid crystal panel in a liquid crystal display according to a second exemplary embodiment of the present invention. FIG.

FIG. 14 is a waveform diagram illustrating an example of a gate output signal supplied to each block of a liquid crystal panel partitioned into a plurality of blocks as shown in FIG.

<Description of Symbols for Main Parts of Drawings>

131: timing controller 132: data driving circuit

133: gate driving circuit 134: liquid crystal panel

135: GOE conversion circuit 170: multiplex

181: first latch 182: shift register

183: second latch 184: digital-to-analog converter

185: Charge share circuit 186: Buffer

200: stage 201: level shift

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for improving display quality of a liquid crystal display device driven by a 2-dot inversion method.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. In an active matrix type liquid crystal display, switching elements are formed in each liquid crystal cell, which is advantageous for displaying a moving image. As the switching device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

The LCD is driven in an inversion manner to reduce flicker and afterimage by periodically inverting the polarity of data charged in the liquid crystal cell. The inversion method includes a line inversion method for inverting polarities of data between adjacent liquid crystal cells in a vertical line direction, a column inversion method for inverting polarities of data between adjacent liquid crystal cells in a horizontal line direction, a vertical line direction and a horizontal line direction. There is a dot inversion method of inverting the polarity of data between adjacent liquid crystal cells. Of these inversion methods, the dot inversion method is mainly selected because flicker hardly appears in the vertical and horizontal directions.

In the dot inversion scheme, as illustrated in FIG. 1, polarities of data supplied to adjacent liquid crystal cells in the vertical direction are opposite to each other, and polarities of data supplied to adjacent liquid crystal cells in the horizontal direction are opposite to each other. The polarity of the data is inverted every frame (Fn-1, Fn). The dot inversion method is most widely used in liquid crystal display devices because flicker is minimized in both the vertical and horizontal directions.

In the dot inversion scheme of FIG. 2, the polarity of data is inverted in units of two dots in the horizontal and vertical directions. The two-dot inversion method as shown in FIG. 2 has the advantage of lower power consumption than the one-dot inversion method as shown in FIG.

3 schematically shows a conventional liquid crystal display device driven in a two dot inversion method.

Referring to FIG. 3, a conventional liquid crystal display device includes a liquid crystal panel 34 in which data lines D1 to Dm and gate lines G1 to Gn cross each other, and TFTs for driving the liquid crystal cell Clc are formed at the intersections thereof. ), A data driving circuit 32 for supplying data to the data lines D1 to Dm of the liquid crystal panel 34, and a scan pulse for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 34. And a timing controller 31 for controlling the gate driving circuit 33 and the data driving circuit 32 and the gate driving circuit 33.

The data driving circuit 32 stores a shift register for sampling a clock, a register for temporarily storing data, a line for storing data in response to a clock signal from the shift register, and simultaneously outputs the stored one line of data. Latch, a digital / analog converter for selecting a positive / negative gamma voltage corresponding to the digital data value from the latch, and a data line to which analog data converted by the positive / negative gamma voltage is supplied (D1 to Dm) ), And a multiplexer for selecting) and an output buffer connected between the multiplexer and the data line. The data driving circuit 32 inverts the polarity of the data voltages supplied to the data lines D1 to Dm in units of two horizontal periods according to a two dot inversion scheme, and converts the data voltages into a source output enable signal. Enable: Supply the data lines D1 to Dm of the liquid crystal panel 34 according to SOE.

The gate driving circuit 33 includes a shift register for sequentially generating scan pulses, and a level shifter for shifting the voltage of the scan pulses to a level suitable for driving the liquid crystal cell Clc. The gate driving circuit 33 sequentially supplies scan pulses to the gate lines G1 to Gn under the control of the timing controller 31.

The timing controller 31 controls the gate control signal GDC and the data driving circuit 32 for controlling the gate driving circuit 33 by using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, a polarity signal POL, and the like. Here, the source output signal SOE is a signal indicating the output time of the data. The gate control signal GDC includes a gate shift clock GSC, a gate output enable GOE, a gate start pulse GSP, and the like. Here, the gate output signal GOE is a control signal indicating an output time point of the gate driving circuit 33.

FIG. 4 is an enlarged view of a matrix of 4x4 liquid crystal cells arranged vertically side by side in the liquid crystal panel, and FIG. 5 is a two-dot inversion type data voltage supplied to four liquid crystal cells shown in FIG. Indicates.

4 and 5, the liquid crystal display of the two dot inversion method inverts the polarity of the data voltage every two horizontal line periods. Therefore, the positive polarity voltage higher than the common voltage Vcom is applied to the liquid crystal cell A of the first horizontal line HL1 and the liquid crystal cell B of the second horizontal line HL2 connected to the first data line DL1. On the other hand, the liquid crystal cell C of the third horizontal line HL3 connected to the first data line DL1 and the liquid crystal cell D of the fourth horizontal line HL4 are connected to the common voltage Vcom. Low negative voltage is applied.

However, in such a two-dot inversion system, a liquid crystal cell to which a positive voltage (or negative voltage) rising from the negative voltage (or positive voltage) is applied, and a positive voltage changing from the positive voltage (or negative voltage) The amount of charge of data charged in the liquid crystal cell is different between the liquid crystal cells to which the negative voltage is applied. This is because the rising time (or falling time) of the positive voltage (or negative voltage) rising from the negative voltage (or positive voltage) is long, while the positive voltage varies from the positive voltage. This is because the rising time (or polling time) of R is relatively short. Due to such a difference in charging characteristics, the second and fourth horizontal lines HL2 and HL4 may have the same gray level data voltage as compared to the liquid crystal cells A and C of the first and third horizontal lines HL1 and HL3. The liquid crystal cells B and D of FIG. 2 appear brighter, and as a result, a luminance difference is generated between neighboring horizontal lines.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof to improve the display quality of a liquid crystal display device driven by a 2-dot inversion method.

In order to achieve the above object, the liquid crystal display according to the first embodiment of the present invention comprises a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are arranged; A control signal generator generating a source output signal and generating a gate output signal having a different pulse width in horizontal period units; A data driving circuit for inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line in response to the source output signal; And a gate driving circuit supplying a scan pulse to the gate line in response to the gate output signal.

The control signal generator further generates a polarity control signal indicating the polarity of the data voltage.

The data driving circuit inverts the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal and in response to the source output enable signal, first data and second data having the same polarity as the first data. The third and fourth data having different polarities from the first and second data are sequentially output.

The liquid crystal panel includes a plurality of thin film transistors for supplying data from the data lines to the liquid crystal cells in response to the scan pulse.

The scan pulse may include an odd scan pulse for supplying the first data voltage to a first liquid crystal cell and for supplying the third data voltage to a third liquid crystal cell disposed below the first liquid crystal cell; Supplying the second data voltage to a second liquid crystal cell disposed between the first liquid crystal cell and the third liquid crystal cell and supplying the fourth data voltage to a fourth liquid crystal cell disposed under the third liquid crystal cell And the even scan pulse for the even scan pulse; the pulse width of the even scan pulse is narrower than that of the odd scan pulse.

The gate output signal includes: an odd gate output signal for controlling the output of the odd scan pulse; An even gate output signal for controlling the output of the even scan pulse; The pulse width of the even gate output signal is wider than that of the odd gate output signal.

The control signal generator may include an odd gate output signal in which pulses appear in units of two horizontal periods, an even gate output signal in which pulses appear in units of two horizontal periods and a delay of about one horizontal period compared to the first gate output signal, and the A timing controller for generating a selection control signal for selection of odd and even gate output signals; And a multiplexer for alternately outputting the odd and even gate output signals in units of one horizontal period in response to the selection control signal.

A liquid crystal display according to a second embodiment of the present invention comprises: a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; A control signal generator for generating a source output signal and generating a gate output signal having a different pulse width according to the position of the liquid crystal panel; A data driving circuit for inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line in response to the source output signal; And a gate driving circuit supplying a scan pulse to the gate line in response to the gate output signal.

The liquid crystal panel includes a first block closer to the data driving circuit, a second block located farther from the data driving circuit than the first block, and a third block farther from the data driving circuit than the second block. Include.

The control signal generator includes a gate output signal of a first block including a first odd pulse and a first even pulse having substantially the same pulse width, and a second even pulse having a wider pulse width than that of the first even pulse. And a gate output signal of the third block including the gate output signal of the block and a third even pulse having a wider pulse width than the second even pulse.

The gator driving circuit causes the data to be displayed on the first block to be charged in each liquid crystal cell in response to the gate output signal of the first block, and to the second block in response to the gate output signal of the second block. Data to be displayed is charged in each liquid crystal cell, and data to be displayed in the third block is charged in each liquid crystal cell in response to a gate output signal of the third block.

 The control signal generator has an odd gate output signal in which pulses appear in units of two horizontal periods, and a pulse having a delay in about one horizontal period compared to the odd gate output signal and having a pulse width different according to the block in two horizontal period units. A timing controller for generating a gate output signal and a selection control signal for selecting the gate output signals; And a multiplexer configured to alternately output the first and second gate output signals in units of one horizontal period in response to the selection control signal.

A method of driving a liquid crystal display according to a first embodiment of the present invention comprises the steps of: generating a source output signal; Generating a gate output signal having a different pulse width in horizontal period units; Inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line of the liquid crystal panel in response to the source output signal; And supplying a scan pulse to a gate line of the liquid crystal panel in response to the gate output signal.

A method of driving a liquid crystal display according to a second exemplary embodiment of the present invention includes generating a source output signal; Generating a gate output signal having a different pulse width according to the position of the liquid crystal panel; Inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line of the liquid crystal panel in response to the source output signal; And supplying a scan pulse to a gate line of the liquid crystal panel in response to the gate output signal.

The liquid crystal panel includes a first block closer to the data driving circuit, a second block located farther from the data driving circuit than the first block, and a third block farther from the data driving circuit than the second block. Including; The generating of the gate output signal may include a gate output signal of a first block including a first odd pulse and a first even pulse having substantially the same pulse width, and a second even pulse having a wider pulse width than the first even pulse. And generating a gate output signal of the second block including the gate output signal of the second block and a third even pulse having a wider pulse width than the second even pulse.

The supplying of the scan pulse to the gate line of the liquid crystal panel causes the data to be displayed in the first block to be filled in each liquid crystal cell in response to the gate output signal of the first block, and the gate of the second block. Data to be displayed in the second block is filled in each liquid crystal cell in response to an output signal, and data to be displayed in the third block is charged in each liquid crystal cell in response to a gate output signal of the third block. It includes a step.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 14.

6 to 12 show a liquid crystal display according to a first embodiment of the present invention and a driving method thereof.

Referring to FIG. 6, the liquid crystal display according to the first exemplary embodiment of the present invention transmits the first gate output signal GOE1 and the second gate output signal GOE2 having different pulse widths to the gate driving circuit 133. A GOE conversion circuit 135 for supplying, a data driving circuit 132 for supplying data to the data lines D1 to Dm of the liquid crystal panel 134, a first gate output signal GOE1 and a second gate A gate driving circuit 133 for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 134 in response to the output signal GOE2, and a data driving circuit 132 and a gate driving circuit ( 133 and a timing controller 131 for controlling the GOE conversion circuit 135.

The liquid crystal panel 154 is substantially the same as that shown in FIG. Reference numeral 'Cst' denotes a storage capacitor. The storage capacitor Cst may be formed between the liquid crystal cell Clc connected to the k-th gate line (where k is a positive integer between 1 and n) and the k-1 th front gate line, and the k th It may be formed between the liquid crystal cell Clc connected to the gate line and a separate common line.

The GOE conversion circuit 135 alternately selects the first (odd) gate output signal GOE1 and the second (good) gate output signal GOE2 input from the timing controller 131 at approximately one horizontal period period, and selects the selected gate. The output signals GOE1 and GOE2 are supplied to the gate driving circuit 133.

The data driving circuit 132 responds to the digital data RGB input from the timing controller 131 in response to the control signal DDC input from the timing controller 131. The data lines D1 to Dm of the liquid crystal panel 134. ) Will be supplied. That is, the data driving circuit 132 generates data having the same polarity for two horizontal periods according to the polarity control signal POL included in the control signal DDC from the timing controller 131, and then reverses the polarity of the data. Inverts the polarities of horizontally neighboring data to each other. The data driving circuit 132 will be described in detail with reference to FIG. 9.

The gate driving circuit 133 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signals GDC (GOE1 and GOE2) from the timing controller 131 and the GOE conversion circuit 135. .

The timing controller 131 controls the gate control signal GDC and the data driving circuit 132 to control the gate driving circuit 133 by using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. As shown in FIG. 9, the data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity signal POL, and the like. As shown in FIG. 10, the gate control signal GDC includes a gate shift clock GSC, a first gate output signal GOE1, a second gate output signal GOE2, a gate start pulse GSP, and the like. .

The timing controller 151 varies the number of counts of the clock CLK, and the first gate output signal GOE1 having a short pulse width and a period of 1 horizontal period 1H as shown in FIG. Generates a second gate output signal GOE2 having one horizontal period 1H. As such, the second gate output signal GOE2 is set to be wider than the pulse width of the first gate output signal GOE1, thereby reducing the time for the even data to be charged to the liquid crystal cell and charging with the even data and the liquid crystal cell filled with the odd data. The filling amount of the liquid crystal cell becomes uniform. This will be described in detail with reference to FIG. 12.

7 illustrates the first and second gate output signals GOE1 and GOE2 generated from the timing controller 131.

Referring to FIG. 7, the first and second gate output signals GOE1 and GOE2 are control signals for controlling the output time of the scan pulse SP output from the gate driving circuit 133. The pulse width of the first gate output signal GOE1 is set to W1, and the second gate output signal GOE2 controls the output time of the scan pulse SP relatively short compared to the first gate output signal GOE2. The pulse width is set to W2 which is wider than that W1 of the first gate output signal GOE1 as a control signal.

8 shows the GOE conversion circuit 135 in detail.

Referring to FIG. 8, the GOE conversion circuit 135 may apply one of the first gate output signal GOE1 and the second gate output signal GOE2 in response to the switch control signal MUXC2 from the timing controller 131. A MUX 170 is provided for selection.

The switch control signal MUXC2 has two logic values, high logic and low logic. The MUX 170 controls the first gate output signal GOE1 having a narrow pulse width and the second gate output signal GOE2 having a wide pulse width in approximately one horizontal period unit in response to the high logic value of the switch control signal MUXC2. Alternately, the selected gate output signals GOE1 and GOE2 are supplied to the gate driving circuit 133. The GOE conversion circuit 135 may be embedded in the timing controller 131.

9 schematically shows the data driving circuit 132.

Referring to FIG. 9, the data driving circuit 132 includes a plurality of integrated circuits (ICs), each integrated circuit including a shift register 182 and a first latch (eg, a cascade connected between an input line and a data line). 181, a second latch 183, a digital-to-analog converter (hereinafter referred to as a “DAC”) 184, a charge share circuit 185, and a buffer 186.

The shift register 182 shifts the source start pulse SSP from the timing controller 131 according to the source shift clock signal SSC to generate a sampling signal. In addition, the shift register 182 shifts the source start pulse SSP to transfer a carry signal CAR to the next stage shift register 182.

The first latch 181 samples and stores the digital data RGB according to the sampling signal input from the shift register 182, and supplies the stored digital data to the second latch 183.

The second latch 183 latches the data EFD and RGB input from the first latch 181, and then a second latch in another integrated circuit in response to the source output signal SOE from the timing controller 131. The digital data of one horizontal line latched together with 183 is simultaneously output. At this time, the source output signal SOE is generated approximately every one horizontal period, and each pulse width is constant.

The DAC 184 converts the digital data RGB from the second latch 183 according to the polarity signal POL from the timing controller 131 to the positive analog gamma voltage VPG or the negative analog gamma voltage VNG. Convert to In addition, the voltage generated from the DAC 184 controls the polarity of the data according to an inversion scheme such as a dot inversion, N dot inversion, line inversion, column inversion scheme, etc. in response to the polar line signal POL.

The charge share circuit 185 supplies the charge share voltage to the data line through the buffer 186 during the high logic period of the source output signal SOE generated from the timing controller 131. Here, the charge share voltage is an intermediate voltage between the positive data voltage and the negative data voltage and is equal to or similar to the common voltage Vcom supplied to the common electrode of the liquid crystal cell. This charge share voltage may be generated by a switch circuit that supplies a voltage supplied from a power supply circuit disposed outside the data integrated circuit to the data line during the high logic period of the source output enable SOE. It may be generated by a switch circuit for shorting neighboring data lines to which data of different polarities are supplied during the high logic period of the enable signal SOE.

The buffer 186 outputs the analog gamma voltages VPG and VNG input from the DAC 184 to the data lines D1 to Dm without signal attenuation.

In FIG. 9, reference numeral 'R' denotes a line resistance between the output terminal of the data driving circuit 132 and the data lines D1 to Dm.

10 shows the gate driving circuit 133 in detail.

Referring to FIG. 10, the gate driving circuit 133 includes a plurality of stages 200 ₁ to 200 _n and a shift register for adjusting output of scan pulses according to the first and second gate output signals GOE1 and GOE2. 202 and the level shifters 201 ₁ to 201 _n input to the shift register 202.

The first stage 200 ₁ of the shift register 202 generates a scan pulse in response to the gate start pulse GSP and the gate shift clock GSC from the timing controller 131. The second to nth stages 200 ₂ to 200 _n receive a voltage on the front gate lines G1 to Gn-1 as gate start pulses and respond to the signal and the gate shift clock GSC in response to the scan pulse SP. ) Occurs sequentially. The width of the scan pulse SP output from the shift register 202 is adjusted according to the first and second gate output signals GOE1 and GOE2 as shown in FIG. For example, the width of the scan pulse SP is relatively higher when the second gate output signal GOE2 is input to the shift register 202 than when the first gate output signal GOE1 is input to the shift register 202. Narrows.

The level shifters 201 ₁ to 201 _n are respectively connected to the output terminals of the shift register 202 to convert the swing width of each output signal of the shift register 202 into a swing width suitable for driving the liquid crystal cell Clc. The scan pulses output from the level shifters 201 ₁ to 201 _n have two voltage levels, Vgh and Vgl. A buffer may be provided between the level shifters 201 ₁ to 201 _n and the gate lines G1 to Gn.

 12 shows a gate output signal GOE and a charging voltage of a liquid crystal cell according to the present invention. The charging characteristics of the liquid crystal cells according to the present invention will be described by combining the waveform diagram of FIG. 12 and the 4 × 4 liquid crystal cell matrix of FIG. 4.

4 and 12, the liquid crystal display according to the first exemplary embodiment of the present invention includes an analog data voltage having alternating polarities based on approximately two horizontal periods in response to the source output signal SOE. D1 to Dm) and the TFTs are supplied to the liquid crystal cells Clc.

The pulse widths of the odd and even pulses of the source output signal SOE are constant. On the other hand, the pulse width of the odd pulse of the gate output signal GOE is smaller than the pulse width of the even pulse. At this time, the rising time of the odd pulse of the gate output signal GOE and the rising time of the even pulse are approximately one horizontal period 1H. Accordingly, the liquid crystal cells B and D of the second and fourth horizontal lines HL2 and HL4 may be charged in comparison with the liquid crystal cells A and C of the first and third horizontal lines HL1 and HL3. The output time of data is shorter. As a result, according to the present invention, the charging characteristic nonuniformity between the liquid crystal cell of the odd line and the liquid crystal cell of the even line can be made uniform by the modulation of the gate output signal SOE in the two dot inversion method.

The charge share voltage between the positive data voltage and the negative data voltage is supplied to the data line during the high logic period during which the source output signal SOE is generated.

On the other hand, since the liquid crystal cells close to the data driving circuit 132 have no RC delay due to the line resistance of the data line and the capacitance of the liquid crystal cell, data having the same polarity as the gate output signal GOE shown in FIG. If the pulse width of the gate output signal GOE to be charged is different, charging nonuniformity may result.

13 and 14 illustrate a liquid crystal display and a driving method thereof according to the second embodiment of the present invention.

13 and 14, the liquid crystal display according to the second exemplary embodiment of the present invention virtually converts the liquid crystal panel 134 into a plurality of blocks, for example, three blocks BL1, BL2, and BL3. In this case, the amount of data to be charged in each of the blocks BL1, BL2, and BL3 is controlled by different gate output signals GOE (BL1), GOE (BL2), and GOE (BL2).

The first block BL1 of the liquid crystal panel 134 includes a plurality of horizontal lines and approaches the data driving circuit 132. The gate output signal GOE BL1 for controlling the charge amount of the analog data voltage to be charged in the liquid crystal cells Clc of the first block BL1 is controlled by the source output signal SOE. To control the amount of data to be filled when output, the pulse width has the same odd pulse and even pulse. Therefore, the present invention provides the liquid crystal cells of the first block BL1 that may be generated when the pulse width of the gate output signal GOE is periodically changed in the first block BL1 having almost no delay when the polarity of the data changes. Filling unevenness can be prevented.

The second block BL2 of the liquid crystal panel 134 includes a plurality of horizontal lines and is located farther from the data driving circuit 132 than the first block BL1 to change the line resistance of the data line when the polarity of the data changes. And the RC delay due to the capacitance of the liquid crystal panel is larger than that of the first block BL1. The gate output signal GOE BL2 for controlling the charge amount of the analog data voltage to be charged in the liquid crystal cells Clc of the second block BL2 is controlled by the source output signal SOE. When the output is controlled, the pulse width between the odd pulse and the even pulse is varied to control the amount of data filling, but the pulse width of the even pulse is about 1 to 1.2 times wider than that of the odd pulse. Accordingly, in the present invention, when the polarity of the data changes, in the second block BL2 where the RC delay occurs, the charging time of the excellent data is shortened by the shortage of the odd data whose charging time is shortened due to the delay between the odd data and the even data of the same polarity. In the second block BL2, the liquid crystal cell charging characteristic of the odd data and the liquid crystal cell charging characteristic of the even data can be made uniform.

The third block BL3 of the liquid crystal panel 134 includes a plurality of horizontal lines and is located farther from the data driving circuit 134 than the second block BL2 so that the line resistance of the data line changes when the polarity of the data changes. And the RC delay due to the capacitance of the liquid crystal panel is larger than that of the second block BL2. The gate output signal GOE BL3 for controlling the charge amount of the analog data voltage to be supplied to the liquid crystal cells Clc of the third block BL2 is controlled by the source output signal SOE. When the output is controlled, the pulse width between the odd pulse and the even pulse is varied to control the amount of data filling, but the pulse width of the even pulse is approximately 1.2 to 1.5 times wider than that of the odd pulse. Therefore, in the third block BL3 where a delay occurs when the polarity of the data changes, the charging time of the excellent data is increased by the shortage of the odd data whose charging time is shortened due to the delay between the odd data and the even data of the same polarity. It is possible to shorten the liquid crystal cell charging characteristic of odd data and the liquid crystal cell charging characteristic of even data in the third block BL3.

The liquid crystal display according to the second exemplary embodiment of the present invention is substantially the same as the above-described embodiment except for the second gate output signal GOE2 generated from the timing controller 131. In this second embodiment, the timing controller 131 changes the pulse width of the second gate output signal GOE2 as shown in FIG. 7 to change the even pulse width of the gate output signal GOE according to the position of the liquid crystal panel. It depends on the position of the panel 134. That is, the timing controller 131 makes the pulse width of the second gate output signal GOE2 corresponding to the first block BL1 of the liquid crystal panel 134 substantially equal to the first gate output signal GOE1, The timing controller 131 makes the pulse width of the second gate output signal GOE2 corresponding to the second block BL2 of the liquid crystal panel 134 1 to 1.2 times wider than that of the first gate output signal GOE1. do. The timing controller 131 further increases the pulse width of the second gate output signal GOE2 corresponding to the third block BL3 of the liquid crystal panel 134 by 1.2 to 1.5 times as compared to the first gate output signal GOE1. Widen.

As described above, the liquid crystal display and the driving method thereof according to the present invention invert the polarity of the data voltage to be supplied to the liquid crystal cell in units of two horizontal periods, and when the data voltages of the same polarity are output by the source output signal The pulse width of the even pulses of the gate output signal is longer than the odd pulses to control the charge amount of the gate, so that the liquid crystal cell to which the data of the odd horizontal line is supplied in the liquid crystal display device driven by the 2-dot inversion method The charging characteristic of the liquid crystal cell to which the data of the line is supplied can be made uniform. As a result, the liquid crystal display device and the driving method thereof according to the present invention can improve the display quality in the 2-dot inversion method.

Furthermore, the liquid crystal display and the driving method thereof according to the present invention can make the charging characteristics of all liquid crystal cells in the panel to which data is supplied in a 2-dot inversion method by varying the pulse width of the gate output signal according to the panel position. have.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, although the embodiment of the present invention has been described based on the two dot inversion method, N (where N is a positive integer of 2 or more) may also be applied to the dot inversion method. In addition, embodiments disclosed in the detailed description of the invention may be used in combination. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (31)

A liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; A control signal generator generating a source output signal and generating a gate output signal having a different pulse width in horizontal period units; A data driving circuit for inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line in response to the source output signal; And a gate driving circuit configured to supply a scan pulse to the gate line in response to the gate output signal. The method of claim 1, And the control signal generator further generates a polarity control signal indicating the polarity of the data voltage. The method of claim 2, The data driving circuit, Inverting the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal, and in response to the source output signal, the first data, the second data having the same polarity as the first data, the first and the first And second and fourth data having different polarities from the second data in sequence. The method of claim 3, wherein The liquid crystal panel, And a plurality of thin film transistors for supplying data from the data lines to the liquid crystal cells in response to the scan pulse. The method of claim 4, wherein The scan pulse, An odd scan pulse for supplying said first data voltage to a first liquid crystal cell and for supplying said third data voltage to a third liquid crystal cell disposed below said first liquid crystal cell; Supplying the second data voltage to a second liquid crystal cell disposed between the first liquid crystal cell and the third liquid crystal cell and supplying the fourth data voltage to a fourth liquid crystal cell disposed under the third liquid crystal cell A good scan pulse for the device; And the pulse width of the even scan pulse is narrower than that of the odd scan pulse. The method of claim 5, The gate output signal, An odd gate output signal for controlling the output of the odd scan pulse; An even gate output signal for controlling the output of the even scan pulse; And the pulse width of the even gate output signal is wider than that of the odd gate output signal. The method of claim 6, The control signal generator, A radix gate output signal in which pulses appear in units of two horizontal periods, an even gate output signal delayed by about one horizontal period relative to the first gate output signal, and a pulse appears in units of two horizontal periods, and the odd and even gate output signals A timing controller for generating a selection control signal for selection of the signals; And a multiplexer for alternately outputting the odd and even gate output signals in units of one horizontal period in response to the selection control signal. A liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; A control signal generator for generating a source output signal and generating a gate output signal having a different pulse width according to the position of the liquid crystal panel; A data driving circuit for inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line in response to the source output signal; And a gate driving circuit configured to supply a scan pulse to the gate line in response to the gate output signal. The method of claim 8, And the control signal generator further generates a polarity control signal indicating the polarity of the data voltage. The method of claim 8, The data driving circuit, Invert the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal, and in response to the source output signal, first data, second data having the same polarity as the first data, and the first and second signals. And third and fourth data having different polarities from the data are sequentially output. The method of claim 10, The liquid crystal panel, And a plurality of thin film transistors for supplying data from the data lines to the liquid crystal cells in response to the scan pulse. The method of claim 11, The scan pulse, An odd scan pulse for supplying said first data voltage to a first liquid crystal cell and for supplying said third data voltage to a third liquid crystal cell disposed below said first liquid crystal cell; Supplying the second data voltage to a second liquid crystal cell disposed between the first liquid crystal cell and the third liquid crystal cell and supplying the fourth data voltage to a fourth liquid crystal cell disposed under the third liquid crystal cell Liquid crystal display comprising an excellent scan pulse for. The method of claim 12, The gate output signal, An odd gate output signal for controlling the output of the odd scan pulse; An even gate output signal for controlling the output of the even scan pulse; And the pulse width of the even gate output signal varies depending on the position of the liquid crystal panel. The method of claim 13, The liquid crystal panel includes a first block close to the data driving circuit, a second block located farther from the data driving circuit than the first block, and a second block located farther from the data driving circuit than the second block. Includes three blocks; The control signal generator includes a gate output signal of a first block including a first odd pulse and a first even pulse having substantially the same pulse width, and a second even pulse having a wider pulse width than that of the first even pulse. A gate output signal of the third block including a gate output signal of the block and a third even pulse having a wider pulse width than the second even pulse; The gator driving circuit causes the data to be displayed on the first block to be charged in each liquid crystal cell in response to the gate output signal of the first block, and to the second block in response to the gate output signal of the second block. And data to be displayed on the third block in each liquid crystal cell in response to a gate output signal of the third block. The method of claim 14, The control signal generator, An odd gate output signal in which pulses appear in units of two horizontal periods, and an even gate output signal in which pulses having a different pulse width according to the block are delayed by one horizontal period compared to the odd gate output signal, A timing controller for generating a selection control signal for selecting the gate output signals; And a multiplexer configured to alternately output the first and second gate output signals in units of one horizontal period in response to the selection control signal. Generating a source output signal; Generating a gate output signal having a different pulse width in horizontal period units; Inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line of the liquid crystal panel in response to the source output signal; And supplying a scan pulse to a gate line of the liquid crystal panel in response to the gate output signal. The method of claim 16, And generating a polarity control signal indicative of the polarity of the data voltage. The method of claim 17, Invert the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal, and in response to the source output signal, first data, second data having the same polarity as the first data, and the first and second signals. And sequentially outputting third and fourth data having different polarities from the data. The method of claim 18, The liquid crystal panel, And a plurality of thin film transistors for supplying data from the data lines to the liquid crystal cells in response to the scan pulse. The method of claim 19, The scan pulse, An odd scan pulse for supplying said first data voltage to a first liquid crystal cell and for supplying said third data voltage to a third liquid crystal cell disposed below said first liquid crystal cell; Supplying the second data voltage to a second liquid crystal cell disposed between the first liquid crystal cell and the third liquid crystal cell and supplying the fourth data voltage to a fourth liquid crystal cell disposed under the third liquid crystal cell A good scan pulse for the device; And the pulse width of the even scan pulse is narrower than that of the odd scan pulse. The method of claim 20, The gate output signal, An odd gate output signal for controlling the output of the odd scan pulse; An even gate output signal for controlling the output of the even scan pulse; And the pulse width of the even gate output signal is wider than that of the odd gate output signal. The method of claim 21, A radix gate output signal in which pulses appear in units of two horizontal periods, an even gate output signal delayed by about one horizontal period compared to the radix gate output signal, and a pulse appears in units of two horizontal periods, Generating a selection control signal for selection; And outputting the odd and even gate output signals alternately in units of one horizontal period by using a multiplexer controlled according to the selection control signal. Generating a source output signal; Generating a gate output signal having a different pulse width according to the position of the liquid crystal panel; Inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line of the liquid crystal panel in response to the source output signal; And supplying a scan pulse to a gate line of the liquid crystal panel in response to the gate output signal. The method of claim 23, And generating a polarity control signal indicative of the polarity of the data voltage. The method of claim 23, Invert the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal, and in response to the source output signal, first data, second data having the same polarity as the first data, and the first and second signals. And sequentially outputting third and fourth data having different polarities from the data. The method of claim 25, The liquid crystal panel, And a plurality of thin film transistors for supplying data from the data lines to the liquid crystal cells in response to the scan pulse. The method of claim 26, The scan pulse, An odd scan pulse for supplying said first data voltage to a first liquid crystal cell and for supplying said third data voltage to a third liquid crystal cell disposed below said first liquid crystal cell; Supplying the second data voltage to a second liquid crystal cell disposed between the first liquid crystal cell and the third liquid crystal cell and supplying the fourth data voltage to a fourth liquid crystal cell disposed under the third liquid crystal cell Method for driving a liquid crystal display device comprising an excellent scan pulse for. The method of claim 27, The gate output signal, An odd gate output signal for controlling the output of the odd scan pulse; An even gate output signal for controlling the output of the even scan pulse; And a pulse width of the even gate output signal varies depending on a position of the liquid crystal panel. The method of claim 28, The liquid crystal panel includes a first block closer to the data driving circuit, a second block located farther from the data driving circuit than the first block, and a third block farther from the data driving circuit than the second block. Method of driving a liquid crystal display device comprising a. The method of claim 29, The generating of the gate output signal may include a gate output signal of a first block including a first odd pulse and a first even pulse having substantially the same pulse width, and a second even pulse having a wider pulse width than the first even pulse. Generating a gate output signal of the second block including a gate output signal of the third block including a third even pulse having a wider pulse width than the second even pulse; The supplying of the scan pulse to the gate line of the liquid crystal panel causes the data to be displayed in the first block to be filled in each liquid crystal cell in response to the gate output signal of the first block, and the gate of the second block. Data to be displayed in the second block is filled in each liquid crystal cell in response to an output signal, and data to be displayed in the third block is charged in each liquid crystal cell in response to a gate output signal of the third block. And driving the liquid crystal display device. The method of claim 30, An odd gate output signal in which pulses appear in units of two horizontal periods, an even gate output signal in which pulses having a different pulse width according to the block are delayed by about one horizontal period compared to the first gate output signal, Generating a selection control signal for selecting the gate output signals; And outputting the odd and even gate output signals alternately in units of one horizontal period by using a multiplexer controlled according to the selection control signal.

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