KR100920375B1 - Liquid crystal display and method for driving the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for improving display quality, comprising: a liquid crystal panel having a liquid crystal cell to which a positive voltage is applied and a liquid crystal cell to which a negative voltage is applied; According to at least one of a pulse width and a duty ratio of a source output signal instructing output of data according to a data driving circuit for supplying data, and a liquid crystal cell to which a positive voltage is applied and a liquid crystal cell to which a negative voltage is applied. And a source output control circuit for controlling.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND METHOD FOR DRIVING THE SAME}             

FIG. 1 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a one dot inversion scheme.

FIG. 2 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a two dot inversion scheme.

3 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a line inversion scheme.

4 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a column inversion scheme.

5 is a block diagram showing a conventional liquid crystal display device.

FIG. 6 is a waveform diagram illustrating a control signal generated by the liquid crystal display shown in FIG. 5 and a liquid crystal cell voltage according thereto.

FIG. 7 is an equivalent circuit diagram of a subpixel for explaining a parasitic capacitance variation and a feedthrough voltage ΔVp of a thin film transistor.

8 is a block diagram illustrating a liquid crystal display according to a first embodiment of the present invention.                 

FIG. 9 is a waveform diagram illustrating a source output signal generated from the timing controller shown in FIG. 8.

FIG. 10 is a circuit diagram illustrating the SOE conversion circuit shown in FIG. 8 in detail.

FIG. 11 is a circuit diagram illustrating in detail the data driving circuit shown in FIG. 8.

FIG. 12 is a circuit diagram illustrating the gate driving circuit of FIG. 8 in detail.

FIG. 13 is a waveform diagram illustrating a source output signal of the Fn−1 th frame and a source output signal of the Fn th frame generated from the SOE conversion circuit shown in FIG. 8.

FIG. 14A is a waveform diagram illustrating data output controlled by the source output signal of the Fn−1th frame shown in FIG. 13 and the voltage of the liquid crystal cell accordingly.

FIG. 14B is a waveform diagram illustrating data output controlled by the source output signal of the Fn-th frame shown in FIG. 13 and the voltage of the liquid crystal cell accordingly.

15 is a block diagram illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 16 is a waveform diagram illustrating a source output signal generated from the timing controller shown in FIG. 15.

FIG. 17 is a circuit diagram illustrating the GOE conversion circuit illustrated in FIG. 15 in detail.

FIG. 18 is a circuit diagram illustrating the data driving circuit shown in FIG. 15 in detail.

FIG. 19 is a circuit diagram illustrating the gate driving circuit shown in FIG. 15 in detail.

FIG. 20 is a waveform diagram illustrating a source output signal of the Fn−1 th frame and a source output signal of the Fn th frame generated from the GOE conversion circuit shown in FIG. 15.

FIG. 21A is a waveform diagram illustrating an output of a scan pulse controlled by a source output signal of the Fn−1 th frame shown in FIG. 20 and a voltage of a liquid crystal cell accordingly.

FIG. 21B is a waveform diagram illustrating an output of a scan pulse controlled by a source output signal of an Fn-th frame shown in FIG. 20 and a voltage of a liquid crystal cell accordingly.

<Description of Symbols for Main Parts of Drawings>

51,81,151: Timing controller 52,82,152: Data driving circuit

53,83,153 gate driving circuit 54,84,154 liquid crystal panel

85: SOE conversion circuit 110, 170: multiplexer

91,181: first latch 93,183: second latch

94,184: digital-to-analog converter 95,185: buffer

155: GOE conversion circuit

92,182: shift register of data driving circuit

1011 to 101n, 2011 to 200n: level shifter

102, 202: shift register of gate driving circuit

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof to improve display quality.                         

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. In an active matrix type liquid crystal display, switching elements are formed in each liquid crystal cell, which is advantageous for displaying a moving image. As the switching device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

The LCD is driven in an inversion manner to reduce flicker and afterimage by periodically inverting the polarity of data charged in the liquid crystal cell. The inversion method includes a line inversion method for inverting polarities of data between adjacent liquid crystal cells in a vertical line direction, a column inversion method for inverting polarities of data between adjacent liquid crystal cells in a horizontal line direction, a vertical line direction and a horizontal line direction. There is a dot inversion method of inverting the polarity of data between adjacent liquid crystal cells.

In the dot inversion scheme, as illustrated in FIG. 1, polarities of data supplied to adjacent liquid crystal cells in the vertical direction are opposite to each other, and polarities of data supplied to adjacent liquid crystal cells in the horizontal direction are opposite to each other. The polarity of the data is inverted every frame (Fn-1, Fn). The dot inversion method is most widely used in liquid crystal display devices because flicker is minimized in both the vertical and horizontal directions.

In the dot inversion scheme of FIG. 2, the polarity of data is inverted in units of two dots in the horizontal and vertical directions. The two-dot inversion method as shown in FIG. 2 has the advantage of lower power consumption than the one-dot inversion method as shown in FIG.

In the line inversion method, as shown in FIG. 3, polarities of data supplied to adjacent liquid crystal cells in the vertical direction are opposite to each other, whereas polarities of data supplied to adjacent liquid crystal cells in the horizontal direction are the same. The polarity of the data is inverted every frame (Fn-1, Fn).

In the column inversion scheme, as shown in FIG. 4, polarities of data supplied to adjacent liquid crystal cells in the horizontal direction are opposite to each other, whereas polarities of data supplied to adjacent liquid crystal cells in the vertical direction are the same. The polarity of the data is inverted every frame (Fn-1, Fn).

5 schematically shows a conventional liquid crystal display device.

Referring to FIG. 5, in the conventional liquid crystal display device, a liquid crystal panel 54 in which data lines D1 to Dm and gate lines G1 to Gn cross each other and a TFT for driving the liquid crystal cell Clc is formed at an intersection thereof. ), A data driving circuit 52 for supplying data to the data lines D1 to Dm of the liquid crystal panel 54, and a scan pulse for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 54. And a timing controller 51 for controlling the gate driving circuit 53 and the data driving circuit 52 and the gate driving circuit 53.

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 54 is formed such that the data lines D1 to Dm and the gate lines G1 to Gn are orthogonal to each other on the lower glass substrate. The TFTs formed at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn liquid crystal the data on the data lines D1 to Dm in response to a scan pulse from the gate lines G1 to Gn. It is supplied to the cell Clc. For this purpose, the gate electrodes of the TFTs are connected to the gate lines G1 to Gn, and the source electrodes are connected to the data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. The common voltage Vcom is supplied to the common electrode facing the pixel electrode.

The data driving circuit 52 stores a data line by line in response to a shift register for sampling a clock, a register for temporarily storing data, and a clock signal from the shift register, and simultaneously outputs one line of stored data. Latch, a digital / analog converter for selecting a positive / negative gamma voltage corresponding to the digital data value from the latch, and a data line to which analog data converted by the positive / negative gamma voltage is supplied (D1 to Dm) ), And a multiplexer for selecting) and an output buffer connected between the multiplexer and the data line. The data driving circuit 52 supplies data input from the timing controller 51 to the data lines D1 to Dm of the liquid crystal panel 54 under the control of the timing controller 51.

The gate driving circuit 53 includes a shift register for sequentially generating scan pulses, and a level shifter for shifting the voltage of the scan pulses to a level suitable for driving the liquid crystal cell Clc. The gate driving circuit 53 sequentially supplies scan pulses to the gate lines G1 to Gn under the control of the timing controller 51.

The timing controller 51 controls the gate control signal GDC and the data driving circuit 52 for controlling the gate driving circuit 53 by using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. The data control signal (DDC) includes a source start pulse (SSP), a source shift clock (SSC), a source output signal (SOE), and a polarity signal (POL). do. Here, the source output signal SOE is a signal indicating the output time of the data. The gate control signal GDC includes a gate shift clock GSC, a gate output enable GOE, a gate start pulse GSP, and the like. Here, the gate output signal GOE is a signal indicating the output calculation of the scan pulse.

6 illustrates a data pulse generated according to the source output signal POL and a scan pulse generated according to the gate output signal GOE and a voltage charged in the liquid crystal cell Clc.

Referring to FIG. 6, the source output signal SOE and the gate output signal GOE are generated in approximately one horizontal period period. The data voltage data is supplied to the data lines D1 to Dm whenever the source output signal SOE is generated in synchronization with the polling edge of the source output signal.

In an inversion method such as dot inversion or line inversion, the data voltage data alternates between positive and negative polarities as shown in the drawing.

The scan pulse SP is generated at a Vgh voltage set above the threshold voltage of the TFT in synchronization with the falling edge of the gate output signal GOE every scan period of the horizontal line.

The liquid crystal cell Clc charges the data voltage data by turning on the TFT during the scan period in which the scan pulse SP is generated, and maintains the charged voltage Vlc for one frame period.

However, in the conventional liquid crystal display device, the voltage charged in the parasitic capacitance Cgd of the TFT varies according to the liquid crystal cell Clc in the inversion method. In particular, as shown in the shaded portion in FIG. 6, the parasitic capacitance Cgd between the gate and the drain of the TFT is between the liquid crystal cell Clc charged with the positive voltage and the liquid crystal cell Clc charged with the negative voltage. The voltage that is charged varies greatly. For this reason, the conventional liquid crystal display device has a problem in that flicker is generated and luminance deviation is generated between lines and between cells. This will be described in detail with reference to FIGS. 7 and 1 and 2.

Referring to FIG. 7, each of the sub-pixels of the liquid crystal panel 54 includes a TFT, a liquid crystal cell Clc, and a storage capacitor Cst in the cell region between the data line D1 and the gate line G1 that cross each other. It includes. Parasitic capacitance Cgd exists between the gate electrode of the TFT connected to the gate line G1 and the drain electrode of the TFT connected to the pixel electrode of the liquid crystal cell Clc.

Assuming that the data voltage charge rate of the liquid crystal cell Clc is 100%, the voltage of the liquid crystal cell Clc is the voltage on the data line D1 during the period in which the gate voltage of the TFT maintains Vgh. As the gate voltage of the TFT changes from Vgh to Vgl, the TFT is turned off and turned off. At this moment, the voltage Vlc of the liquid crystal cell Clc changes as shown in Equations 1 and 2 below because of the parasitic capacitance Cgd of the TFT.

Vlc (t) = V _D -ΔVp

ΔVp is referred to as a feed-through voltage. This ΔVp lowers the voltage Vlc of the liquid crystal cell Clc when the voltage applied to the liquid crystal cell Clc is positive as shown in Equation 1, while the voltage applied to the liquid crystal cell Clc is negative. The voltage Vlc of the liquid crystal cell Clc is increased. Due to the difference of ΔVp, a luminance difference is generated between the liquid crystal cell Clc charged with the positive voltage and the liquid crystal cell Clc charged with the negative voltage, thereby causing a flicker phenomenon. As can be seen from Equation 1, ΔVp is changed by the parasitic capacitance Cgd of the TFT.

Accordingly, it is an object of the present invention to provide a liquid crystal display device and a driving method thereof in which display quality is improved by suppressing fluctuations in parasitic capacitance of a TFT.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention is a liquid crystal panel having a liquid crystal cell to which a positive voltage is applied and a liquid crystal cell to which a negative voltage is applied, and a liquid crystal panel connected to a data line of the liquid crystal panel. At least one of a data driving circuit for supplying data to the panel, a pulse width and a duty ratio of a source output signal instructing output of data according to a liquid crystal cell to which a positive voltage is applied and a liquid crystal cell to which a negative voltage is applied It is provided with a source output control circuit for controlling differently.

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The source output control circuit may control the pulse width of the source output signal to be wider in the liquid crystal cell to which the negative voltage is applied than to the liquid crystal cell to which the positive voltage is applied.

The source output control circuit may include a signal generator for generating a first source output signal having a first pulse width and a second source output signal having a second pulse width, and alternately between the first source output signal and the second source output signal. And a switch circuit for selecting and supplying the selected source output signal to the data driving circuit.

The source output control circuit alternately selects the first source output signal and the second source output signal at approximately one horizontal period period.

The signal generator is a timing controller for controlling the data driving circuit and supplying data to the data driving circuit.

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According to an exemplary embodiment of the present invention, a driving method of a liquid crystal display device includes a pulse width of a source output signal instructing output of data supplied to a liquid crystal panel according to a liquid crystal cell to which a positive voltage is applied and a liquid crystal cell to which a negative voltage is applied. And controlling at least one of the duty ratios differently, and supplying a source output signal to the liquid crystal panel.

The controlling of the source output signal may control the pulse width of the source output signal to be wider in the liquid crystal cell to which the negative voltage is applied than to the liquid crystal cell to which the positive voltage is applied.

The controlling of the source output signal may include generating a first source output signal having a first pulse width and a second source output signal having a second pulse width, and generating the first source output signal and the first source output signal at approximately one horizontal period. Two source output signals are alternately selected and the selected source output signals are supplied to a data driving circuit connected to the data lines of the liquid crystal panel.

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Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 21.

Referring to FIG. 8, the liquid crystal display according to the first exemplary embodiment of the present invention transmits the first source output signal SOE1 and the second source output signal SOE2 having different pulse widths to the data driving circuit 82. Data is supplied to the data lines D1 to Dm of the liquid crystal panel 84 in alternating response to the SOE conversion circuit 85 for supplying and the first source output signal SOE1 and the second source output signal SOE2. A data driving circuit 82 for supplying, a gate driving circuit 83 for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 84, a data driving circuit 82 and a gate driving circuit ( 83 and a timing controller 81 for controlling the SOE conversion circuit 85.

The liquid crystal panel 84 is substantially the same as that shown in FIG. Reference numeral 'Cst' denotes a storage capacitor. The storage capacitor Cst may be formed between the liquid crystal cell Clc connected to the k th gate line (where k is a positive integer between 1 and n) and the k-1 th front gate line, and the k th It may be formed between the liquid crystal cell Clc connected to the gate line and a separate common line.

The SOE conversion circuit 85 alternately selects the first source output signal SOE1 and the second source output signal SOE2 input from the timing controller 81 at approximately one horizontal period period, and selects the selected source output signals SOE1, SOE2. ) Is supplied to the data driving circuit 82.

The data driving circuit 82 receives the digital data RGB input from the timing controller 81 in response to the control signals DDC (SOE1 and SOE2) input from the timing controller 81 and the SOE conversion circuit 85. The data lines D1 to Dm of the panel 84 are supplied.

The gate driving circuit 83 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signal GDC from the timing controller 81.

The timing controller 81 controls the gate control signal GDC and the data driving circuit 82 to control the gate driving circuit 83 by using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. As shown in FIG. 11, the data control signal DDC includes a bar source start pulse SSP, a source shift clock SSC, a first source output signal SOE1, a first source output signal SOE1, and a polarity signal POL. ), And the like. The gate control signal GDC includes a bar gate shift clock GSC, a gate output signal GOE, a gate start pulse GSP and the like, which can be seen in FIG. 12.

The timing controller 81 generates the first source output signal SOE1 and the second source output signal SOE2 having different pulse widths and duty ratios as shown in FIG. 9 by varying the number of coefficients of the clock CLK. The first source output signal SOE1 and the second source output signal SOE2 have different supply periods of voltages supplied to the liquid crystal panel 84, so that the liquid crystal cell Clc and the negative voltage supplied with the positive voltage are different. It serves to reduce the voltage difference caused by the TFT parasitic capacitance in the supplied liquid crystal cell (Clc).

9 shows the first and second source output signals SOE1 and SOE2 generated from the timing controller 81.

Referring to FIG. 9, the first source output signal SOE1 is a control signal for outputting a positive voltage from the data driving circuit 82 and its pulse width is set to W1. The second source output signal SOE2 is a control signal for outputting the negative voltage from the data driving circuit 82 and is set to W2 whose pulse width is wider than that W1 of the first source output signal SOE1. .

10 shows the SOE conversion circuit 85 in detail.

Referring to FIG. 10, the SOE conversion circuit 85 may select one of the first source output signal SOE1 and the second source output signal SOE2 in response to the switch control signal MUXC1 from the timing controller 81. And a multiplexer 110 for selection.

The switch control signal MUXC1 has two logic values, high logic and low logic, and the logic values are inverted by approximately one horizontal period.

The MUX 110 selects the first source output signal SOE1 in response to the high logic value of the switch control signal MUXC1 among the first and second source output signals SOE1 and SOE2 input to its input terminal. The second source output signal SOE2 is selected in response to the low logic value of the switch control signal MUXC1.

In addition, the SOE conversion circuit 85 inverts the output signals of the first source output signal SOE1 and the second source output signal SOE1 whenever the frame is changed in response to the switch control signal MUXC1.

11 schematically shows the data driving circuit 82.

Referring to FIG. 11, the data driving circuit 82 may include a plurality of integrated circuits IC, each integrated circuit having a shift register 92 and a first latch (sub) which are cascaded between an input line and a data line. 91, a second latch 93, a digital-to-analog converter (hereinafter referred to as "DAC") 94, and a buffer 95.

The shift register 92 shifts the source start pulse SSP from the timing controller 81 in accordance with the source shift clock signal SSC to generate a sampling signal. In addition, the shift register 92 shifts the source start pulse SSP to transfer a carry signal CAR to the next stage shift register 92.

The first latch 91 samples and stores digital data RGB according to a sampling signal input from the shift register 92, and supplies the stored digital data to the second latch 93.

The second latch 93 latches the data EFD and RGB input from the first latch 91, and then a second latch in another integrated circuit in response to the source output signal SOE from the timing controller 60. The digital data of one horizontal line latched together with 93 is simultaneously output. The second latch 93 outputs the stored data in response to the first source output signal SOE1 or the second source output signal SOE2 from the SOE conversion circuit 85.

The DAC 94 converts the digital data RGB from the second latch 93 according to the polarity signal POL from the timing controller 81 to the positive analog gamma voltage VPG or the negative analog gamma voltage VNG. Convert to In addition, the voltage generated from the DAC 94 controls the polarity of the data in accordance with inversion schemes such as dot inversion, N dot inversion, line inversion, and column inversion scheme in response to the polar line signal POL.

The buffer 95 outputs the analog gamma voltages VPG and VNG input from the DAC 94 to the data lines D1 to Dm without signal attenuation.

In Fig. 11, reference numeral 'R' denotes a line resistance between the output terminal of the data driving circuit 82 and the data lines D1 to Dm.

12 shows the gate driving circuit 83 in detail.

Referring to FIG. 12, the gate driving circuit 83 includes a shift register 102 having a plurality of stages 1001 to 100n, and level shifters 1011 to 101n input to the shift register 102.                     

The first stage 1001 of the shift register 102 generates a scan pulse in response to the gate start pulse GSP and the gate shift clock GSC from the timing controller 81. The second to nth stages 1002 to 100n receive a voltage on the front gate lines G1 to Gn-1 as gate start pulses and sequentially generate scan pulses in response to the signal and the gate shift clock GSC. do.

The level shifters 1011 to 101n are respectively connected to the output terminals of the shift register 102 to convert the swing width of each output signal of the shift register 102 into a swing width for driving the liquid crystal cell Clc. The scan pulses output from the level shifters 1011 to 101n have two voltage levels, Vgh and Vgl. A buffer may be provided between the level shifters 1011 to 101n and the gate lines G1 to Gn.

The source output signal of the Fn−1th frame and the source output signal of the Fn−th frame output from the SOE converter 85 are reversed as shown in FIG. 13. As can be seen from FIG. 13, the source output signal output from the SOE converter 85 is periodically changed in units of one horizontal period depending on the polarity of the data voltage supplied to the liquid crystal cell Clc. When the source output signal is as shown in FIG. 13, the voltage charged in the liquid crystal cell Clc is as shown in FIGS. 14A and 14B.

14A and 14B, in the liquid crystal display according to the first exemplary embodiment of the present invention, the parasitic capacitance of the TFT is between the liquid crystal cell Clc charged with the positive voltage and the liquid crystal cell Clc charged with the negative voltage. The difference between the voltage Vgd charged in Cgd becomes small. Therefore, assuming that the same data, the amount of charge of the liquid crystal cell Clc charged with the positive voltage and the liquid crystal cell Clc charged with the negative voltage is almost the same. This is because the voltage Vgd charged in the parasitic capacitance Cgd becomes larger than the output time of the positive voltage by the source output signal SOE (Fn-1, Fn) output from the SOE conversion circuit 85. This is because the output time of the polarity voltage is short.

15 to 21 illustrate a liquid crystal display and a driving method thereof according to the second embodiment of the present invention.

Referring to FIG. 15, the liquid crystal display according to the second exemplary embodiment of the present invention transmits the first gate output signal GOE1 and the second gate output signal GOE2 having different pulse widths to the gate driving circuit 153. A GOE conversion circuit 155 for supplying, a data driving circuit 152 for supplying data to the data lines D1 to Dm of the liquid crystal panel 154, a first gate output signal GOE1 and a second gate A gate driving circuit 153 for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 154 in response to the output signal GOE2, and a data driving circuit 152 and a gate driving circuit ( 153 and a timing controller 151 for controlling the GOE conversion circuit 155.

The liquid crystal panel 154 is substantially the same as that shown in FIGS. 5 and 8.

The GOE conversion circuit 155 alternately selects the first gate output signal GOE1 and the second gate output signal GOE2 input from the timing controller 151 at approximately one horizontal period period, and selects the selected gate output signals GOE1 and GOE2. ) Is supplied to the gate driving circuit 153.

The data driving circuit 152 responds to the digital data RGB input from the timing controller 151 in response to the control signal DDC input from the timing controller 151. Dm).

The gate driving circuit 153 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signals GDC (GOE1 and GOE2) from the timing controller 151 and the GOE conversion circuit 155. .

The timing controller 151 controls the gate control signal GDC and the data driving circuit 152 for controlling the gate driving circuit 153 by using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. The data control signal DDC includes a bar source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity signal POL, and the like shown in FIG. 18. The gate control signal GDC includes a bar gate shift clock GSC, a first gate output signal GOE1, a second gate output signal GOE2, and a gate start pulse GSP as shown in FIG. 19.

The timing controller 151 generates the first gate output signal GOE1 and the second gate output signal GOE2 having different pulse widths and duty ratios as shown in FIG. 16 by varying the number of clocks CLK. The first gate output signal GOE1 and the second gate output signal GOE2 have different supply periods of the voltages supplied to the liquid crystal panel 154 so that the liquid crystal cell Clc and the negative voltage supplied with the positive voltage are different. It serves to reduce the voltage difference caused by the TFT parasitic capacitance in the supplied liquid crystal cell (Clc).

16 illustrates the first and second source output signals SOE1 and SOE2 generated from the timing controller 151.                     

Referring to FIG. 16, the first gate output signal GOE1 is a control signal for controlling the output time of the scan pulse SP output from the gate driving circuit 153 and its pulse width is set to W1. The second gate output signal GOE2 is a control signal for controlling the output time of the scan pulse SP relatively short compared to the first gate output signal GOE2, and the pulse width thereof is equal to that of the first gate output signal GOE1. It is set to W2 which is wider than W1.

17 shows the GOE conversion circuit 155 in detail.

Referring to FIG. 17, the GOE conversion circuit 155 may output one of the first gate output signal GOE1 and the second gate output signal GOE2 in response to the switch control signal MUXC2 from the timing controller 151. A MUX 170 is provided for selection.

The switch control signal MUXC2 has two logic values, high logic and low logic, and the logic values are inverted by approximately one horizontal period.

The MUX 170 selects the first gate output signal GOE1 in response to the high logic value of the switch control signal MUXC2 among the first and second gate output signals GOE1 and GOE2 input to its input terminal. The second gate output signal GOE2 is selected in response to the low logic value of the switch control signal MUXC2.

In addition, the GOE conversion circuit 155 inverts the output signals of the first gate output signal GOE1 and the second gate output signal GOE1 whenever the frame changes in response to the switch control signal MUXC2.

18 schematically shows the data driving circuit 152.

Referring to FIG. 18, the data driving circuit 152 includes a plurality of integrated circuits (ICs), each integrated circuit including a shift register 182 and a first latch that are cascaded between an input line and a data line. 181, a second latch 183, a DAC 184, and a buffer 185.

The data driving circuit 152 has a configuration other than that except that the second latch 183 outputs the stored data in response to the source output signal SOE generated with a constant pulse width and approximately one horizontal period. It is substantially the same as that shown in FIG.

19 shows the gate driving circuit 153 in detail.

Referring to FIG. 19, the gate driving circuit 153 includes a plurality of stages 1001 to 100n and adjusts the output of scan pulses according to the first and second gate output signals GOE1 and GOE2. And level shifters 2011 to 201n input to the shift register 202.

The first stage 2001 of the shift register 202 generates a scan pulse in response to the gate start pulse GSP and the gate shift clock GSC from the timing controller 151. The second to nth stages 2002 to 200n receive a voltage on the front gate lines G1 to Gn-1 as gate start pulses and sequentially generate scan pulses in response to the signal and the gate shift clock GSC. do. The width of the scan pulse output from the shift register 202 is adjusted according to the first and second gate output signals GOE1 and GOE2. For example, the width of the scan pulse becomes relatively narrower when the second gate output signal GOE2 is input to the shift register 202 than when the first gate output signal GOE1 is input to the shift register 202.                     

The level shifters 2011 to 201n are respectively connected to the output terminals of the shift register 202 to convert the swing width of each output signal of the shift register 202 into a swing width for driving the liquid crystal cell Clc. The scan pulses output from the level shifters 2011 to 201n have two voltage levels, Vgh and Vgl. A buffer may be provided between the level shifters 2011 to 201n and the gate lines G1 to Gn.

The gate output signal of the Fn−1th frame and the gate output signal of the Fn−th frame output from the GOE converter 155 are reversed as shown in FIG. 20. As can be seen in FIG. 20, the gate output signal output from the GOE converter 155 is periodically changed in approximately one horizontal period according to the polarity of the data voltage supplied to the liquid crystal cell Clc. When the gate output signal is as shown in FIG. 20, the voltage charged in the liquid crystal cell Clc is as shown in FIGS. 21A and 21B.

21A and 21B, the liquid crystal display according to the second exemplary embodiment of the present invention has a parasitic capacitance of a TFT between a liquid crystal cell Clc charged with a positive voltage and a liquid crystal cell Clc charged with a negative voltage. The difference between the voltage Vgd charged in Cgd becomes small. Therefore, assuming that the same data, the amount of charge of the liquid crystal cell Clc charged with the positive voltage and the liquid crystal cell Clc charged with the negative voltage is almost the same. This is because the voltage Vgd charged in the parasitic capacitance Cgd becomes larger than the output time of the positive voltage by the gate output signal GOE (Fn-1, Fn) output from the GOE conversion circuit 155. This is because the output time of the polarity voltage is short.

As described above, the liquid crystal display and the driving method thereof according to the present invention control the source output signal or the gate output signal differently in the liquid crystal cell in which the positive voltage is charged and the liquid crystal cell in which the negative voltage is charged. As a result, the liquid crystal display device and the driving method thereof according to the present invention improve the display quality by reducing the flicker by suppressing the variation of the parasitic capacitance of the TFT in the liquid crystal cell charged with the positive voltage and the liquid crystal cell charged with the negative voltage. It becomes possible.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, although the embodiment of the present invention has been described based on the dot inversion method, N (where N is a positive integer of 2 or more) may be applied to the dot inversion method, the line inversion method, the column inversion method, or the like. In addition, embodiments disclosed in the detailed description of the invention may be used in combination. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (20)

delete delete delete delete A liquid crystal panel having a liquid crystal cell to which a positive voltage is applied and a liquid crystal cell to which a negative voltage is applied; A data driving circuit connected to a data line of the liquid crystal panel to supply data to the liquid crystal panel; And A source output control circuit for differently controlling at least one of a pulse width and a duty ratio of a source output signal indicating the output of the data according to the liquid crystal cell to which the positive voltage is applied and the liquid crystal cell to which the negative voltage is applied Liquid crystal display comprising a. The method of claim 5, wherein The source output control circuit, And controlling the pulse width of the source output signal to be wider in a liquid crystal cell to which the negative voltage is applied than to a liquid crystal cell to which the positive voltage is applied. The method of claim 5, wherein The source output control circuit, A signal generator for generating a first source output signal having a first pulse width and a second source output signal having a second pulse width different from the first pulse width; And a switch circuit for alternately selecting the first source output signal and the second source output signal and for supplying the selected source output signal to the data driving circuit. The method of claim 7, wherein The source output control circuit, And the first source output signal and the second source output signal are alternately selected in one horizontal period. The method of claim 7, wherein And the signal generator is a timing controller for controlling the data driving circuit and supplying the data to the data driving circuit. A liquid crystal panel having a liquid crystal cell to which a positive voltage is applied and a liquid crystal cell to which a negative voltage is applied; A gate driving circuit connected to a scan line of the liquid crystal panel to supply scan pulses to the liquid crystal panel; And Gate output control for differently controlling at least one of a pulse width and a duty ratio of a gate output signal indicating the output of the scan pulse according to the liquid crystal cell to which the positive voltage is applied and the liquid crystal cell to which the negative voltage is applied With a circuit, The gate output control circuit, A signal generator for generating a first gate output signal having a first pulse width and a second gate output signal having a second pulse width different from the first pulse width; And And a switch circuit for alternately selecting the first gate output signal and the second gate output signal and for supplying the selected gate output signal to the gate driving circuit. The method of claim 10, The gate output control circuit, And controlling the pulse width of the gate output signal to be wider in a liquid crystal cell to which the negative voltage is applied than to a liquid crystal cell to which the positive voltage is applied. delete The method of claim 10, The gate output control circuit, And the first gate output signal and the second gate output signal are alternately selected at one horizontal period. The method of claim 10, And the signal generator is a timing controller for controlling the gate driving circuit. Controlling at least one of a pulse width and a duty ratio of a source output signal instructing output of data supplied to the liquid crystal panel according to the liquid crystal cell to which the positive voltage is applied and the liquid crystal cell to which the negative voltage is applied; And And supplying the source output signal to the liquid crystal panel. The method of claim 15, Controlling the source output signal, And controlling the pulse width of the source output signal to be wider in a liquid crystal cell to which the negative voltage is applied than to a liquid crystal cell to which the positive voltage is applied. The method of claim 15, Controlling the source output signal, Generating a first source output signal having a first pulse width and a second source output signal having a second pulse width different from the first pulse width; Alternately selecting the first source output signal and the second source output signal at one horizontal period, and supplying the selected source output signal to a data driving circuit connected to a data line of the liquid crystal panel. Driving method of liquid crystal display device. delete delete delete

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