TWI417865B - A method for eliminating bright lines and dark lines of a crystal liquid display panel - Google Patents

Description

Method for eliminating bright and dark lines of liquid crystal display panel

The invention relates to a method for eliminating bright and dark lines of a liquid crystal display panel, in particular to providing different width output enable (OE) signals for different blocks of liquid crystal display panels to control the liquid crystal display panel. The charging time of each block is equal to achieve the method of eliminating the bright and dark lines.

Liquid crystal display (LCD) has been widely used in computer LCD screens and LCD TVs in recent years due to its low power consumption, light weight, high resolution, high color saturation and long life. On electronic products that are closely related to life.

Please refer to FIG. 1A for a schematic diagram showing the structure of a liquid crystal display panel of a conventional thin film transistor liquid crystal display (TFT-LCD). A timing controller 101 passes through a plurality of Flexible Printed Circuits (FPC) 103 and a plurality of source drivers (S/D) 107 and gate drivers (Gate Driver, G) on the glass substrate 105. /D) 109 electrical connection. An active matrix area 111 includes a plurality of horizontal scanning lines 113, a vertical data line 115, and a plurality of pixels (not shown) formed by the scanning lines 113 and the data lines 115, and A thin film transistor structure is included in each pixel. The gate of each thin film transistor structure is electrically connected to the scan line 113, the drain is electrically connected to the data line 115 in the vertical direction, and the source is electrically connected to the pixel electrode. Therefore, the gates of adjacent thin film transistors on the same scan line are connected to each other, that is, each scan line can be regarded as an RC equivalent circuit, as shown in FIG.

The gate driver 109 has a plurality of output channels, and each of the output channels has the same driving capability. However, the traces 117 between the gate driver 109 and the active matrix region 111 are limited by the space, that is, the trace path for the middle portion is shorter, and the trace path for the upper and lower sides is longer. Thus, the equivalent RC value of each scan line is not exactly the same. In the liquid crystal display panel, the switching state of the thin film transistor on the scanning line 113 is driven by the positive and negative voltages applied by the gate driver 109. Therefore, referring to the first C diagram, the gate driver 109 is shown to have The waveform of the gate output signal when the differential trace path 117 transmits the gate output signal to the active matrix region 111 represents the charging time of the pixel electrode. In the first C diagram, the active matrix area 111 can be roughly divided into upper, middle, and lower blocks, which are the first block 1, the second block 2, and the third block 3, respectively, and are first. It can be seen from the figure C that the waveforms of the gate output signals of the first block 1 and the third block 3 on the upper and lower sides are longer because the path of the trace 117 is longer to make the first block 1 and the third block 3 The signal waveform of the scan line exhibits a distorted condition; and the waveform of the gate output signal of the second block 2 in the middle portion is shorter for the first block 1 and the third block 3 because the path of the trace 117 Therefore, the signal waveform of the scan line in the second block 2 is closer to the ideal square wave. Thus, the charging time of the pixels of the first block 1 and the third block 3 on the upper and lower sides is different from the charging time of the pixels of the second block 2 in the central portion, and the charging ability of the pixels is not uniform. In this case, the liquid crystal display panel may exhibit defects of bright and dark lines when displayed.

The above-mentioned display defect phenomenon is mainly caused by the narrow space between the gate driver 109 and the active matrix region 111, so that the trace 117 disposed therein is restricted to be designed as a fan-shaped structure, and thus As a result, the impedance between the traces 117 is not uniform, which causes the charging of the pixels to be uneven, so that the liquid crystal display panel may exhibit display defects such as bright and dark lines when displayed. Conventionally, in order to solve the above problems, by changing the structure of the traces, please refer to the second figure, which shows a method of conventionally eliminating pixel charging unevenness caused by the sector structure of the traces. Among them, the middle portion of the trace 119 is designed as a fold line structure, so that the length of the trace of the middle portion can be increased and the resistance value can be increased. The design of the trace is due to the long path of the traces on the upper and lower sides, so that the resistance of the traces on the upper and lower sides is greater than the resistance of the traces in the middle portion, and the trace 119 in the middle portion is formed by the fold line structure. Increasing the length allows the resistance value to be equal to the resistance of the upper and lower traces, thereby charging the pixels in the first block 1, the second block 2, and the third block 3 of the active matrix region 111. If the situation is equal, the problem of display defects such as bright and dark lines due to uneven charging of the pixels can be solved.

However, the above design has a problem in that the method of solving the bright and dark lines of the liquid crystal display panel caused by the unevenness of the trace resistance by the wiring line 119 of the middle portion in a fold line structure. These problems include that since the space of the gate driver 109 to the active matrix region 111 is relatively narrow, and the traces 117 are formed on the glass substrate 105 by the lithography process, when designing the structures of the traces 117, Will cause the structure of not all traces to be adjusted. Moreover, too many bends in the design of the routing structure can easily cause serious distortion of the signal, which affects the quality of the display screen. In addition, if the bending region of the fold line structure of the trace 119 in the middle portion is larger than ninety degrees, the phenomenon of electrolytic corrosion is more likely to occur, thereby causing the liquid crystal display to fail to operate normally.

Therefore, there is a need for a structure that can eliminate the display line 117 between the gate driver 109 and the active matrix region 111, thereby effectively eliminating display defects such as bright and dark lines caused by uneven resistance of the traces. The method.

One of the objects of the present invention is to solve the problem of bright and dark lines of a liquid crystal display panel caused by a difference in resistance caused by a space limitation of a trace from a gate driver to an active matrix region.

Another object of the present invention is to effectively improve the display brightness unevenness of the liquid crystal display panel due to the difference in the resistance of the traces without changing the hardware structure.

In order to achieve the above object, the present invention provides a method for eliminating a bright and dark line of a liquid crystal display panel, the method comprising: providing an output enable (OE) signal to a gate driver by using a timing controller, wherein the output The enable signal includes at least a first pulse width and at least a second pulse width, and the second pulse width is greater than the first pulse width. The waveform of the gate output signal will be defined by the first pulse width and the second pulse width described above. For example, the gate driver transmits a first gate output signal to the first block of the liquid crystal display panel, wherein the first gate output signal is defined by the first pulse width; and further, the gate driver transmits a second gate output signal to a second block of the liquid crystal display panel, wherein the second gate output signal is defined by a second pulse width; and the gate driver transmits a third gate output signal to the liquid crystal a third block of the display panel, wherein the third gate output signal is defined by a first pulse width; based on a first gate output signal, a pulse width of the third gate output signal, and a second gate The pulse width of the polar output signal is different, so that the charging time of the pixels of the first block, the second block, and the third block of the liquid crystal display panel is equal. In this way, it is possible to eliminate display defects such as bright and dark lines due to insufficient charging of the pixels of the liquid crystal display panel without modifying the hardware.

The present invention further provides a method for eliminating a bright and dark line of a liquid crystal display panel, the method comprising: providing an output enable signal to a gate driver by a timing controller, wherein the output enable signal comprises a plurality of pulse waves Width; and a plurality of gate output signals are respectively transmitted to the plurality of blocks of the liquid crystal display panel by the gate driver, wherein the plurality of gate output signals are defined by the plurality of pulse widths; The gate output signals are such that the charging times of the pixels of the plurality of blocks are equal to achieve the effect of eliminating display defects such as bright and dark lines.

In some embodiments of the present invention, the timing controller includes a signal control IC and a memory; and the plurality of pulse width (or first pulse width and second pulse width) commands are temporarily stored. The output enable signal is generated in the memory by providing the signal control IC. In addition, the timing controller further provides a gate clock signal to the gate driver, and the plurality of gate output signals (or the first gate output signal, the second gate output signal, and the third gate) The output signal is controlled by this gate clock signal.

In this way, due to the uneven resistance of the traces between the gate driver and the active matrix region, the display defects such as bright and dark lines caused by uneven pixel charging capability in the active matrix region can be achieved by the method provided by the present invention. The charging time of each pixel in the active matrix area is equal to effectively eliminate display defects such as bright and dark lines of the liquid crystal display panel during display.

The advantages of the present invention will be apparent from the following description of the preferred embodiments and the accompanying claims.

The present invention will be described in detail with reference to the preferred embodiments and the accompanying claims Therefore, the invention may be embodied in other embodiments in addition to the preferred embodiments described herein.

Details of the invention will now be described, including embodiments of the invention. The reference numerals are used to identify the same or functionally similar elements, and the main features of the embodiments are described in a highly simplified schematic manner. In addition, the drawings do not depict each feature of the actual embodiments, and the depicted figures are in relative dimensions and not drawn to scale.

The invention discloses a method for eliminating the bright and dark lines of the liquid crystal display panel, which uses the signal control method to change the gate output signal so that the charging time of each pixel in the active matrix region of the liquid crystal display panel is equal to eliminate the gate The difference in the charging capacity of the thin film transistor caused by the unevenness of the trace line between the polar driver and the active matrix region causes the liquid crystal display panel to exhibit display defects such as bright and dark lines during display.

Please refer to the third figure, which is a schematic diagram showing the flow of the method for eliminating the bright and dark lines of the liquid crystal display panel of the present invention, and the control signal transmission diagram of the liquid crystal display panel shown in the fourth figure is shown in FIG. 5A to FIG. The schematic diagram of the timing control method is described.

First, referring to step 301, an output enable (OE) signal is provided to a gate driver by using a timing controller, wherein the output enable signal includes a first pulse width and a second pulse width. And the first pulse width is less than the second pulse width; then, referring to step 303, the first gate output signal is transmitted to the first block of the liquid crystal display panel by the gate driver, wherein the first gate The pulse width of the output signal is defined by the first pulse width of the output enable signal; in step 305, the second gate output signal is transmitted to the second block of the liquid crystal display panel by the gate driver, wherein the second gate The pulse width of the polar output signal is defined by the second pulse width of the output enable signal; and in step 307, the third gate output signal is transmitted to the third block of the liquid crystal display panel by the gate driver, wherein The pulse width of the three-gate output signal is defined by the first pulse width of the output enable signal.

Referring to the schematic diagram of the control signal transmission of the liquid crystal display panel shown in the fourth figure, the timing controller 101 can include a signal control IC 11 and a memory 13, wherein the timing controller 101 controls the timing of the IC 11 by the signal. The control signal is transmitted to the source driver 107 and the gate driver 109, and the memory 13 is used to store the operation mode of the signal control IC 11, that is, the operation mode of the signal control IC 11 is stored in the memory. In the body 13, after the liquid crystal display panel is driven, the related commands are read by the signal control IC 11 in the memory 13 and the output of the timing control signal is executed according to the relevant instructions. Here, the signal control IC 11 is included as an Application-Specific IC (ASIC), and the memory 13 may include non-volatile memory such as flash memory (FLASH) or electronic Electrically Erasable Programmable Read-Only Memory (EEPROM), but is not limited thereto. The signal control IC 11 in the timing controller 101 outputs a latch pulse (LP) signal to the source driver 103 according to the relevant instruction stored in the memory 13, and the source drivers 103 receive the signal. After latching the pulse signal (LP), each of the pixel electrodes in the active array region 111 is driven through a plurality of data lines 115 (as shown in FIG. A). In addition, the signal control IC 11 in the timing controller 101 also outputs a gate clock signal (CLKV) and an output enable signal (OE) to the gate driver 109. The gate driver 109 receives the gate clock. The signal (CLKV) and the output enable signal (OE) are then driven through a plurality of scan lines 113 (as shown in FIG. A) to drive the switching states of the thin film transistors (TFTs) in the active array region 111.

The driving method of the liquid crystal display panel is described by a schematic diagram of the timing control method shown in FIG. The gate clock signal (CLKV) uses a square wave signal as an embodiment for controlling the driving state of the scanning line 113 (shown in FIG. A) in the active matrix region 111, and the signal control IC 11 borrows The gate clock signal (CLKV) is sequentially transmitted from the shift register (not shown) to the gate driver 109, and the first gate clock signal (CLKV) is received at the gate driver 109. When the rising edge of the square wave, the first scanning line is driven, and when the gate driver 109 receives the rising edge of the next gate pulse signal (CLKV) square wave, it will drive the second line. Scan lines, and so on. The latch pulse signal (LP) outputted to the source driver 107 also takes a signal in the form of a square wave as an embodiment. When the latch pulse (LP) is in a high level state, it is in the active array region 111. The pixel electrode will be driven. As can be seen in Figure 5A, the gate clock signal (CLKV) is aligned with the rising edge of the latch pulse signal (LP), indicating that the signal control IC 11 is driven by the first gate clock signal (CLKV). When the thin film transistor (TFT) of the first scanning line 113 is turned on, the liquid crystal display panel is driven by opening the pixel electrode through the data line 115 by the latch pulse signal (LP).

The output enable signal (OE) is also the control signal outputted from the signal control IC 11 in the timing controller 101 to the gate driver 109, and the signal control IC 11 outputs the enable signal (OE) when the liquid crystal display panel is activated. Outputted to the gate driver 109, wherein the output enable signal (OE) related command is also stored in the memory 13, and when the liquid crystal display panel is activated, the signal control IC 11 reads the correlation The instructions are output to the gate driver 109. After the output enable signal (OE) is output to the gate driver 109, when the gate driver 109 receives the output enable signal (OE) as a high level, the output of the gate output signal is maintained. Low level. Traditionally, this output enable signal (OE) is mainly used to prevent each thin film transistor on the scan line from being turned on at the same time when the gate pulse signal (CLKV) is delayed during the transfer. And the phenomenon of re-writing caused by it.

In the fourth figure, the gate output signal of the embodiment is roughly divided into a first gate output signal (G _block1 ) and a middle portion in the first block 1 corresponding to the upper portion of the active matrix region 111. second gate output signal of the block 2 bis (G _block2) and a third portion of the lower block 3 in the output signal of the third gate (G _block3). Please then refer to FIG fifth A, wherein when the gate driver 109 does not receive the output enable signal (the OE), the output signal having a first gate (G _block1), a second gate output signal (G _block2) second The three-gate output signal (G _block3 ) is only output according to the gate clock signal (CLKV), which is the waveform shown by the dotted line in the figure. Since the gate drive signal 109 from the control IC 11 receives the output enable signal (OE), so that a first gate output signal (G _block1), a second gate output signal (G _block2), and a third gate output signal ( G _block3 ) is controlled by the output enable signal (OE), and the actual output waveform will still output a low level signal when the output enable signal (OE) is at a high level, thus corresponding to the gate The rising edge of the clock signal (CLKV) should be driven to the high-level dotted line. The output of the signal (OE) is still a low-level waveform and a solid line waveform is output to the active matrix area. 111.

Since the trace resistance between the gate driver 109 and the active matrix region 111 in the liquid crystal display panel is not uniform, the charging time of the pixels of the first block 1 and the third block 3 on the upper and lower sides is low. The charging time of the pixel of the second block 2 in the middle portion. Therefore, in the embodiment, the output enable signal (OE) includes the first pulse width (w ₁ ) and the second pulse width (w). ₂ ), that is, the first pulse width (w ₁ ) corresponding to the output enable signal (OE) of the first block 1 and the third block 3 corresponding to the upper and lower sides is maintained, and corresponds to the middle portion The second pulse width (w ₂ ) of the square wave width of the output enable signal (OE) of the second block 2 of the second block 2 (between the first block 1 and the third block 3) is widened, as shown in FIG. Shown. In this way, the pixel blocks in the first block 1 and the second block 3 corresponding to the output enable signal (OE) of the first pulse width (w ₁ ) in the active matrix region 111 of the liquid crystal display panel can be made. Receiving the pulse width (w _block1 ) of the first gate output signal (G _block1 ) outputted by the gate driver 109 and the third gate output signal (G _block3 ), corresponding to the second pulse width ( w ₂₎ of the second gate output signal (G _block2) a pulse width (w _Block2) smaller than the first gate output signal (G _block1) and the output signal of the third gate (G _block3) of the pulse width (w _Block1 ). It should be noted that, for those of ordinary skill in the art, it should be readily apparent that the present invention adds a second pulse width (w ₂ ) corresponding to the output enable signal (OE) of the intermediate portion. Width, but the scope of this widening is in the charging time is still within the specification value, the purpose is to make the charging time of the pixels in the second block 2 of the middle part of the active matrix area can be compared with the upper and lower sides The charging time of the pixels in the first block 1 and the third block 3 is equal.

In order to make the above description clearer and clearer, please refer to the sixth figure. The square wave depicted by the dotted line is the ideal square wave shape of the gate output signal, and the waveform depicted by the solid line is the gate output signal. The actual waveform shape, and the first gate output signal (G _block1 ) and the third gate output signal (G _block3 ) of the first block 1 and the third block 3 output to the active matrix region 111 of the liquid crystal display panel The waveform distortion phenomenon is more serious because of the higher resistance of the trace, which results in shorter charging time of the pixels in the first block 1 and the third block 3; however, the second block 2 The two gate output signal (G _block2 ) has a waveform that is closer to the ideal square wave shape because of the lower resistance of the trace, so if the width of the second gate output signal (G _block2 ) and the first gate output signal ( G _block1 ) and the third gate output signal (G _block3 ) are the same, which causes the charging time of the pixels in the second block 2 to be longer. In this embodiment, the second gate output signal (G _block2 ) of the second block 2 of the active matrix 111 outputted to the liquid crystal display panel is widened by the pulse width of the output enable signal (OE). The pulse width of the second gate output signal (G _block2 ) is reduced, so that the charging time (A ₁ ) of the pixels of the second block 2 is shortened and compared with the first block 1 and the third block. The charging time (A ₂ ) of the pixel of 3 is equivalent, that is, A ₁ = A ₂ . Therefore, when the pixels in the active matrix region 111 of the liquid crystal display panel have the same charging time, the display defects caused by the uneven charging ability of the pixels of the different blocks in the active matrix region 111 are bright. Dark lines and other phenomena can be eliminated.

In this embodiment, since the output enable signal (OE) is generated by the signal control IC 11 and output to the gate driver 109, the signal is used to control the internal timing of the IC 11 to achieve output. The energy signal (OE) has a first pulse width (w ₁ ) and a second pulse width (w ₂ ). In some embodiments of the present invention, the information about the waveform width of the output enable signal (OE) can be temporarily stored in the memory 13 and controlled by the information stored in the memory 13 to control the signal. The operating mode of the IC.

In another embodiment of the present invention, instead of changing the pulse width of the output enable signal, the first gate output signal (G _block1 ) is changed by using different gate clock signals (CLKV). The second gate output signal (G _block2 ) and the third gate output signal (G _block3 ) have different pulse widths. Therefore, the gate output signal is output to the active matrix region 111 of the liquid crystal display panel. The pixels can reach an equal charging time. Here, the clock command of the different gate clock signal (CLKV) is also stored in the memory 13 and is read by the signal control IC 11 after the clock command is activated when the liquid crystal display panel is activated. This is achieved by outputting different gate clock signals (CLKV). In this way, it is possible to eliminate the display defect of the liquid crystal display panel such as the bright and dark lines due to the uneven charging ability of the respective pixels.

It should be noted that although the description herein roughly divides the active matrix region 111 into three blocks, it should be easily known to the first block 1 for those having ordinary knowledge in the art. The second block 2 can be subdivided into more blocks, and the second block 2 and the third block 3 can be subdivided into more blocks to adjust according to the actual display effect. That is, in some embodiments of the present invention, the block may vary depending on the resolution of the liquid crystal display panel. In other embodiments of the present invention, each gate output signal may also adjust its corresponding output enable signal for the resistance of the trace between the gate driver and the active matrix. The pulse width is such that the charging time of each pixel in the active matrix area is the same, and the display effect of the liquid crystal display is ensured.

The above description is a preferred embodiment of the invention. Those skilled in the art should be able to understand the invention and not to limit the scope of the patent claims claimed herein. The scope of patent protection is subject to the scope of the patent application and its equivalent fields. Any modification or refinement made by those skilled in the art without departing from the spirit or scope of the present invention is equivalent to the equivalent change or design made in the spirit of the present disclosure, and should be included in the following patent application scope. Inside.

101. . . Timing controller

103. . . Flexible circuit board

105. . . glass substrate

107. . . Source driver

109. . . Gate driver

111. . . Active matrix area

113. . . Scanning line

115. . . Data line

117. . . Traces

119. . . Middle part of the trace

1. . . First block

2. . . Second block

3. . . Third block

301. . . Using a timing controller to provide an output enable signal to a gate driver, wherein the output enable signal includes a first pulse width and a second pulse width

303. . . Transmitting the first gate output signal to the first block of the liquid crystal display panel by the gate driver, wherein the first gate output signal is defined by the first pulse width

305. . . Transmitting the second gate output signal to the second block of the liquid crystal display panel by the gate driver, wherein the second gate output signal is defined by the second pulse width

307. . . Transmitting the third gate output signal to the third block of the liquid crystal display panel by the gate driver, wherein the third gate output signal is defined by the first pulse width

11. . . Signal control IC

13. . . Memory

LP. . . Latch pulse

CLKV. . . Gate clock signal

OE. . . Output enable signal

G _block1 . . . First gate output signal

G _block2 . . . Second gate output signal

G _block3 . . . Third gate output signal

G _ideal . . . Ideal square wave shape for gate output signal

w ₁ . . . First pulse width

w ₂ . . . Second pulse width

w _block1 . . . Pulse width of the first gate output signal

w _block2 . . . Pulse width of the second gate output signal

A ₁ . . . Charging time of the first block and the third block

A ₂ . . . Charging time of the second block

The first A-C diagram shows a schematic diagram of the structure of a liquid crystal display panel of a conventional thin film transistor liquid crystal display.

The second figure shows a method of conventionally forming the intermediate traces in a fold line to solve the bright and dark lines of the liquid crystal display panel.

The third figure shows a schematic flow chart of the method for eliminating the bright and dark lines of the liquid crystal display panel of the present invention.

The fourth figure shows a schematic diagram of control signal transmission of the liquid crystal display panel of the present invention.

The fifth A-B diagram shows a schematic diagram of the timing control method of the method for eliminating the bright and dark lines of the liquid crystal display panel of the present invention.

The sixth figure shows a schematic diagram of the method for eliminating the bright and dark lines of the liquid crystal display panel of the present invention such that each pixel of the liquid crystal display panel has the same charging time.

301. . . Providing an output enable signal to a gate driver by using a timing controller, wherein the output enable signal includes a first pulse width and a second pulse width

303. . . Transmitting the first gate output signal to the first block of the liquid crystal display panel by the gate driver, wherein the first gate output signal is defined by the first pulse width

305. . . Transmitting the second gate output signal to the second block of the liquid crystal display panel by the gate driver, wherein the second gate output signal is defined by the second pulse width

307. . . Transmitting the third gate output signal to the third block of the liquid crystal display panel by the gate driver, wherein the third gate output signal is defined by the first pulse width

Claims (10)

A method for eliminating a bright and dark line of a liquid crystal display panel, the method comprising: providing an output enable signal to a gate driver by a timing controller, wherein the output enable signal comprises at least a first pulse width and at least one a second pulse width, the first pulse width is smaller than the second pulse width; the gate driver transmits a first gate output signal to the first block of the liquid crystal display panel, wherein the first gate The pole output signal is defined by the first pulse width; the gate driver transmits a second gate output signal to a second block of the liquid crystal display panel, wherein the second gate output signal is The second pulse width is defined by the gate driver, and the third gate output signal is transmitted to the third block of the liquid crystal display panel, wherein the third gate output signal is determined by the first pulse width The first gate output signal, the second gate output signal, and the third gate output signal are such that pixels of the first block, the second block, and the third block are Charging time is equal. The method for eliminating a bright and dark line of a liquid crystal display panel according to claim 1, wherein the timing controller comprises a signal control IC and a memory. The method for eliminating a bright and dark line of a liquid crystal display panel according to claim 2, wherein the first pulse width and the second pulse width are controlled The memory is temporarily stored in the memory to provide the signal control IC to generate the output enable signal. The method for eliminating a bright and dark line of a liquid crystal display panel according to claim 1, wherein the timing controller further provides a gate clock signal to the gate driver. The method for eliminating a bright and dark line of a liquid crystal display panel according to claim 4, wherein the first gate output signal, the second gate output signal, and the third gate output signal are connected to the gate clock Controlled by the signal. A method for eliminating a bright and dark line of a liquid crystal display panel, the method comprising: providing an output enable signal to a gate driver by a timing controller, wherein the output enable signal has a plurality of pulse widths, wherein the plurality of pulse widths The pulse width includes at least a first pulse width and at least a second pulse width, the first pulse width is smaller than the second pulse width; and the plurality of gate output signals are respectively transmitted by the gate driver a plurality of blocks of the liquid crystal display panel, wherein the plurality of gate output signals in the plurality of blocks are defined by the plurality of pulse widths; wherein the plurality of gate output signals are caused by the plurality of gates The charging time of the pixels of the block is equal. The method for eliminating a bright and dark line of a liquid crystal display panel according to claim 6, wherein the timing controller comprises a signal control IC and a memory. The method for eliminating the bright and dark lines of the liquid crystal display panel according to claim 7, wherein the command for controlling the plurality of pulse widths is temporarily stored in the memory to provide the signal control IC to generate the output enable signal. The method for eliminating a bright and dark line of a liquid crystal display panel according to claim 8, wherein the timing controller further provides a gate clock signal to the gate driver. The method for eliminating a bright and dark line of a liquid crystal display panel according to claim 9, wherein the plurality of gate output signals are controlled by the gate clock signal.