KR20110070171A - Liquid crystal display device and method of driving the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a method of driving the same are provided to maintain the leakage current of a thin film transistor in a pixel region and the coupling between a data line and a pixel electrode by supplying a gate low voltage to a gate line. CONSTITUTION: In a liquid crystal display device and a method of driving the same, a liquid crystal panel(120) comprises a gate line and a data line, a thin film transistor, a storage capacitor, and a liquid crystal capacitor. The gate driving unit(130) comprises a gate low voltage supply unit(132) and supplies a gate signal to the gate line. The gate signal has a gate high voltage and a gate low voltage. A gate low voltage supply unit outputs different gate low voltages at frame. A data driver supplies a data signal to the data line. A timing controller(150) supplies a gate control signal to the gate driving unit and supplies RGB signal and data control signal to the data driver.

Description

Liquid Crystal Display and Driving Method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a frame inversion and common voltage swing method, in which upper and lower luminance deviations and vertical crosstalk are improved by supplying different gate low voltages to the gate wirings. will be.

In general, a liquid crystal display (LCD) forms a liquid crystal layer between two substrates facing each other and is spaced apart from each other, and reconstructs the liquid crystal molecules of the liquid crystal layer by an electric field generated by applying a voltage to the electrodes of the two substrates. By arranging, it is an apparatus which expresses an image by the transmittance | permeability of the light which changes.

In particular, among the liquid crystal display devices, an active matrix liquid crystal display device in which pixels defined by gate lines and data lines that cross each other are arranged in a matrix form, and switching elements and pixel electrodes are formed in each pixel are widely used. All.

FIG. 1 is a diagram illustrating one pixel area of a conventional active matrix liquid crystal display device.

As illustrated in FIG. 1, one pixel area P of a conventional liquid crystal display device is defined by a gate line GL and a data line DL that cross each other.

In the pixel region P, a thin film transistor T connected to the gate line GL and a data line DL, a storage capacitor Cst and a liquid crystal capacitor Clc connected to the thin film transistor T are formed. Is formed.

Specifically, the gate electrode g of the thin film transistor T is connected to the gate line GL, the source electrode s of the thin film transistor T is connected to the data line DL, and the thin film transistor T The drain electrode of is connected to a pixel electrode (not shown) which is one electrode of the liquid crystal capacitor Clc.

Referring to the operation of the pixel area P of the liquid crystal display, a gate signal and a data signal are applied to the gate line GL and the data line DL, and the thin film transistor T is turned on according to the gate signal. When turned on, the data signal is applied as a pixel voltage Vp to one electrode of the storage capacitor Cst and the liquid crystal capacitor Clc through the thin film transistor T.

At this time, the common voltage Vcom is applied to the other electrodes of the capacitor Cst and the liquid crystal capacitor Clc, and the electric field generated by the pixel voltage Vp and the common voltage Vcom re-assembles the liquid crystal layer (not shown). Display the images by arranging.

The difference between the pixel voltage Vp and the common voltage Vcom for generating an electric field to substantially control the liquid crystal layer may be referred to as the effective voltage Vrms.

However, when the liquid crystal display is driven for a long time, the optical characteristics of the liquid crystal layer are degraded by the same electric field applied for a long time, or positive or negative charges are accumulated in the liquid crystal layer adjacent to the pixel electrode and the common electrode, thereby causing the liquid crystal capacitor. (Clc) deteriorates and may cause deterioration of image quality such as afterimages.

Accordingly, in order to prevent degradation of the liquid crystal capacitor Clc and deterioration of image quality, the polarity of the data signal applied to the pixel electrode is inverted at regular intervals, thereby inverting the charge accumulated in the liquid crystal layer. inversion) is proposed.

Invert driving methods include dot inversion, horizontal line inversion, vertical line inversion, and frame inversion. Dot inversion, horizontal line inversion, and vertical line inversion are combined with frame inversion. Can be applied.

Here, the frame inversion method inverts the polarity of the data signal applied to the pixel electrode, that is, the polarity of the pixel voltage for each frame of the video signal. In order to reduce the power consumption and reduce the power consumption, a common voltage swing method in which the common voltage is changed inversely to the pixel voltage may be used.

However, in the liquid crystal display of the frame inversion and the common voltage swing type, defects such as an increase in leakage current, an upper and lower luminance difference, and a vertical crosstalk occur, which will be described with reference to the drawings.

FIG. 2 is a diagram illustrating a test screen displayed by a liquid crystal display of a conventional frame inversion and common voltage swing method, and FIG. 3 is a gate signal, a pixel voltage, 4 is a diagram illustrating a common voltage and an effective voltage, and FIG. 4 is a diagram illustrating a current-voltage (IV) characteristic curve of a thin film transistor of the liquid crystal display of FIG. 2.

As shown on the left side of FIG. 2, when a single gray scale data signal is applied to the liquid crystal panel 20 of the liquid crystal display device driven by the frame inversion and the common voltage swing method, an image of uniform luminance is displayed. Instead of being displayed, an image in which luminance increases from the upper portion A of the liquid crystal panel 20 to the lower portion C through the central portion B is displayed, thereby causing an upper and lower luminance deviation.

In addition, as shown in the right side of FIG. 2, a crosstalk is provided in the liquid crystal panel 20 of the liquid crystal display device driven by the frame inversion and the common voltage swing method, in which a window at the center portion having different luminance from the edge portion is disposed. When the test pattern is displayed, vertical crosstalk phenomena occur in which edges at the top of the window and at the bottom of the window have different luminance from those of the other edges.

This defect is caused by the source electrode s and the drain of the thin film transistor T during the period where the thin film transistor (T in FIG. 1) of the pixel region (P in FIG. 1) of the liquid crystal panel 20 is turned off. This is due to the leakage current between the electrodes d and the coupling capacitance between the data lines DL and the pixel electrodes.

That is, as shown in FIG. 3, in the pixel area P of the upper portion A of the liquid crystal panel 20, the gate signal Vg is initially displayed at each of the nth and (n + 1) th frames. After the gate high voltage Vgh is turned on and the thin film transistor T is turned on, the gate signal Vg becomes the first gate low for the remaining periods of the nth and (n + 1) th frames. The thin film transistor T is turned off by the voltage Vgl1.

During the nth frame, the common voltage Vcom becomes the first voltage V1 of positive polarity (+) and the pixel voltage Vp becomes the second voltage V2 of negative polarity (−). During the n + 1 frame, the common voltage Vcom becomes the second voltage V2 of negative polarity (-) and the pixel voltage Vp becomes the first voltage V1 of positive polarity (+).

That is, not only the pixel voltage Vp is inverted for each frame, but the common voltage Vcom is also inverted for each frame. Such a voltage change of the common voltage Vcom is also referred to as a common voltage Vcom swing.

As described above, in the pixel area P of the upper portion A of the liquid crystal panel 20, the common voltage Vcom and the pixel voltage Vp are inverted and kept constant for the nth and (n + 1) th frames, respectively. As a result, the difference between the common voltage Vcom and the pixel voltage Vp in the nth and (n + 1) th frames is the same as the first effective voltage Vrms1.

On the other hand, in the pixel area P of the central portion B of the liquid crystal panel 20, the gate signal Vg is the gate high voltage Vgh in the middle of each of the nth and (n + 1) th frames. After the thin film transistor T is turned on, the gate signal Vg is applied to the first gate for the remaining periods of the nth and (n + 1) th frames until the next gate high voltage Vgh is reached. The thin film transistor T is turned off by the low voltage Vgl1.

That is, in the pixel area P of the central portion B of the liquid crystal panel 20, the pixel voltage Vp of the previous frame is maintained until the middle of the nth frame, and the thin film transistor T is turned on in the middle of the nth frame. After being turned on, the common voltage Vcom becomes the first voltage V1 and the pixel voltage Vp becomes the second voltage V2 so as to correspond to the nth frame.

However, when the common voltage Vcom is changed from the first voltage V1 to the second voltage V2 as the (n + 1) th frame, the pixel voltage Vp is coupled to the second voltage by coupling. The voltage is changed from V2 to the third voltage V3.

The variation of the pixel voltage Vp refers to the variation of the drain electrode (d of FIG. 1) of the thin film transistor T, and accordingly, the voltage difference between the gate electrode (g of FIG. 1) and the drain electrode d is first. The gate drain voltage Vgd1 is changed from the second gate drain voltage Vgd2.

The variation of the gate drain voltage causes a difference in leakage current of the thin film transistor T. As shown in FIG. 4, the first current (A) is applied to the thin film transistor T to which the first gate drain voltage Vgd1 is applied. While I1) flows, the second current I2 larger than the first current I1 flows through the thin film transistor T to which the second gate drain voltage is applied.

Therefore, the amount of change in the pixel voltage Vp due to the coupling is different from the amount of change in the common voltage Vcom. As a result, the difference between the common voltage Vcom and the pixel voltage Vp before the common voltage Vcom is changed. Although the first effective voltage Vrms1 is different, the difference between the common voltage Vcom and the pixel voltage Vp after the common voltage Vcom is changed is that the second effective voltage Vrms2 different from the first effective voltage Vrms1 is different. do.

That is, since the pixel area P of the central portion B of the liquid crystal panel 20 displays the image by the combination of the first and second effective voltages Vrms1 and Vrms2, the image is displayed by the first effective voltage Vrms1. An image of different luminance from the pixel area of the upper portion A to be displayed is displayed.

This situation is similarly applied to the lower portion C of the liquid crystal panel 20. The gate signal Vg becomes the gate high voltage Vgh at the end of each of the n-th and (n + 1) th frames. Since the thin film transistor T is turned on, the application time ratio of the second effective voltage Vrms2 to the first effective voltage Vrms1 is longer than that of the upper portion A and the central portion B, and thus the upper portion ( An image of different luminance from A) and the center portion B is displayed.

Therefore, in the liquid crystal panel 20 of the liquid crystal display device driven by the frame inversion and the common voltage swing method, the upper and lower luminances at which images of different luminance are displayed for each vertical position are displayed due to the coupling difference caused by the leakage current of the thin film transistor T. A difference occurs.

On the other hand, the upper portion, the central portion, and the lower portion (A, B, C) of the liquid crystal panel are all supplied with a data signal through one data wire, while the upper portion and the data signal corresponding to the high luminance are supplied to the central portion (B). The pixel voltages Vp of the lower portions A and C are changed by the leakage current between the source electrode and the drain electrode of the thin film transistor and the coupling between the data line and the pixel electrode.

In addition, as shown in FIG. 3, the pixel voltages Vp of the upper and lower portions A and C have different polarities for most of the frames while the data signal is applied to the central portion B. The pixel voltages Vp of (A, C) fluctuate in opposite directions, which generates vertical crosstalk with fluctuations in brightness in opposite directions.

As a method for preventing the upper and lower luminance deviations and the vertical crosstalk, the thin film transistor is applied by applying a second gate voltage Vg2 by lowering the first gate voltage Vg1 which is the turn-off voltage of the thin film transistor T. A method of reducing the leakage current of (T) may be considered.

However, lowering the turn-off voltage of the thin film transistor T again may cause an increase in leakage current.

3 and 4, when the turn-off voltage of the thin film transistor T is changed to the second gate voltage Vgl2, the pixel region P of the central portion B of the liquid crystal panel 20 is changed. The leakage current can be reduced after the pixel voltage Vp of Eq.) Is changed to the third voltage V3, but the second voltage V2 is changed before the pixel voltage Vp is changed to the third voltage V3. During the holding, the third gate drain voltage Vgd3 is applied to the thin film transistor T so that the third current I3 larger than the first current I1 flows, thereby increasing the leakage current.

As described above, in a liquid crystal display device having a frame inversion and a common voltage swing type, there is a problem that image quality defects such as upper and lower luminance deviation and vertical crosstalk occur due to leakage current of the thin film transistor and coupling between the data line and the pixel electrode. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. In the liquid crystal display device of the frame inversion and the common voltage swing type, the leakage current and the data of the thin film transistor in the pixel region are supplied by supplying different gate-low voltages to the gate wirings for each frame. An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which maintain a constant coupling between a wiring and a pixel electrode, and improve image quality defects such as upper and lower luminance deviations and vertical crosstalk.

In order to achieve the above object, the present invention includes a gate wiring and data wiring crossing each other, a thin film transistor connected to the gate wiring and data wiring, a storage capacitor and a liquid crystal capacitor connected to the thin film transistor. A liquid crystal panel; A gate driver configured to output a gate low voltage for each frame, the gate driver supplying a gate signal having a gate high voltage and the gate low voltage to the gate line; A data driver supplying a data signal to the data line; It provides a liquid crystal display device including a timing controller for supplying a gate control signal to the gate driver, and supplying an RGB signal and a data control signal to the data driver.

Here, the gate low voltage supply unit outputs a first gate voltage during an nth frame, and a second gate low lower than a first gate voltage during a (n + 1) th frame continuous with the nth frame. The voltage can be output.

The gate driver may further include a shift register unit and pull-up and pull-down transistors turned on or off according to an output of the shift register unit and connected in series with each other. The supply unit may include an n-th and (n + 1) th frame transistor connected in series between the first and second gate voltages.

In addition, a connection node of the n-th and n-th frame transistors is connected to the pull-down transistor, and the n-th frame transistor is turned on during the nth frame according to an nth control signal. The transistor for the (n + 1) th frame may be turned on during the (n + 1) th frame according to the (n + 1) th control signal.

The n-th and n-th frame transistors may be formed in the liquid crystal panel.

The gate driver may further include a shift register unit and a pull-up transistor that is turned on or off according to an output of the shift register unit, and the gate-low voltage supply unit is further configured to the pull-up transistor. The first and second pull-down transistors may be connected in parallel and connected to the first and second gate voltages, respectively.

The first pull-down transistor is turned on for the n-th frame according to the n-th control signal, and the second pull-down transistor is the (n + 1) -th according to the (n + 1) th control signal. Can be turned on during the frame.

In addition, the first and second pull-down transistors may be formed in the liquid crystal panel.

On the other hand, the present invention, a liquid crystal display including a liquid crystal panel including a gate wiring and a data wiring crossing each other, a thin film transistor connected to the gate wiring and a data wiring, a storage capacitor and a liquid crystal capacitor connected to the thin film transistor. CLAIMS 1. A method of driving an apparatus, comprising: turning on the thin film transistor by supplying a gate signal of a gate high voltage to the gate wiring; Supplying a data signal to the data line and applying a pixel voltage to one electrode of the storage capacitor and the liquid crystal capacitor through the thin film transistor turned on; Applying a common voltage to the storage capacitor and the other electrode of the liquid crystal capacitor during the nth frame, and supplying the gate signal having a first gate voltage to the gate line to turn off the thin film transistor; During the (n + 1) th frame consecutive to the nth frame, a voltage inverted from the common voltage is applied to the storage electrode and the other electrode of the liquid crystal capacitor, and the gate wiring voltage is greater than the first gate voltage. A method of driving a liquid crystal display device includes supplying the gate signal having a low second gate voltage to turn off the thin film transistor.

Here, the data signals during the nth and (n + 1) th frames may be inverted with each other.

As described above, in the liquid crystal display device according to the present invention, by supplying a different gate low voltage for each frame to the gate wiring, it is possible to minimize the leakage current of the thin film transistor due to the variation of the common voltage, thereby Image degradation such as upper and lower luminance deviations and vertical crosstalk can be improved.

That is, when the common voltage is changed while the thin film transistor is turned off and the pixel voltage is maintained, the gate low voltage of the gate signal is changed accordingly, so that the difference between the pixel voltage and the gate voltage is kept constant, thereby reducing the leakage current of the thin film transistor. It can be minimized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a diagram illustrating a liquid crystal display device of frame inversion and common voltage swing type according to a first embodiment of the present invention.

As shown in FIG. 5, the liquid crystal display 110 includes a liquid crystal panel 120 displaying an image, a gate driver 130 supplying a gate signal to the liquid crystal panel 120, and a liquid crystal panel 120. A data driver 140 for supplying a data signal to a video signal, an image signal, a data enable (DE) signal, a horizontal sync (HSY) signal, a vertical sync (VSY) signal, and a clock (CLK) signal from an external system (not shown). The timing controller 150 generates a gate control signal, a data control signal and an RGB signal, supplies a gate control signal to the gate driver 130, and supplies a data control signal and an RGB signal to the data driver 140. Include.

The liquid crystal panel 120 has gate lines GL and data lines DL that cross each other to define pixel regions P, and each pixel region P has gate lines GL and data lines DL. A thin film transistor T connected to each other, a storage capacitor Cst and a liquid crystal capacitor Clc connected to the thin film transistor T are formed.

Specifically, the gate electrode g of the thin film transistor T is connected to the gate line GL, the source electrode s of the thin film transistor T is connected to the data line DL, and the thin film transistor T The drain electrode of is connected to a pixel electrode (not shown) which is one electrode of the liquid crystal capacitor Clc.

Although not shown, the liquid crystal panel 120 includes first and second substrates facing each other, and a liquid crystal layer formed between the first and second substrates, and includes a gate line GL, a data line DL, and a thin film transistor. (T) and the storage capacitor Cst are formed on the first substrate, and the liquid crystal capacitor Clc is a pixel electrode formed on the first substrate, a common electrode formed on the second substrate, a pixel electrode and a common It may be composed of a liquid crystal layer between the electrodes. Of course, in the case of a liquid crystal display of in-plane switching (IPS), a common electrode may be formed on the first substrate.

The gate driver 130 generates a gate signal using the gate control signal, supplies the generated gate signal to the gate line GL of the liquid crystal panel 120, and the data driver uses the data control signal and the RGB signal. The data signal is generated and the generated data signal is supplied to the data line DL of the liquid crystal panel 120.

The gate driver 130 and the data driver 140 each include a plurality of driving integrated circuits (D-ICs) and printed circuit boards (PCBs) on which the plurality of driving integrated circuits are mounted. can do.

In another embodiment, the gate driver 130 may be configured as a plurality of driving integrated circuits without a printed circuit board. In this case, the plurality of driving wirings are formed on the liquid crystal panel 120. The gate control signal is supplied from the data driver 140 through LOG to generate a gate signal.

In another embodiment, the gate driver 130 and the data driver 140 are integrated into one, but a portion of the gate driver 130 such as a level shifter is formed in one integrated driver, and the shift register ( The other part of the gate driver 130, such as a shift register, may be formed in the liquid crystal panel 120 to generate a gate signal. In another embodiment, the gate driver 130 and the data driver 140 may be integrated. In addition, the gate driver and the data signal may be generated and supplied to the liquid crystal panel 120 by one integrated driver.

The timing controller 150 receives a video signal, a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, a clock signal, and the like from an external system such as a TV set or a graphic card of a computer. The signal is generated and supplied to the gate driver 130 and the data driver 140.

Referring to the operation of the liquid crystal display 110, when the thin film transistor T is sequentially turned on according to a gate signal supplied from the gate driver 130 to the gate line GL, the data driver The data signal supplied from the 140 to the data line DL is applied as the pixel voltage Vp to the pixel electrode (not shown) which is one electrode of the storage capacitor Cst and the liquid crystal capacitor Clc.

In this case, the common voltage Vcom is applied to the common electrode, which is the other electrode of the storage capacitor Cst and the liquid crystal capacitor Clc, so that the effective voltage Vrms = defined as the difference between the pixel voltage Vp and the common voltage Vcom. The electric field is generated by | Vp-Vcom |), and the liquid crystal molecules of the liquid crystal layer between the pixel electrode and the common electrode are rearranged by the electric field due to the effective voltage Vrms to display an image.

Here, the gate driver 130 includes a gate low voltage supply unit 132, and the gate low voltage supply unit 132 may have different first and second gate low voltages on respective gate lines GL of the liquid crystal panel 120. It serves to supply, which will be described with reference to the drawings.

6 is a diagram illustrating a gate driver of a liquid crystal display according to a first exemplary embodiment of the present invention.

As shown in FIG. 6, the gate driver 130 of the liquid crystal display (110 of FIG. 5) includes a shift register composed of a plurality of stages (SRS) and an n-th connected to each stage. The gate low voltage supply unit 132 includes a frame transistor Tfn and a (n + 1) th frame transistor Tfn + 1.

The plurality of stages SRS of the shift register sequentially generate the gate signal Vg using the first and second clock signals CLK1 and CLK2 and the output signal of the previous stage, and supply the gate signal Vg to the gate line GL. Each of the plurality of stages SRS includes a shift register unit SRU that receives outputs of the first and second end gates AG1 and AG2, outputs of the first and second end gates AG1 and AG2, and a shift register unit. It includes pull-up and pull-down transistors Tu and Td connected to the output node of the (SRU).

The Q and Qb nodes of the shift register unit SRU alternately have a high and a low in accordance with the first and second clock signals CLK1 and CLK2 and the output signal of the previous stage. When the nodes are high and low, respectively, the pull-up and pull-down transistors Tu and Td are turned on and turned off, respectively, to convert the gate high voltage Vgh of the first clock signal CLK1 to the gate signal Vg. If the Q and Qb nodes are low and high, respectively, the pull-up and pull-down transistors Tu and Td are turned off and turned on to gate the output of the gate-low voltage supply unit 132. Output as signal Vg.

The gate-low voltage supply unit 132 is an n-th frame transistor Tfn and an (n + 1) th frame transistor Tfn + 1 connected in series between the first and second gate voltages Vgl1 and Vgl2. The n-th frame transistor Tfn is turned on for the n-th frame according to the n-th control signal Vfn applied to the gate electrode, and the transistor for the (n + 1) th frame Tfn + 1) is turned on during the (n + 1) th frame according to the (n + 1) th control signal Vfn + 1 applied to the gate electrode.

Accordingly, the gate low voltage supply unit 132 outputs the first gate low voltage Vgl1 through the n-th frame transistor Tfn turned on during the nth frame, and during the (n + 1) th frame. The second gate voltage Vgl2 is output through the turned-on (n + 1) th frame transistor Tfn + 1.

Here, the second gate voltage Vgl2 may be a voltage lower than the first gate voltage Vgl1 by a common voltage variation, and the start of the gate low voltage supply unit 132 corresponding to each gate line GL is started. ) Signal may use a gate high voltage Vgh which is an output of the shift register stage SRS connected to the corresponding gate line GL.

In conclusion, the gate driver 130 of the liquid crystal display 110 according to the first embodiment of the present invention sequentially supplies the gate high voltage Vgh to the gate line GL in a portion of one frame. The gate low voltage is supplied to the gate line GL in the remaining period of one frame, and the first gate voltage Vgl1 is supplied during the nth frame and the second gate voltage (n + 1) during the (n + 1) frame. Vgl2).

Therefore, even when the common voltage Vcom applied to the pixel region P of the liquid crystal panel 120 swings and the pixel voltage Vp is changed by coupling with the common voltage Vcom, By varying the gate low voltage by a corresponding voltage, the voltage difference between the gate electrode and the drain electrode of the thin film transistor T of the pixel region P and the corresponding leakage current can be maintained constant.

In another exemplary embodiment, the shift register and the gate low voltage supply unit 132 of the gate driver 130 may be formed on the first substrate of the liquid crystal panel 120 in the same manner as the thin film transistor T of the pixel region P. It may be formed.

The variation of the gate low voltage by the gate low voltage supply unit 132 will be described with reference to the drawings.

FIG. 7 is a view illustrating a gate signal voltage supply unit of FIG. 6 supplying a gate signal, a pixel voltage, a common voltage and an effective voltage at upper, center, and lower portions of the liquid crystal display of FIG. n and (n + 1) th control signals are shown, which will be described with reference to FIGS. 5 and 6 together.

As shown in FIG. 7, in the pixel area P of the upper portion A of the liquid crystal panel 120, the gate signal Vg is initially gated in each of the nth and (n + 1) th frames. After the thin film transistor T is turned on due to the high voltage Vgh, the gate signal Vg becomes the first gate low voltage (Vg) for the remaining periods of the nth and (n + 1) th frames. Vgl1) turns the thin film transistor T off.

During the nth frame, the common voltage Vcom becomes the first voltage V1 of positive polarity (+) and the pixel voltage Vp becomes the second voltage V2 of negative polarity (−). During the n + 1 frame, the common voltage Vcom becomes the second voltage V2 of negative polarity (-) and the pixel voltage Vp becomes the first voltage V1 of positive polarity (+).

That is, the pixel voltage Vp is inverted frame by frame, the common voltage Vcom is also inverted frame by frame, and the liquid crystal display 110 is driven in a frame inversion and a common voltage swing method.

As described above, in the pixel area P of the upper portion A of the liquid crystal panel 120, the common voltage Vcom and the pixel voltage Vp are inverted and kept constant for the nth and (n + 1) th frames, respectively. As a result, the difference between the common voltage Vcom and the pixel voltage Vp in the nth and (n + 1) th frames is the same as the first effective voltage Vrms1.

In the pixel area P of the central portion B of the liquid crystal panel 120, the gate signal Vg becomes the gate high voltage Vgh in the middle of the n-th frame so that the thin film transistor T is turned on. Then, the gate signal Vg becomes the gate high voltage Vgh again in the middle of the (n + 1) th frame, and the gate signal Vg becomes the first gatelow voltage during the last period of the nth frame among the remaining periods. The thin film transistor T is turned off by (Vgl1), and the gate signal Vg becomes the second gate voltage Vgl2 during the initial period of the (n + 1) th frame so that the thin film transistor T is turned off. It is turned off.

That is, in the pixel area P of the central portion B of the liquid crystal panel 120, the pixel voltage Vp of the previous frame is maintained until the middle of the nth frame, and the thin film transistor T is turned on in the middle of the nth frame. After being turned on, the common voltage Vcom becomes the first voltage V1 and the pixel voltage Vp becomes the second voltage V2 so as to correspond to the nth frame.

Subsequently, during the last period of the n-th frame, the first gate voltage Vgl1 is applied to the gate electrode g of the thin film transistor T, and the drain electrode d and the pixel electrode of the thin film transistor T are applied to the gate electrode g. The second voltage V2, which is the pixel voltage Vp, is applied. Therefore, the second voltage V2 and the first gate row are disposed between the gate electrode g and the drain electrode d of the thin film transistor T. The gate drain voltage corresponding to the difference V2-Vgl1 of the voltage Vgl1 is maintained, and the thin film transistor T has a leakage current corresponding thereto.

When the common voltage Vcom is changed from the first voltage V1 to the second voltage V2 as the (n + 1) th frame, the pixel voltage Vp is coupled to the second voltage by coupling. The voltage is changed from V2 to the third voltage V3.

At this time, unlike the prior art, the second gate voltage Vgl2 lower than the first gate voltage Vgl1 is applied to the gate electrode g of the thin film transistor T, and the second gate voltage Vgl2 is The voltage may be lower than the first gate voltage Vgl1 by the common voltage variation amount V2-V3. (Vgl2 = Vgl1-(V2-V3))

That is, during the initial period of the (n + 1) frame, the second gate voltage Vgl2 is applied to the gate electrode g of the thin film transistor T, and the drain electrode d of the thin film transistor T is applied. And a third voltage V3, which is a pixel voltage Vp, is applied to the pixel electrode. Therefore, the third voltage V3 and the drain electrode d are disposed between the gate electrode g and the drain electrode d of the thin film transistor T. The gate drain voltage corresponding to the difference V3-Vgl2 of the second gate voltage Vgl2 is maintained, and the thin film transistor T has a leakage current corresponding thereto.

In this case, since the second gate voltage Vgl2 is smaller than the first gate voltage Vgl1 by the common voltage variation amount V2-V3, the difference between the third voltage V3 and the second gate voltage Vgl2 ( V3-Vgl2 are equal to the difference (V2-Vgl1) between the second voltage V2 and the first gate voltage Vgl1. (V3-Vgl2 = V3-(Vgl1-(V2-V3)) = V3-Vgl1 + V2-V3 = V2-Vgl1)

That is, the same gate drain voltage is applied to the thin film transistor T of the center portion B of the liquid crystal panel 120 during the last period of the nth frame and the initial period of the (n + 1) th frame, and as a result, the thin film transistor T (T) always maintains a constant leakage current characteristic regardless of the frame.

Therefore, the amount of change in the pixel voltage Vp due to the coupling is kept the same as the amount of change in the common voltage Vcom, so that the difference between the common voltage Vcom and the pixel voltage Vp before and after the common voltage Vcom is changed. Is kept the same as the first effective voltage Vrms1.

That is, since the pixel region P of the central portion B of the liquid crystal panel 120 also displays an image by the first voltage Vrms1, the pixel of the upper portion A displaying the image by the first effective voltage Vrms1. Since the image having the same luminance as that of the region is displayed, the upper and lower luminance deviations of the liquid crystal display 110 do not occur.

This situation is similarly applied to the lower part C of the liquid crystal panel 120. After the gate signal Vg becomes the gate high voltage Vgh at the end of the nth frame, the thin film transistor T is turned on. During the rest of the nth frame, the gate signal Vg becomes the first gate voltage Vgl1 and the thin film transistor T is turned off. During the initial and middle periods of the (n + 1) th frame, The thin film transistor T is turned off because the gate signal Vg becomes the second gate voltage Vgl2.

In this case, the first gate voltage Vgl1 is applied to the gate electrode g of the thin film transistor T during the remaining period of the nth frame, and the thin film transistor is applied during the initial and middle periods of the (n + 1) th frame. Since the second gate voltage Vgl2 is applied to the gate electrode g of (T), the thin film transistor T of the lower portion C of the liquid crystal panel 120 has the remaining section of the nth frame and (n). +1) The same gate drain voltage is applied during the initial and middle periods of the frame, and the thin film transistor T always maintains a constant leakage current characteristic regardless of the frame.

Therefore, the amount of change in the pixel voltage Vp due to the coupling is kept the same as the amount of change in the common voltage Vcom, so that the difference between the common voltage Vcom and the pixel voltage Vp before and after the common voltage Vcom is changed. Is kept the same as the first effective voltage Vrms1.

That is, since the pixel area P of the lower portion C of the liquid crystal panel 120 also displays an image by the first voltage Vrms1, the upper portion A and the center portion displaying the image by the first effective voltage Vrms1. An image having the same luminance as that of the pixel area (B) is displayed, so that upper and lower luminance deviations of the liquid crystal display 110 do not occur.

In addition, since the leakage current of the thin film transistor T is minimized and kept constant by applying different first and second gate voltages Vgl1 and Vgl2 according to the variation of the common voltage Vcom for each frame, the thin film transistor T Also, vertical crosstalk due to the source and drain electrode leakage currents and the coupling between the data line and the pixel electrode does not occur.

As described above, in the liquid crystal display according to the first exemplary embodiment of the present invention, the thin film transistor is applied with a different gate low voltage for each frame so that the thin film transistor has a constant gate drain voltage and leakage current regardless of the common voltage variation. As a result, upper and lower luminance deviations and vertical crosstalk are prevented, thereby improving image quality of the liquid crystal display.

FIG. 8 is a view illustrating a gate driver of a liquid crystal display according to a second exemplary embodiment of the present invention. The configuration of the liquid crystal display according to the second exemplary embodiment of the present invention is applied to upper, middle, and lower portions of the liquid crystal panel. Since the waveforms of the signal and the voltage are the same as those of the first embodiment shown in Figs. 5 and 7, the description thereof will be omitted.

As shown in FIG. 8, the gate driver of the liquid crystal display includes a shift register including a plurality of stages SRS, and first and second pull-down transistors Td1 connected to each stage. And a gate low voltage supply unit 232 configured as Td2.

The plurality of stages SRS of the shift register sequentially generate the gate signal Vg using the first and second clock signals CLK1 and CLK2 and the output signal of the previous stage, and supply the gate signal Vg to the gate line GL. Each of the plurality of stages SRS includes a shift register unit SRU that receives outputs of the first and second end gates AG1 and AG2, outputs of the first and second end gates AG1 and AG2, and a shift register unit. And a pull-up transistor Tu connected to the output node of the SRU.

The Q node of the shift register unit SRU alternates high and low according to the first and second clock signals CLK1 and CLK2 and the output signal of the previous stage. In this case, the pull-up transistor Tu is turned on and outputs the gate high voltage Vgh of the first clock signal CLK1 as the gate signal Vg.

The gate-low voltage supply unit 232 includes first and second pull-down transistors Td1 and Td2 connected in parallel to the pull-up transistor Tu, and includes the first and second pull-down transistors Td1. , Td2 are connected to the first and second gate voltages Vgl1 and Vgl2, respectively.

The first pull-down transistor Td1 is turned on for the nth frame according to the nth control signal Vfn applied to the gate electrode, and the second pull-down transistor Td2 is applied to the gate electrode. The shift register stage SRS is turned on during the n-th frame according to the (n + 1) th control signal Vfn + 1, so that the shift register stage SRS is turned on during the n-th frame. The first gate voltage Vgl1 is output through the transistor Td1, and the second gate voltage Vgl2 is turned on through the second pull-down transistor Td2 turned on during the (n + 1) th frame. Outputs

Here, the second gate voltage Vgl2 may be lower than the first gate voltage Vgl1 by a common voltage variation.

In conclusion, the gate driver of the liquid crystal display according to the second exemplary embodiment of the present invention sequentially supplies the gate high voltage Vgh to the gate line GL in a portion of one frame, and in the remaining portion of one frame. The gate low voltage is supplied to the gate line GL, and the first gate voltage Vgl1 is supplied during the nth frame, and the second gate voltage Vgl2 is supplied during the (n + 1) th frame. .

Therefore, even when the common voltage applied to the pixel region of the liquid crystal panel is changed and the pixel voltage is changed by the coupling with the common voltage, the gate low voltage is varied by the corresponding voltage, thereby making the thin film of the pixel region thin. The voltage difference between the gate electrode and the drain electrode of the transistor T and the resulting leakage current can be kept constant.

In another exemplary embodiment, the shift register and the gate low voltage supply unit 232 of the gate driver may be formed on the first substrate of the liquid crystal panel through the same process as in the thin film transistor T of the pixel region P. .

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

1 is a view showing one pixel area of a conventional active matrix liquid crystal display device;

FIG. 2 is a diagram illustrating a test screen displayed by a liquid crystal display of a conventional frame inversion and common voltage swing method. FIG.

FIG. 3 is a diagram illustrating gate signals, pixel voltages, common voltages, and effective voltages at the top, center, and bottom of the liquid crystal display of FIG.

FIG. 4 is a diagram illustrating a current-voltage (IV) characteristic curve of a thin film transistor of the liquid crystal display of FIG. 2.

FIG. 5 is a diagram illustrating a liquid crystal display device of frame inversion and common voltage swing type according to a first embodiment of the present invention. FIG.

6 is a view illustrating a gate driver of a liquid crystal display according to a first embodiment of the present invention.

FIG. 7 illustrates gate signals, pixel voltages, common voltages and effective voltages at the top, the center, and the bottom of the liquid crystal display of FIG. 5; Figure (n + 1) shows a control signal.

8 is a view illustrating a gate driver of a liquid crystal display according to a second exemplary embodiment of the present invention.

Claims (10)

A liquid crystal panel comprising a gate wiring and a data wiring crossing each other, a thin film transistor connected to the gate wiring and a data wiring, a storage capacitor and a liquid crystal capacitor connected to the thin film transistor; A gate driver configured to output a gate low voltage for each frame, the gate driver supplying a gate signal having a gate high voltage and the gate low voltage to the gate line; A data driver supplying a data signal to the data line; A timing controller supplying a gate control signal to the gate driver and supplying an RGB signal and a data control signal to the data driver Liquid crystal display comprising a. The method of claim 1, The gate low voltage supply unit outputs a first gate voltage during an nth frame, and outputs a second gate voltage lower than a first gate voltage during a (n + 1) th frame continuous with the nth frame. LCD output. The method of claim 2, The gate driver further includes a shift register unit and pull-up and pull-down transistors turned on or off according to an output of the shift register unit and connected in series with each other. And the gate low voltage supply unit includes transistors for n-th and (n + 1) th frames connected in series between the first and second gate-low voltages. The method of claim 3, wherein The connection node of the n-th and (n + 1) -th transistors is connected to the pull-down transistor, The n-th frame transistor is turned on during the n-th frame according to the nth control signal, and the (n + 1) th frame transistor is the (n + 1) th signal according to the (n + 1) th control signal. LCD display turned on during the frame. The method of claim 4, wherein And the nth and (n + 1) th frame transistors are formed in the liquid crystal panel. The method of claim 2, The gate driver further includes a shift register unit and a pull-up transistor turned on or off according to an output of the shift register unit. And the gate low voltage supply unit includes first and second pull-down transistors connected in parallel to the pull-up transistors and connected to the first and second gate voltages, respectively. The method of claim 6, The first pull-down transistor is turned on during the nth frame according to the nth control signal, and the second pull-down transistor is turned on the (n + 1) th frame according to the (n + 1) th control signal. LCD that is turned on during The method of claim 7, wherein And the first and second pull-down transistors are formed in the liquid crystal panel. A method of driving a liquid crystal display device comprising a liquid crystal panel including a gate line and a data line crossing each other, a thin film transistor connected to the gate line and a data line, a storage capacitor and a liquid crystal capacitor connected to the thin film transistor. , Supplying a gate signal having a gate high voltage to the gate wiring to turn on the thin film transistor; Supplying a data signal to the data line and applying a pixel voltage to one electrode of the storage capacitor and the liquid crystal capacitor through the thin film transistor turned on; Applying a common voltage to the storage capacitor and the other electrode of the liquid crystal capacitor during the nth frame, and supplying the gate signal having a first gate voltage to the gate line to turn off the thin film transistor; During the (n + 1) th frame consecutive to the nth frame, a voltage inverted from the common voltage is applied to the storage electrode and the other electrode of the liquid crystal capacitor, and the gate wiring voltage is greater than the first gate voltage. Supplying the gate signal having a low second gate voltage to turn off the thin film transistor; Method of driving a liquid crystal display device comprising a. The method of claim 9, And the data signals during the nth and (n + 1) th frames are inverted from each other.

Images