KR20080054658A - Driving circuit of liquid crystal display device and method for driving the same - Google Patents

Abstract

An apparatus and a method for driving an LCD(Liquid Crystal Display) are provided to decrease voltages of first and second data signals using a line inversion method and invert polarities of neighboring liquid crystal cells for preventing flickering. An apparatus for driving an LCD includes an LCD panel(2), a gate driver(4), a data driver(6), and a common voltage generator(10). The LCD panel includes a plurality of pixels and a plurality of horizontal lines. The gate driver provides a gate signal to a gate line of the LCD panel. The data driver supplies a data signal to a data line of the LCD panel. The common voltage generator supplies an AC common voltage to a common line of the LCD panel. Each of the plurality of pixels includes a first TFT(Thin Film Transistor)(TFT1) connected to the gate line and the data line, a second TFT(TFT2) connected to the common line and the gate line, and a liquid crystal capacitor(Clc) connected to the first and second TFTs.

Description

Driving device for liquid crystal display and driving method thereof {Driving circuit of liquid crystal display device and method for driving the same}

1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a driving waveform diagram of signals for driving the liquid crystal display shown in FIG.

3 is a block diagram showing a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a driving waveform diagram of signals for driving the liquid crystal display shown in FIG.

＊ Description of symbols for main parts of the drawings ＊

2: liquid crystal panel 4: gate driver

6: data driver 8: timing controller

10: common voltage generator Clc: liquid crystal capacitor

Vcom1, Vcom2: first and second common voltages

VL1, VL2: first and second common voltage supply lines

DV1, DV2: first and second data signals

GV1 to GV3: first to third gate signals

ΔVp, ΔVc: data signal and common kickback voltage

The present invention relates to a driving apparatus of a liquid crystal display device and a driving method thereof, which can prevent a flicker by compensating a kickback voltage ΔVp of a data signal with a kickback voltage ΔVc of a common voltage.

Conventional liquid crystal displays display images by adjusting the light transmittance of liquid crystals having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed. Each of the pixel electrodes is connected to a thin film transistor (TFT) which is a switching element. The TFT is turned on by the scan pulse of the gate line, so that the data signal of the data line is charged to the pixel electrode.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying control signals for controlling the gate driver and the data driver, and a common voltage for supplying a common voltage to the liquid crystal panel. It includes a voltage generator.

In the liquid crystal display configured as described above, in order to drive the liquid crystal cells on the liquid crystal panel, such as a frame inversion system, a line column inversion system, and a dot inversion system, Inversion driving method is used.

The liquid crystal panel driving method of the frame inversion method inverts the polarity of the data signal supplied to the liquid crystal cells on the liquid crystal panel every time the frame is changed. In the liquid crystal panel driving method of the line inversion method, the polarities of the data signals supplied to the liquid crystal cells are inverted according to a line (column) on the liquid crystal panel. In the dot inversion method, data signals having polarities opposite to those of adjacent liquid crystal cells in the vertical and horizontal directions are supplied to each of the liquid crystal cells on the liquid crystal panel, and the polarities of the data signals supplied to all liquid crystal cells on the liquid crystal panel are changed for each frame. Let it be reversed. The driving of the inversion method is performed in response to the data driver according to the polarity control signal supplied from the timing controller to the data driver.

Among the inversion driving methods, the line inversion method can reduce the power consumption compared to the driving methods such as dot inversion since the low power driving capable of driving by lowering the voltage level of the data signal is possible.

In this line inversion driving method, the data line direction of the liquid crystal panel, that is, a positive or negative data signal is repeatedly applied to the liquid crystal cell in each gate line unit, and the voltage level of the data signal is B (black), It is displayed repeatedly as W (white), B, W .... or W, B, W, B .... In addition, the voltage level of the common voltage is also in units of each gate line so as to be opposite to the polarity of each data signal. It is supplied inverted in 1 vertical period. As a result, an image is displayed according to the difference between the voltage level and the common voltage level of each data signal, thereby enabling low power driving to lower and drive the voltage level of the data signal.

However, the above-described line inversion method is particularly vulnerable to pixel voltage variations called kickback voltages. In other words, the voltage level of the data signal charged in the liquid crystal cell drops by the kickback voltage at the falling edge of the scan pulse applied to each gate line, and the voltage level of the data signal is applied when the next data signal is applied. Will fall slowly.

In particular, when a negative data signal is applied, the difference between the voltage level of the data signal and the common voltage level becomes larger than that of the positive polarity, thereby making it more vulnerable to horizontal crosstalk. Accordingly, there is a problem in that the flicker occurrence rate of flickering of the screen increases and the image quality deteriorates.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a driving device of a liquid crystal display device and a driving method thereof, which can prevent a flicker by compensating a kickback voltage of a data signal with a kickback voltage of a common voltage. .

A driving device of a liquid crystal display according to an exemplary embodiment of the present invention for achieving the above object is a liquid crystal panel including a plurality of horizontal lines consisting of a plurality of pixels, and supplying a gate signal to a gate line of the liquid crystal panel. A gate driver, a data driver supplying a data signal to a data line of the liquid crystal panel, and a common voltage generator supplying an AC common voltage to a common line of the liquid crystal panel, wherein each of the plurality of pixels includes: the gate line; A first thin film transistor connected to the data line; A second thin film transistor connected to the common line and the gate line; And a liquid crystal capacitor connected to the first and second thin film transistors.

In addition, the driving method of the liquid crystal display according to the embodiment of the present invention for achieving the above object is the step of supplying a data signal to the data line, supplying an AC common voltage to the common line, a gate signal to the gate line Supplying the liquid crystal signal to a voltage difference between the data signal supplied through the first thin film transistor turned on by the gate signal and the AC common voltage supplied through the second thin film transistor turned on by the gate signal; Charging the capacitor and maintaining the charging voltage of the liquid crystal capacitor by the first and second thin film transistors turned off by the gate signal.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram illustrating a liquid crystal display according to a first embodiment of the present invention.

The liquid crystal display shown in FIG. 1 includes a liquid crystal panel 2 having a pixel region, a gate driver 4 for driving gate lines GL1 to GLn of the liquid crystal panel 2, and a data line. Common to the data driver 6 for driving the DL1 to DLm, the timing controller 8 for controlling the gate driver 4 and the data driver 6 and the common voltage supply line VL of the liquid crystal panel 2. It includes a common voltage generator 10 for supplying a voltage (Vcom).

The liquid crystal panel 2 includes a first thin film transistor TFT1 formed in each pixel area defined by the gate lines GL1 to GLn and the data lines DL1 to DLm, and a liquid crystal capacitor connected to the TFT1. Clc). The liquid crystal capacitor Clc includes a pixel electrode connected to the TFT1, a common electrode positioned parallel to the pixel electrode to form a horizontal electric field in the liquid crystal, and a second thin film transistor connected between the common electrode and the common voltage supply line VL. (Hereinafter referred to as TFT2). The TFT1 supplies the data signals from the data lines DL1 to DLm to the pixel electrodes in response to the scan pulses from the gate lines GL1 to GLn. The TFT2 supplies the common voltage Vcom from the common voltage supply line VL to the common electrode in response to the scan pulses from the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected to the liquid crystal capacitor Clc in parallel so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating layer interposed therebetween. In contrast, the storage capacitor Cst is formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween.

The gate driver 4 includes a shift register that sequentially generates scan pulses, that is, gate-on voltages, in response to the gate control signal GCS from the timing controller 8. The shift register sequentially supplies scan pulses of the gate-on voltage to each gate line GL1 to GLn. The gate-off voltage is supplied to the gate lines GL1 to GLn during the period when the scan pulse is not supplied.

The data driver 6 converts the digital image data Data from the outside into analog image data, that is, a data signal in accordance with the data control signal DCS from the timing controller 8. Specifically, the data driver 6 selects a gamma voltage having a predetermined level according to the gray value of the analog image data and supplies the selected gamma voltage to the data lines DL1 to DLm. In addition, the inversion method of the liquid crystal panel 2 is converted in accordance with the polarity control signal POL, so that one horizontal line of data signals is supplied for each horizontal period in which scan pulses are supplied to the gate lines GL1 to GLn. DL1 to DLm). Accordingly, the polarity of the data signal supplied to the data lines DL1 to DLm is inverted into a positive polarity or a negative polarity every one horizontal period.

The timing controller 8 arranges the image data RGB from the outside so as to be suitable for driving the liquid crystal panel 2, and supplies the image data RGB to the data driver 6. In addition, the gate driver 4 and the data driver 6 are controlled by generating the gate control signal GCS and the data control signal DCS using the external synchronization signals DCLK, DE, Hsync, and Vsync. .

The common voltage generator 10 generates a common voltage Vcom and supplies it to the common voltage supply line VL of the liquid crystal panel 2. At this time, the common voltage generator 10 inverts the polarity of the common voltage Vcom to be opposite to the polarity of the data signal and supplies it to the common voltage supply line VL. Accordingly, the polarity of the common voltage Vcom applied to the common voltage supply line VL is inverted by one horizontal period based on the polarity of the data signal.

FIG. 2 is a driving waveform diagram of signals for driving the liquid crystal display shown in FIG. 1.

The common voltage Vcom shown in FIG. 2 is inverted in one horizontal period and is supplied to the common voltage supply line VL. In other words, the common voltage Vcom is generated to have a polarity opposite to that of the data signal DV based on the voltage level of the data signal DV, that is, the polarity of the data signal DV.

The data signal DV is generated at a voltage level corresponding to the gray value of the analog image data and supplied to each data line DL1 to DLm. At this time, the data signal DV is supplied in units of one horizontal period so as to have a polarity opposite to that of the common voltage Vcom based on the voltage level of the common voltage Vcom, that is, the polarity of the common voltage Vcom. . Here, the data signals DV for one horizontal line are supplied to each of the data lines DL1 to DLm, but in FIG. 2, only the data signals DV supplied to the first data line DL1 are illustrated. It was.

Next, a driving method of the liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to the sections T1 to T3 of FIGS. 1 and 2.

First, the T1 section is a section in which the scan pulse GV of the gate-on voltage is supplied to the first gate line GL1, and the TFT1 and TFT2 of the first liquid crystal cells DL1 and GL1 are turned on. Accordingly, the positive data signal DV is supplied to the pixel electrodes of the first liquid crystal cells DL1 and GL1 through the TFT1, and the common electrode of the first liquid crystal cells DL1 and GL1 is provided through the TFT2. The voltage Vcom is supplied.

The liquid crystal capacitor Clc charges the difference voltage VDif between the positive data signal DV and the negative common voltage Vcom. When the gate-off voltage is supplied to the first gate line GL1, the TFT1 and the TFT2 are turned off. The liquid crystal capacitor Clc displays the gray level of the image by maintaining the charged difference voltage VDif, and at this time, the storage capacitor Cst connected in parallel to the liquid crystal capacitor Clc receives the voltage charged in the liquid crystal capacitor Clc. It is maintained until the next data signal DV is supplied.

In other words, when the gate-off voltage is supplied, that is, at the falling edge of the gate-on voltage, the voltage level of the data signal DV charged in the liquid crystal capacitor Clc drops by the kickback voltage ΔVp. The voltage level of the data signal DV gradually falls until the next data signal is applied. In addition, at the same time as the supply of the data signal DV, the level of the common voltage Vcom supplied through the TFT2 also drops by the kickback voltage ΔVc. The level of the common voltage Vcom drops to the same width as the data signal DV until the next data signal DV is applied. Accordingly, the kickback voltage ΔVp of the data signal DVR is compensated by the kickback voltage ΔVc of the common voltage Vcom.

Next, the T2 section is a section in which the scan pulse GV of the gate-on voltage is supplied to the second gate line GL2, and the TFT1 and the TFT2 of the second liquid crystal cells DL1 and GL2 are turned on. Accordingly, the negative data signal DV is supplied to the pixel electrodes of the second liquid crystal cells DL1 and GL2 through the TFT1, and the common common voltage Vcom is supplied to the common electrode through the TFT2.

The liquid crystal capacitor Clc charges the difference voltage VDif between the negative data signal DV and the positive common voltage Vcom. When the gate-off voltage is supplied to the second gate line GL2, the TFT1 and the TFT2 are turned off. The liquid crystal capacitor Clc displays the gray level of the image by maintaining the charged difference voltage VDif, and at this time, the storage capacitor Cst connected in parallel to the liquid crystal capacitor Clc receives the voltage charged in the liquid crystal capacitor Clc. It is maintained until the next data signal DV is supplied.

At the falling edge of the scan pulse GV, the voltage level of the data signal DV charged in the liquid crystal capacitor Clc drops by the kickback voltage ΔVp, and the voltage level of the data signal DV is the next data. It gradually falls until the signal DV is applied. In addition, at the same time as the supply of the data signal DV, the level of the common voltage Vcom supplied through the TFT2 also drops by the kickback voltage ΔVc. The level of the common voltage Vcom drops to the same width as the data signal DV until the next data signal DV is applied. Accordingly, the kickback voltage ΔVp of the data signal DV is compensated by the kickback voltage ΔVc of the common voltage Vcom.

The T3 section is a section in which the scan pulse GV of the gate-on voltage is supplied to the third gate line GL3, and the TFT1 and the TFT2 of the third liquid crystal cells DL1 and GL3 are turned on. Accordingly, the positive data signal DVR is supplied to the pixel electrodes of the third liquid crystal cells DL1 and GL3 through the TFT1, and the negative common voltage Vcom is supplied to the common electrode through the TFT2.

The liquid crystal capacitor Clc charges the difference voltage VDif between the positive data signal DV and the negative common voltage Vcom. When the gate-off voltage is supplied to the third gate line GL3, the TFT1 and the TFT2 are turned off. The liquid crystal capacitor Clc displays the gray level of the image by maintaining the charged difference voltage VDif, and at this time, the storage capacitor Cst connected in parallel to the liquid crystal capacitor Clc receives the voltage charged in the liquid crystal capacitor Clc. It is maintained until the next data signal DV is supplied.

In other words, when the gate-off voltage is supplied, that is, at the falling edge of the scan pulse GV, the voltage level of the data signal DV charged in the liquid crystal capacitor Clc drops by the kickback voltage ΔVp. The voltage level of the data signal DV gradually falls until the next data signal is applied. In addition, at the same time as the supply of the data signal DV, the level of the common voltage Vcom supplied through the TFT2 also drops by the kickback voltage ΔVc. The level of the common voltage Vcom drops to the same width as the data signal DV until the next data signal DV is applied. Accordingly, the kickback voltage ΔVp of the data signal DVR is compensated by the kickback voltage ΔVc of the common voltage Vcom.

As described above, the liquid crystal display according to the first exemplary embodiment of the present invention includes TFT1 and TFT2 to simultaneously supply the data signal DV and the common voltage Vcom, which are inverted by one horizontal period, to each liquid crystal cell. do. Accordingly, while the voltage level of the data signal DV can be driven by performing the line inversion method, the kickback voltage ΔVp of the data signal DV is compensated by the kickback voltage ΔVc of the common voltage Vcom, thereby flickering. Can be prevented.

3 is a configuration diagram illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 3 includes a liquid crystal panel 22 including a pixel region, a gate driver 24 driving gate lines GL1 to GLn of the liquid crystal panel 22, and data lines DL1 to. A data driver 26 for driving the DLm, a timing controller 28 for controlling the gate driver 24 and the data driver 26, and first and second common voltage supply lines VL1 of the liquid crystal panel 22. And a common voltage generator 30 supplying the first and second common voltages Vcom1 and Vcom2 having polarities reversed to each other to VL2.

In the liquid crystal display according to the second exemplary embodiment, other configurations except for the liquid crystal panel 22 and the common voltage generator 30 are the same as those shown in the first exemplary embodiment, a detailed description thereof will be omitted.

The liquid crystal panel 22 according to the second embodiment includes a first thin film transistor TFT1 formed in each pixel region defined by gate lines GL1 through GLn and data lines DL1 through DLm, and TFT1. And a liquid crystal capacitor Clc connected thereto. The liquid crystal capacitor Clc includes a pixel electrode connected to the TFT1, a common electrode positioned parallel to the pixel electrode to form a horizontal electric field in the liquid crystal, and between the common electrode and the first or second common voltage supply lines VL1 and VL2. And a second thin film transistor (hereinafter referred to as TFT2) connected to it. The TFT1 supplies the data signals from the data lines DL1 to DLm to the pixel electrodes in response to the scan pulses from the gate lines GL1 to GLn. The TFT2 supplies first and second common voltages Vcom1 and Vcom from the first or second common voltage supply lines VL1 and VL2 to the common electrode in response to the scan pulses from the gate lines GL1 to GLn. do. In other words, the TFT2 of the liquid crystal capacitor Clc connected to the odd-numbered data lines DL1, DL3,... DLn-1 is connected to the first common voltage supply line VL1 to receive the first common voltage Vcom1. Supply to odd-numbered liquid crystal capacitors Clc. The TFT 2 of the liquid crystal capacitor Clc connected to the even-numbered data lines CL2, DL4,... Is connected to the second common voltage supply line VL2, and the second common voltage Vcom2 is applied to the even-numbered liquid crystal capacitors Clc. ). The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. . The storage capacitor Cst is connected to the liquid crystal capacitor Clc in parallel so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating layer interposed therebetween. In contrast, the storage capacitor Cst is formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween.

The common voltage generator 30 inverts the polarities of the first and second common voltages Vcom1 and Vcom2 to be opposite to each other and supplies them to the first and second common voltage supply lines VL1 and VL2. For example, the common voltage generator 30 generates a first common voltage Vcom1 and supplies it to the first common voltage supply line VL1, and generates a second common voltage Vcom2 to supply a second common voltage. Supply to the line VL2. At this time, the common voltage generator 30 generates the polarities of the first and second common voltages Vcom1 and Vcom2 to be opposite to the polarities of the data signals, thereby providing the first and second common voltage supply lines VL1 and VL2. Supply. Accordingly, the polarities of the first and second common voltages Vcom1 and Vcom2 applied to the first and second common voltage supply lines VL1 and VL2 are inverted by one horizontal period based on the polarity of the data signal.

FIG. 4 is a driving waveform diagram of signals for driving the liquid crystal display shown in FIG. 3.

The first and second common voltages Vcom1 and Vcom2 shown in FIG. 4 are inverted in units of one horizontal period and are supplied to the first and second common voltage supply lines VL. In other words, the first common voltage Vcom1 has a polarity opposite to that of the first data signal DV1 based on the voltage level of the first data signal DV1, that is, the polarity of the first data signal DV1. Is generated to have. The second common voltage Vcom2 is generated to have a polarity opposite to that of the second data signal DV2 based on the voltage level of the second data signal DV2, that is, the polarity of the second data signal DV2. .

The first and second data signals DV1 and DV2 are generated at voltage levels corresponding to grayscale values of the analog image data, and are supplied to the data lines DL1 to DLm. In this case, the first data signal DV1 has a voltage level of the first common voltage Vcom1, that is, a polarity opposite to that of the first common voltage Vcom1 based on the polarity of the first common voltage Vcom1. It is supplied inverted in units of one horizontal cycle so as to have it. The second data signal DV2 is inverted and supplied in units of one horizontal period so as to have a polarity opposite to that of the second common voltage Vcom2 based on the polarity of the second common voltage Vcom2. Here, each of the first and second data signals DV1 and DV2 for one horizontal line is supplied to each of the data lines DL1 to DLm, but in FIG. 4, the first and second data lines DL1, Only the first and second data signals DV1 and DV2 supplied to DL2 are shown.

Next, a driving method of the liquid crystal display according to the second exemplary embodiment of the present invention will be described in detail with reference to the sections T1 and T1 of FIGS. 3 and 4.

First, the T1 section is a section in which the first scan pulse GV1 of the gate-on voltage is supplied to the first gate line GL1, and the TFT1 and TFT2 of the first liquid crystal cells DL1 and GL1 are turned on. Accordingly, the first data signal DV1 having the positive polarity is supplied to the pixel electrodes of the first liquid crystal cells DL1 and GL1, and the first electrode is provided through the TFT2 to the common electrode of the first liquid crystal cells DL1 and GL1. The first common voltage Vcom1 from the common voltage supply line VL1 is supplied with a negative polarity.

The liquid crystal capacitor Clc charges the difference voltage VDif between the positive first data signal DV1 and the negative first common voltage Vcom1. When the gate-off voltage is supplied to the first gate line GL1, the TFT1 and the TFT2 are turned off. The liquid crystal capacitor Clc displays the gray level of the image by maintaining the charged difference voltage VDif, and at this time, the storage capacitor Cst connected in parallel to the liquid crystal capacitor Clc receives the voltage charged in the liquid crystal capacitor Clc. It is maintained until the next first data signal is supplied.

In other words, at the falling edge of the gate-on voltage, the voltage level of the first data signal DV1 charged in the liquid crystal capacitor Clc drops by the kickback voltage ΔVp. The voltage level of the first data signal DV1 gradually falls until the next first data signal is applied. In addition, at the same time as the supply of the first data signal DV1, the level of the first common voltage Vcom1 supplied through the TFT2 also decreases by the kickback voltage ΔVc. The level of the first common voltage Vcom falls to the same width as the first data signal DV1 until the next first data signal is applied. Accordingly, the kickback voltage ΔVp of the first data signal DV1 is compensated by the kickback voltage ΔVc of the common voltage Vcom.

In addition, the second liquid crystal cells D2 and G1 are also supplied with the first scan pulse GV1 having the gate-on voltage at the same timing as the first liquid crystal cells D1 and G1 in the T1 section. Accordingly, the TFT1 and the TFT2 of the second liquid crystal cells DL2 and GL1 are also turned on, so that the second data signal DV2 of the negative polarity is supplied to the pixel electrode of the second liquid crystal cells DL2 and GL1 through the TFT1. The second common voltage Vcom2 having the positive polarity is supplied to the common electrode of the second liquid crystal cells DL2 and GL1 through the TFT2.

The liquid crystal capacitor Clc of the second liquid crystal cells D2 and G1 charges the difference voltage VDif between the negative second data signal DV2 and the positive second common voltage Vcom2. When the gate-off voltage is supplied to the first gate line GL1, the TFT1 and the TFT2 are turned off. The liquid crystal capacitor Clc displays the gray level of the image by maintaining the charged difference voltage VDif, and at this time, the storage capacitor Cst connected in parallel to the liquid crystal capacitor Clc receives the voltage charged in the liquid crystal capacitor Clc. It is held until the next second data signal is supplied.

At the falling edge of the first scan pulse GV1, the voltage level of the second data signal DV2 charged in the liquid crystal capacitor Clc drops by the kickback voltage ΔVp, and thus, the second data signal DV2. The voltage level of F is gradually dropped until the next data signal is applied. In addition, at the same time as the supply of the second data signal DV2, the level of the second common voltage Vcom2 supplied through the TFT2 is also lowered by the kickback voltage ΔVc. The level of the second common voltage Vcom2 drops to the same width as the second data signal DV2 until the next data signal is applied. Accordingly, the kickback voltage ΔVp of the second data signal DV2 is compensated by the kickback voltage ΔVc of the common voltage Vcom.

The T2 section is a section in which the second scan pulse GV2 of the gate-on voltage is supplied to the second gate line GL2, and the TFT1 and the TFT2 of the third liquid crystal cells DL1 and GL2 are turned on. Accordingly, the negative first data signal DV1 is supplied to the pixel electrodes of the third liquid crystal cells DL1 and GL2 through the TFT1, and the first common voltage Vcom1 of the positive polarity is supplied through the TFT2 to the common electrode. do.

The liquid crystal capacitor Clc charges the difference voltage VDif between the negative first data signal DV1 and the positive first common voltage Vcom1. When the gate-off voltage is supplied to the second gate line GL2, the TFT1 and the TFT2 are turned off. The liquid crystal capacitor Clc displays the gray level of the image by maintaining the charged difference voltage VDif, and at this time, the storage capacitor Cst connected in parallel to the liquid crystal capacitor Clc receives the voltage charged in the liquid crystal capacitor Clc. It is maintained until the next first data signal is supplied.

At the falling edge of the second scan pulse GV2, the voltage level of the first data signal DV1 charged in the liquid crystal capacitor Clc drops by the kickback voltage ΔVp, and thus, the first data signal DV1. The voltage level of F is gradually dropped until the next data signal is applied. In addition, at the same time as the supply of the first data signal DV1, the level of the first common voltage Vcom1 supplied through the TFT2 also decreases by the kickback voltage ΔVc. The level of the first common voltage Vcom1 drops to the same width as the first data signal DV1 until the next data signal is applied. Accordingly, the kickback voltage ΔVp of the first data signal DV1 is compensated by the kickback voltage ΔVc of the common voltage Vcom.

As described above, in the liquid crystal display according to the second embodiment of the present invention, the first and second data signals DV1 and DV2 and the first and second common voltages are supplied to adjacent liquid crystal cells in units of one horizontal period. (Vcom1, Vcom2) are inverted to have opposite polarities. Accordingly, the flicker can be prevented by inverting the polarity between the liquid crystal cells adjacent to each other like the dot inversion method while being able to drive by lowering the voltage levels of the first and second data signals DV1 and DV2 using the line inversion method. Can be. Also, as in the first embodiment, the kickback voltages ΔVp of the first and second data signals DV1 and DV2 are compensated for by the kickback voltages ΔVc of the first and second common voltages Vcom1 and Vcom2. The image quality of the video can be improved.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is conventional in the art that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the driving apparatus and the driving method thereof of the liquid crystal display according to the exemplary embodiment of the present invention have the following effects.

That is, the driving device of the liquid crystal display according to the embodiment of the present invention can drive the lowered voltage levels of the first and second data signals by using the line inversion method, and the adjacent liquid crystal cells between the liquid crystal cells as in the dot inversion method. By inverting the polarity, flicker can be prevented.

In addition, the image quality of the displayed image may be improved by compensating kickback voltages of the first and second data signals with kickback voltages of the first and second common voltages.

Claims (16)

A liquid crystal panel including a plurality of horizontal lines formed of a plurality of pixels; A gate driver supplying a gate signal to a gate line of the liquid crystal panel; A data driver supplying a data signal to a data line of the liquid crystal panel; A common voltage generator supplying an AC common voltage to a common line of the liquid crystal panel; Each of the plurality of pixels, A first thin film transistor connected to the gate line and the data line; A second thin film transistor connected to the common line and the gate line; And And a liquid crystal capacitor connected to the first and second thin film transistors. The method of claim 1, The liquid crystal capacitor And the data signal is supplied through the first thin film transistor, and an AC common voltage having a polarity opposite to that of the data signal is supplied through the second thin film transistor. The method of claim 2, The polarity of the AC common voltage is inverted by one horizontal period unit driving device of the liquid crystal display device. The method of claim 3, wherein The common voltage generator The first and second AC common voltages having polarities opposite to each other are supplied, and the common line is a first common line supplying the first AC common voltage, and a second AC common voltage having a polarity opposite to the first AC common voltage. And a second common line for supplying the liquid crystals. The method of claim 4, wherein The first and second thin film transistors included in each of the plurality of horizontal lines A drive device for a liquid crystal display device, which is connected to the same gate line. The method of claim 5, wherein A plurality of second thin film transistors included in each of the plurality of horizontal lines And the first and second common lines are alternately connected to each other. The method of claim 6, The first and second common line And an alternating arrangement of the plurality of horizontal lines. The method of claim 7, wherein The data driver And a data signal whose polarity is inverted in units of one horizontal period to the data line. The method of claim 8, The data driver And a data signal of opposite polarities so that adjacent data lines have opposite polarities. Supplying a data signal to a data line; Supplying an AC common voltage to a common line; Supplying a gate signal to the gate line; Charging a liquid crystal capacitor to a data voltage supplied through a first thin film transistor turned on by the gate signal and a differential voltage of the AC common voltage supplied through a second thin film transistor turned on by the gate signal ; And And maintaining a charging voltage of the liquid crystal capacitor by the first and second thin film transistors turned off by the gate signal. The method of claim 10, The polarity of the AC common voltage is supplied inverted in units of one horizontal period, the driving method of the liquid crystal display device. The method of claim 11, Supplying the AC common voltage Generating and supplying a first AC common voltage to the first common line; And generating a second alternating current common voltage having a polarity opposite to that of the first alternating current common voltage and supplying the second alternating current common voltage to a second common line. The method of claim 12, The first and second thin film transistors A driving method of a liquid crystal display device connected to the same gate line and turned on at the same timing. The method of claim 13, Supplying the first and second AC common voltages And supplying the liquid crystal capacitor through a plurality of second thin film transistors alternately arranged with the first and second common lines. The method of claim 14, Supplying the data signal And a data signal whose polarity is inverted in one horizontal period unit to the data line. The method of claim 15, Supplying the data signal A method of driving a liquid crystal display device comprising supplying data signals of opposite polarities such that adjacent data lines have opposite polarities.

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