TWI765564B - Shift register - Google Patents

Abstract

A shift register is provided. The shift register includes a first shift register unit, a second shift register, a third shift register, a fourth shift register, a fifth shift register, a sixth shift register, a seventh shift register, and an eighth shift register. The first shift register, the second shift register, the third shift register, and the fourth shift register are connected horizontally. The fifth shift register, the sixth shift register, the seventh shift register, and the eighth shift register are connected horizontally. Each of the first shift register, the second shift register, the third shift register, the fourth shift register, the fifth shift register, the sixth shift register, the seventh shift register, and the eighth shift register includes two bus lines which signal level are staggered.

Description

shift register

The present invention relates to a shift register and a display device. Specifically, in the present invention, the plurality of shift register units whose signals in the shift register will affect each other are arranged horizontally side by side, and two signal lines whose levels are staggered are arranged inside each shift register unit to avoid displaying The condition of the light and dark lines of the device.

Under the increasingly fierce competition in the panel industry, the pursuit of higher image quality is nothing more than the pursuit of higher image quality. In most panels, the signal lines that transmit the clock signal are usually set outside the shift register. , the signal line needs to be connected to the line disposed on another metal layer to connect to the corresponding shift register, as shown in FIG. 1 . In order to keep the two signal crossovers from affecting each other, an amorphous silicon (AS) semiconductor layer is added between the two metal layers to avoid damage between the signals, as shown in Figure 2.

Please refer to FIG. 6 , the electrons in the amorphous silicon semiconductor layer will be attracted by the metal layer with higher voltage. Therefore, after adding the amorphous silicon semiconductor layer between the two metal layers, the two metal layers M1 and M2 will be When the potential is high or low, the charge distribution inside the amorphous silicon semiconductor layer is uneven, so that the capacitance of the metal layers M1 and M2 at high potential is different from the capacitance at low potential, resulting in the phenomenon of bright and dark lines on the panel.

In view of this, there is an urgent need in the art for a shift register structure to solve the problem of bright and dark lines on a panel caused by uneven distribution of electric charges in the amorphous silicon semiconductor layer due to the difference in high and low potentials between the cross-line signal lines.

The object of the present invention is to provide a shift register structure, which is arranged by connecting a plurality of shift register units in which the levels of the received clock signals in the shift register will affect each other in a horizontal arrangement, and A plurality of shift register units whose levels of the received clock signals do not affect each other are connected in a vertical arrangement, and two signal lines are arranged inside the shift register unit, and the shift registers connected in a vertical arrangement are connected. The signal lines inside the storage unit are the same, and the levels of the clock signals transmitted by the two signal lines inside the same shift register unit are staggered.

Accordingly, the shift register structure of the present invention can not only reduce the number of cross lines between the signal line and the shift register unit, but also solve the bright and dark lines caused by the mutual influence of the two signal capacitances during the transmission of the clock signal, and reduce the Due to the uneven distribution of charges in the amorphous silicon semiconductor layer, the problem of capacitance mismatch between signal lines can avoid the occurrence of bright and dark lines.

To achieve the above object, the present invention discloses a shift register, which includes a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit storage unit. The first shift register unit and the second shift register unit are laterally connected, and the third shift register unit and the fourth shift register unit are laterally connected. The first shift register unit and the third shift register unit include the first signal line and the third signal line, and the second shift register unit and the fourth shift register unit include the second signal line and the fourth signal line.

In addition, the present invention further discloses a shift register, which includes a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit , a fifth shift temporary storage unit, a sixth shift temporary storage unit, a seventh shift temporary storage unit, and an eighth shift temporary storage unit. The first shift register unit is coupled to a first signal line. The second shift register unit is coupled to a second signal line. The third shift register unit is coupled to a third signal line. The fourth shift register unit is coupled to a fourth signal line. The fifth shift register unit is coupled to a fifth signal line. The sixth shift register unit is coupled to a sixth signal line. The seventh shift register unit is coupled to a seventh signal line. The eighth shift register unit is coupled to an eighth signal line. The first shift temporary storage unit, the second shift temporary storage unit, the third shift temporary storage unit and the fourth shift temporary storage unit are horizontally connected. The fifth shift temporary storage unit, the sixth shift temporary storage unit, the seventh shift temporary storage unit, and the eighth shift temporary storage unit are horizontally connected. The first shift register unit and the fifth shift register unit include the first signal line and the fifth signal line, and the second shift register unit and the sixth shift register unit include The second signal line and the sixth signal line, the third shift register unit and the seventh shift register unit include the third signal line and the seventh signal line, and the fourth shift register The storage unit and the eighth shift register unit include the fourth signal line and the eighth signal line inside.

In addition, the present invention further discloses a shift register, which includes a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit , a fifth shift temporary storage unit, a sixth shift temporary storage unit, a seventh shift temporary storage unit, an eighth shift temporary storage unit, a ninth shift temporary storage unit, a tenth shift temporary storage unit Bit temporary storage unit, an eleventh shift temporary storage unit, a twelfth shift temporary storage unit, a fourteenth shift temporary storage unit, a fourteenth shift temporary storage unit, a fifteenth shift temporary storage unit A bit temporary storage unit and a sixteenth shift temporary storage unit. The first shift register unit is coupled to a first signal line. The second shift register unit is coupled to a second signal line. The third shift register unit is coupled to a third signal line. The fourth shift register unit is coupled to a fourth signal line. The fifth shift register unit is coupled to a fifth signal line. The sixth shift register unit is coupled to a sixth signal line. The seventh shift register unit is coupled to a seventh signal line. The eighth shift register unit is coupled to an eighth signal line. The ninth shift register unit is coupled to a ninth signal line. The tenth shift register unit is coupled to a tenth signal line. The eleventh shift register unit is coupled to an eleventh signal line. The twelfth shift register unit is coupled to a twelfth signal line. The thirteenth shift register unit is coupled to a thirteenth signal line. The fourteenth shift register unit is coupled to a fourteenth signal line. The fifteenth shift register unit is coupled to a fifteenth signal line. The sixteenth shift register unit is coupled to a sixteenth signal line. The first shift temporary storage unit, the second shift temporary storage unit, the third shift temporary storage unit, the fourth shift temporary storage unit, the fifth shift temporary storage unit, the sixth shift temporary storage unit The temporary storage unit, the seventh shift temporary storage unit, and the eighth shift temporary storage unit are horizontally connected, and the ninth shift temporary storage unit, the tenth shift temporary storage unit, and the eleventh shift temporary storage unit storage unit, the twelfth shift temporary storage unit, the thirteenth shift temporary storage unit, the fourteenth shift temporary storage unit, the fifteenth shift temporary storage unit, and the sixteenth shift temporary storage unit The storage unit is connected horizontally. The first shift register unit and the ninth shift register unit include the first signal line and the ninth signal line, and the second shift register unit and the tenth shift register unit include The second signal line and the tenth signal line, the third shift register unit and the eleventh shift register unit include the third signal line and the eleventh signal line, and the fourth shift register unit includes the third signal line and the eleventh signal line. The temporary storage unit and the twelfth shift temporary storage unit include the fourth signal line and the twelfth signal line, and the fifth shift temporary storage unit and the thirteenth shift temporary storage unit include the first signal line. The fifth signal line and the thirteenth signal line. The sixth shift register unit and the fourteenth shift register unit include the sixth signal line and the fourteenth signal line. The seventh shift register unit includes the sixth signal line and the fourteenth signal line. The storage unit and the fifteenth shift register unit include the seventh signal line and the fifteenth signal line, and the eighth shift register unit and the sixteenth shift register unit include the first shift register unit. The eighth signal line and the sixteenth signal line.

After referring to the drawings and the embodiments described later, those skilled in the art can understand other objects of the present invention, as well as the technical means and implementation aspects of the present invention.

The content of the present invention will be explained by the following examples, which are not intended to limit the implementation of the present invention in any specific environment, application or special manner as described in the embodiments. Therefore, the description of the embodiments is only for the purpose of illustrating the present invention, rather than limiting the present invention. It should be noted that, in the following embodiments and drawings, elements not directly related to the present invention are omitted and not shown, and the dimensional relationships among the elements in the drawings are only for easy understanding, not for limiting the actual scale.

The first embodiment of the present invention is shown in FIGS. 3 to 5 . FIG. 3 depicts a schematic diagram of the architecture of a conventional shift register. The shift register 100 includes a plurality of shift register units SR1 ˜SRn, and each shift register unit is respectively connected to a signal line to receive a corresponding clock signal. If the shift register 100 is a four-phase shift register, the shift register 100 includes a first shift register unit SR1, a second shift register unit SR2, and a third shift register unit SR3 and the fourth shift register unit SR4 to the nth shift register unit SRn. n is a multiple of 4.

The first shift register unit SR1 is coupled to the first signal line HC1, the second shift register unit SR2 is coupled to the second signal line HC2, and the third shift register unit SR3 is coupled to the third signal line HC3 And the fourth shift register unit SR4 is coupled to the fourth signal line HC4. The vertical wirings of the first signal line HC1 , the second signal line HC2 , the third signal line HC3 and the fourth signal line HC4 are arranged on the first metal layer M1 , and the horizontal wirings are arranged on the second metal layer.

In the existing structure of the shift register 100, the first shift register unit SR1, the second shift register unit SR2, the third shift register unit SR3 and the fourth shift register unit SR4 are arranged in a vertical direction connected, and the first signal line HC1 , the second signal line HC2 , the third signal line HC3 and the fourth signal line HC4 are all disposed outside the shift register 100 .

Therefore, the vertical wiring of the first signal line HC1 will cross the horizontal wiring of the second signal line HC2 to the fourth signal line HC4, and the vertical wiring of the second signal line HC2 will be connected with the third signal line HC3 and the fourth signal line HC3. The horizontal line of the signal line HC4 is crossed, and the vertical line of the third signal line HC3 is crossed with the horizontal line of the fourth signal line HC.

When the first metal layer M1 and the second metal layer M2 are respectively at high/low potential or low/high potential, the charge distribution inside the amorphous silicon semiconductor layer between the first metal layer M1 and the second metal layer M2 is uneven, and further As a result, the capacitances of the metal layers M1 and M2 at a high potential are different from those at a low potential, resulting in the phenomenon of bright and dark lines appearing on the panel.

Next, please refer to FIG. 4 , which depicts a clock diagram of the clock signal transmitted to each shift register unit in the shift register. It can be seen from the clock diagram that when the first clock signal transmitted by the first signal line HC1 drops from a high level to a low level, the second clock signal transmitted by the second signal line HC2 is at a high level , the fifth clock signal transmitted by the fifth signal line HC5, the sixth clock signal transmitted by the sixth signal line HC6, the seventh clock signal transmitted by the seventh signal line HC7 and the eighth clock transmitted by the eighth signal line HC8 The pulse signals are all low-level, so when the existing shift register structure is operating, the first clock signal will receive three high-level signals, the second clock signal, the third clock signal and the fourth clock signal. bit effect, and the first clock signal will be affected by the fifth clock signal, the sixth clock signal, the seventh clock signal and the eighth clock signal, a total of four low levels, resulting in the mismatch between the high and low capacitance of the panel, and Bright and dark lines appear.

When the first clock signal transmitted by the first signal line HC1 drops from a high level to a low level, the first shift register unit SR1 outputs the first start signal to the third shift register unit SR3, so that the third shift register unit SR3 The shift register unit SR3 is turned on in response to the first start signal, so the third clock signal transmitted by the third signal line HC3 rises from a low level to a high level, and the first shift register unit SR1 transmits the first start signal closed later. When the second clock signal transmitted by the second signal line HC2 drops from a high level to a low level, the second shift register unit SR2 outputs a second start signal to the fourth shift register unit SR4, so that the first shift register unit SR4 The four-shift register unit SR4 is turned on in response to the second start signal, so the fourth clock signal transmitted by the fourth signal line HC4 rises from a low level to a high level, and the second shift register unit SR2 transmits the second Turns off after the start signal.

As can be seen from the foregoing description, in the shift register 100, the third clock signal of the third shift register unit SR3 does not affect the level of the first clock signal of the first shift register unit SR1, and The fourth clock signal of the fourth shift register unit SR4 does not affect the level of the second clock signal of the second shift register unit SR2. That is, the first clock signal and the third clock signal are staggered, and the second clock signal and the fourth clock signal are staggered.

Please refer to FIG. 5, which depicts an embodiment of the architecture of the shift register of the present invention. In order to solve the situation that the levels of the clock signals interact with each other and the bright and dark lines on the panel caused by the crossover between the signal lines, the present invention uses the first shift register unit SR1 and the second shift register unit SR1 and the second shift register, which are mutually influenced by the clock signals. The storage units SR2 are arranged and connected horizontally, and the third shift temporary storage unit SR3 and the fourth shift temporary storage unit SR4 are connected horizontally.

In the vertical direction, the present invention vertically arranges and connects the first shift register unit SR1 and the third shift register unit SR3, and the second shift register unit SR2 and the fourth shift register unit SR2 and the fourth shift register unit SR2. The shift temporary storage unit SR4 is vertically arranged and connected.

Regarding the position of the signal lines, in the present invention, two signal lines whose clock signals do not affect each other are arranged inside the same shift register unit. Specifically, please refer to FIG. 5 again, the first shift register unit SR1 and the third shift register unit SR3 internally include a first signal line HC1 and a third signal line HC3, and a second shift register unit SR2 and the fourth shift register unit SR4 internally includes a second signal line HC2 and a fourth signal line HC4.

By arranging the signal lines inside the shift register unit, the number of jump lines between each signal line and other signal lines can be reduced from 3 jump lines to 1 jump line, and the level of the clock signal can be affected. The span line is reduced from 1 span line to 0 span line.

The second embodiment of the present invention is shown in FIGS. 6 to 9 . FIG. 6 depicts a schematic diagram of the architecture of a conventional shift register. The shift register 200 includes a plurality of shift register units SR1 ˜SRn, and each shift register unit is respectively connected to a signal line to receive a corresponding clock signal. If the shift register 200 is an eight-phase shift register, the shift register 200 includes a first shift register unit SR1, a second shift register unit SR2, and a third shift register unit SR3 , the fourth shift temporary storage unit SR4, the fifth shift temporary storage unit SR5, the sixth shift temporary storage unit SR6, the seventh shift temporary storage unit SR7, the eighth shift temporary storage unit SR8 to the nth shift Bit temporary storage unit SRn. n is a multiple of 8.

The first shift register unit SR1 is coupled to the first signal line HC1, the second shift register unit SR2 is coupled to the second signal line HC2, and the third shift register unit SR3 is coupled to the third signal line HC3 , the fourth shift register unit SR4 is coupled to the fourth signal line HC4, the fifth shift register unit SR5 is coupled to the fifth signal line HC5, and the sixth shift register unit SR6 is coupled to the sixth signal line HC6, the seventh shift register unit SR7 is coupled to the seventh signal line HC7, and the eighth shift register unit SR8 is coupled to the eighth signal line HC8. The vertical running of the first signal line HC1, the second signal line HC2, the third signal line HC3, the fourth signal line HC4, the fifth signal line HC5, the sixth signal line HC6, the seventh signal line HC7 and the eighth signal line HC8 The wires are arranged on the first metal layer M1, and the horizontal wirings are arranged on the second metal layer.

In the existing structure of the shift register 200, the first shift register unit SR1, the second shift register unit SR2, the third shift register unit SR3, the fourth shift register unit SR4, the fifth shift register unit SR4, and the The bit register unit SR5, the sixth shift register unit SR6, the seventh shift register unit SR7 and the eighth shift register unit SR8 are arranged and connected in a vertical direction, and the first signal line HC1 and the second signal line HC2 The third signal line HC3 , the fourth signal line HC4 , the fifth signal line HC5 , the sixth signal line HC6 , the seventh signal line HC7 and the eighth signal line HC8 are all disposed outside the shift register 200 .

Therefore, the vertical wiring of the first signal line HC1 will cross the horizontal wiring of the second signal line HC2 to the eighth signal line HC8, and the vertical wiring of the second signal line HC2 will be connected to the third signal line HC3 to the eighth signal line. The horizontal wiring of the signal line HC8 is crossed, the vertical wiring of the third signal line HC3 will be crossed with the horizontal wiring of the fourth signal line HC4 to the eighth signal line HC8, and the vertical wiring of the fourth signal line HC4 will be connected with the horizontal wiring of the fourth signal line HC4 to the eighth signal line HC8. The horizontal wiring of the fifth signal line HC5 to the eighth signal line HC8 is crossed, the vertical wiring of the fifth signal line HC5 will be crossed with the horizontal wiring of the sixth signal line HC6 to the eighth signal line HC8, and the sixth signal line The vertical wiring of the line HC6 will cross the horizontal wiring of the seventh signal line HC7 to the eighth signal line HC8, and the vertical wiring of the seventh signal line HC7 will cross the horizontal wiring of the eighth signal line HC8.

When the first metal layer M1 and the second metal layer M2 are respectively at high/low potential or low/high potential, the charge distribution inside the amorphous silicon semiconductor layer between the first metal layer M1 and the second metal layer M2 is uneven, and further As a result, the capacitances of the metal layers M1 and M2 at a high potential are different from those at a low potential, resulting in the phenomenon of bright and dark lines appearing on the panel.

Next, please refer to FIG. 7, which depicts a clock diagram of the clock signal transmitted to each shift register unit in the shift register. It can be seen from the clock diagram that when the first clock signal transmitted by the first signal line HC1 drops from a high level to a low level, the second clock signal and the third signal transmitted by the second signal line HC2 The third clock signal sent by the line HC3 and the fourth clock signal sent by the fourth signal line HC4 are both high level, the fifth clock signal sent by the fifth signal line HC5, and the sixth clock signal sent by the sixth signal line HC6 The clock signal, the seventh clock signal transmitted by the seventh signal line HC7, and the eighth clock signal transmitted by the eighth signal line HC8 are all low-level, so when the existing shift register structure is operating, the first The clock signal will be affected by three high levels of the second clock signal, the third clock signal and the fourth clock signal, and the first clock signal will be affected by the fifth clock signal, the sixth clock signal, The seventh clock signal and the eighth clock signal have a total of four low-level effects, causing the high and low capacitances to not match the panel, resulting in the phenomenon of bright and dark lines.

When the first clock signal transmitted by the first signal line HC1 drops from a high level to a low level, the fifth clock signal transmitted by the fifth signal line HC5 rises from a low level to a high level. When the second clock signal transmitted by the second signal line HC2 drops from a high level to a low level, the sixth clock signal transmitted by the sixth signal line HC6 rises from a low level to a high level. When the third clock signal transmitted by the third signal line HC3 drops from a high level to a low level, the seventh clock signal transmitted by the seventh signal line HC7 rises from a low level to a high level. When the fourth clock signal transmitted by the fourth signal line HC4 drops from a high level to a low level, the eighth clock signal transmitted by the eighth signal line HC8 rises from a low level to a high level.

Specifically, when the first clock signal transmitted by the first signal line HC1 drops from a high level to a low level, the first shift register unit SR1 outputs the first start signal to the fifth shift register unit SR5 , the fifth shift register unit SR5 is turned on in response to the first start signal, and the first shift register unit SR1 is turned off after the first start signal is transmitted. When the second clock signal transmitted by the second signal line HC2 drops from a high level to a low level, the second shift register unit SR2 outputs a second start signal to the sixth shift register unit SR6, so that the first shift register unit SR6 The six shift register units SR6 are turned on in response to the second start signal, and the second shift register unit SR2 is turned off after the second start signal is transmitted.

When the third clock signal transmitted by the third signal line HC3 drops from a high level to a low level, the third shift register unit SR3 outputs a third start signal to the seventh shift register unit SR7, so that the first shift register unit SR7 The seven shift register units SR7 are turned on in response to the third start signal, and the third shift register unit SR3 is turned off after the third start signal is transmitted. When the fourth clock signal transmitted by the fourth signal line HC4 drops from a high level to a low level, the fourth shift register unit SR4 outputs a fourth start signal to the eighth shift register unit SR, so that the The eight shift register units SR8 are turned on in response to the fourth start signal, and the fourth shift register unit SR4 is turned off after the fourth start signal is transmitted.

As can be seen from the foregoing description, in the shift register 200, the fifth clock signal of the fifth shift register unit SR5 does not affect the level of the first clock signal of the first shift register unit SR1, and the The sixth clock signal of the six shift register unit SR6 will not affect the level of the second clock signal of the second shift register unit SR2, and the seventh clock signal of the seventh shift register unit SR7 will not Affect the level of the third clock signal of the third shift register unit SR3, and the eighth clock signal of the eighth shift register unit SR8 will not affect the fourth clock of the fourth shift register unit SR4 signal level. In short, the first clock signal and the fifth clock signal are staggered, the second clock signal and the sixth clock signal are staggered, the third clock signal and the seventh clock signal are staggered, and the fourth clock signal and the seventh clock signal are staggered. The eighth clock signal is staggered.

Please refer to FIG. 8, which depicts an embodiment of the architecture of the shift register of the present invention. In order to solve the situation that the levels of the clock signals affect each other and the bright and dark lines on the panel caused by the crossover between the signal lines, the present invention uses the first shift register unit SR1, the second shift register unit SR1, the second shift temporary The storage unit SR2, the third shift temporary storage unit SR3, and the fourth shift temporary storage unit SR4 are arranged and connected horizontally, and the fifth shift temporary storage unit SR5, the sixth shift temporary storage unit SR6, and the seventh shift temporary storage unit SR5 are connected. The storage unit SR7 and the eighth shift temporary storage unit SR8 are connected horizontally.

In the vertical direction, the present invention vertically arranges and connects the first shift register unit SR1 and the fifth shift register unit SR5, the second shift register unit SR2 and the sixth shift register unit SR2 and the sixth shift register unit SR2. The bit temporary storage unit SR6 is vertically arranged and connected, the third shift temporary storage unit SR3 and the seventh shift temporary storage unit SR7 are vertically arranged and connected, and the fourth shift temporary storage unit SR4 and the eighth shift temporary storage unit SR8 are vertically arranged connect.

Regarding the signal lines, in the present invention, two signal lines whose clock signals do not affect each other are arranged inside the same shift register unit. Specifically, please refer to FIG. 8 again, the first shift register unit SR1 and the fifth shift register unit SR5 include a first signal line HC1 and a fifth signal line HC5, the second shift register unit SR2 and The sixth shift register unit SR6 includes the second signal line HC2 and the sixth signal line HC6, and the third shift register unit SR3 and the seventh shift register unit SR7 include the third signal line HC3 and the seventh signal line The line HC7, the fourth shift register unit SR4 and the eighth shift register unit SR8 include a fourth signal line HC4 and an eighth signal line HC8 inside.

By arranging the signal lines inside the shift register unit, the number of jump lines between each signal line and other signal lines can be reduced from 7 jump lines to 1 jump line, and the level of the clock signal will be affected. The jump lines are reduced from 3 jump lines to 0 jump lines. In other words, the two signal lines set in the same shift register unit will cross each other instead of the signal lines inside other shift register units, and are set in the same shift register unit The clock signals transmitted by the two internal signal lines will not affect each other. Accordingly, through the arrangement of the shift register unit and the position of the signal lines in the shift register of the present invention, not only the problem of bright and dark lines on the panel can be solved, but also because the number of jump lines between the signal lines is greatly reduced, the Reduce the risk of cross-line blast injuries.

In other embodiments, according to the requirements of other panel designs, the number of the horizontally arranged and connected shift register units can also be designed as two shift register units. Under this structure, each shift register unit includes a Four signal lines. In detail, please refer to FIG. 9, which depicts another embodiment of the architecture of the shift register of the present invention. In FIG. 9 , the first shift register unit SR1 and the second shift register unit SR2 are arranged and connected horizontally, the third shift register unit SR3 and the fourth shift register unit SR4 are arranged and connected horizontally, and the fifth shift register unit SR4 is arranged and connected horizontally. The bit temporary storage unit SR5 and the sixth shift temporary storage unit SR6 are arranged and connected horizontally, and the seventh shift temporary storage unit SR7 and the eighth shift temporary storage unit SR8 are arranged and connected horizontally.

The first shift temporary storage unit SR1, the third shift temporary storage unit SR3, the fifth shift temporary storage unit SR5 and the seventh shift temporary storage unit SR7 are vertically arranged and connected, and the first shift temporary storage unit SR1, The three shift register unit SR3, the fifth shift register unit SR5, and the seventh shift register unit SR7 include a first signal line HC1, a third signal line HC3, a fifth signal line HC5, and a seventh signal line HC7 . The second shift register unit SR2, the fourth shift register unit SR4, the sixth shift register unit SR6 and the eighth shift register unit SR8 are vertically arranged and connected, and the two shift register units SR2, the fourth shift register unit SR6 and the eighth shift register unit SR8 are vertically arranged and connected. The shift register unit SR4 , the sixth shift register unit SR6 and the eighth shift register unit SR8 internally include a second signal line HC2 , a fourth signal line HC4 , a sixth signal line HC6 and an eighth signal line HC8 .

In the structure of the shift register 200, the first signal line HC1 is still affected by the high level of the third signal line HC3 when the high level drops to the low level, and the second signal line HC2 drops to the low level when the high level is low. When the level is still affected by the high potential of the fourth signal line HC4, the fifth signal line HC5 will still be affected by the high potential of the seventh signal line HC7 when the high level drops to the low level, and the sixth signal line HC6 When the high level drops to the low level, it will still be affected by the high potential of the eighth signal line HC8. However, compared with the shift register structure in which all the shift register units are arranged and connected vertically, in the shift register 200 in which the two shift register units are arranged and connected horizontally, each signal line is connected to other signals. The number of jump lines between lines is reduced from 7 jump lines to 3 jump lines, and the jump lines that affect the level of the clock signal are reduced from 3 jump lines to 1 jump line.

In other embodiments, according to the requirements of other panel designs, the shift register can be designed to include at least twelve shift register units. When the number of shift register units connected horizontally is six shift register units, each shift register unit includes two signal lines, and the number of shift register units connected horizontally is When there are three shift register units, each shift register unit includes four signal lines.

The third embodiment of the present invention is shown in FIGS. 10 to 14 . The third embodiment is an extension of the first embodiment and the second embodiment. In this embodiment, the shift register 300 is a sixteen-phase shift register. The shift register 300 includes a first shift register unit SR1, a second shift register unit SR2, a third shift register unit SR3, a fourth shift register unit SR4, and a fifth shift register unit SR5, sixth shift temporary storage unit SR6, seventh shift temporary storage unit SR7, eighth shift temporary storage unit SR8, ninth shift temporary storage unit SR9, tenth shift temporary storage unit SR10, eleventh shift temporary storage unit Shift Temporary Storage Unit SR11, Twelfth Shift Temporary Storage Unit SR12, Thirteenth Shift Temporary Storage Unit SR13, Fourteenth Shift Temporary Storage Unit SR14, Fifteenth Shift Temporary Storage Unit SR15, Sixteenth Shift Temporary Storage Unit SR14 The shift temporary storage unit SR16 to the n-th shift temporary storage unit SRn. n is a multiple of 16.

Like the first shift register unit SR1 to the eighth shift register unit SR8 described in the second embodiment are respectively connected to the corresponding signal lines, in this embodiment, the ninth shift register unit SR9 is coupled to The ninth signal line HC9, the tenth shift register unit SR10 is coupled to the tenth signal line HC10, the eleventh shift register unit SR11 is coupled to the eleventh signal line HC11, and the twelfth shift register unit SR12 is coupled to the twelfth signal line HC12, the thirteenth shift register unit SR13 is coupled to the thirteenth signal line HC13, the fourteenth shift register unit SR14 is coupled to the fourteenth signal line HC14, and the thirteenth shift register unit SR14 is coupled to the fourteenth signal line HC14. The fifteenth shift register unit SR15 is coupled to the fifteenth signal line HC15, and the sixteenth shift register unit SR16 is coupled to the sixteenth signal line HC16. Similarly, the ninth signal line HC9, the tenth signal line HC10, the eleventh signal line HC11, the twelfth signal line HC12, the thirteenth signal line HC13, the fourteenth signal line HC14, the fifteenth signal line HC15 and the The vertical wiring of the sixteenth signal line HC16 is arranged on the first metal layer M1, and the horizontal wiring is arranged on the second metal layer.

In the existing structure of the shift register 300, the first shift register unit SR1, the second shift register unit SR2, the third shift register unit SR3, the fourth shift register unit SR4, the fifth shift register unit SR4, the Bit temporary storage unit SR5, sixth shift temporary storage unit SR6, seventh shift temporary storage unit SR7, eighth shift temporary storage unit SR8, ninth shift temporary storage unit SR9, tenth shift temporary storage unit SR10 , the eleventh shift temporary storage unit SR11, the twelfth shift temporary storage unit SR12, the thirteenth shift temporary storage unit SR13, the fourteenth shift temporary storage unit SR14, the fifteenth shift temporary storage unit SR15 , The sixteenth shift register unit SR16 is arranged and connected in a vertical direction, and the first signal line HC1, the second signal line HC2, the third signal line HC3, the fourth signal line HC4, the fifth signal line HC5, the sixth signal line Line HC6, seventh signal line HC7, eighth signal line HC8, ninth signal line HC9, tenth signal line HC10, eleventh signal line HC11, twelfth signal line HC12, thirteenth signal line HC13, tenth signal line The fourth signal line HC14 , the fifteenth signal line HC15 and the sixteenth signal line HC16 are all disposed outside the shift register 300 .

Therefore, the vertical wiring of the first signal line HC1 will cross the horizontal wiring of the second signal line HC2 to the sixteenth signal line HC16, and the vertical wiring of the second signal line HC2 will be connected with the third signal line HC3 to the sixth signal line HC16. The horizontal wiring of the sixteenth signal line HC16 will be crossed, the vertical wiring of the third signal line HC3 will be crossed with the horizontal wiring of the fourth signal line HC4 to the sixteenth signal line HC16, and so on to the fifteenth signal line. The vertical trace of line HC15 will cross the horizontal trace of the sixteenth signal line HC16.

Next, please refer to FIG. 11, which depicts a clock diagram of the clock signal transmitted to each shift register unit in the shift register. It can be seen from the clock diagram that when the first clock signal transmitted by the first signal line HC1 is at a high level, the second clock signal transmitted by the second signal line HC2 and the second clock signal transmitted by the third signal line HC3 The third clock signal, the fourth clock signal sent by the fourth signal line HC4, the fifth clock signal sent by the fifth signal line HC5, the sixth clock signal sent by the sixth signal line HC6, and the seventh signal line HC7 sent The seventh clock signal and the eighth clock signal transmitted by the eighth signal line HC8 are both high-level, so when the existing shift register structure is operating, the first clock signal will receive the second clock signal , High level influence of the third clock signal, the fourth clock signal, the fifth clock signal, the sixth clock signal, the seventh clock signal and the eighth clock signal.

When the first clock signal transmitted by the first signal line HC1 drops from a high level to a low level, the ninth clock signal transmitted by the ninth signal line HC9 rises from a low level to a high level. When the second clock signal transmitted by the second signal line HC2 drops from a high level to a low level, the tenth clock signal transmitted by the tenth signal line HC10 rises from a low level to a high level. When the third clock signal transmitted by the third signal line HC3 drops from a high level to a low level, the eleventh clock signal transmitted by the eleventh signal line HC11 rises from a low level to a high level. When the fourth clock signal transmitted by the fourth signal line HC4 drops from a high level to a low level, the twelfth clock signal transmitted by the twelfth signal line HC12 rises from a low level to a high level. When the fifth clock signal transmitted by the fifth signal line HC5 drops from a high level to a low level, the thirteenth clock signal transmitted by the thirteenth signal line HC13 rises from a low level to a high level. When the sixth clock signal transmitted by the sixth signal line HC6 drops from a high level to a low level, the fourteenth clock signal transmitted by the fourteenth signal line HC14 rises from a low level to a high level. When the seventh clock signal transmitted by the seventh signal line HC7 drops from a high level to a low level, the fifteenth clock signal transmitted by the fifteenth signal line HC15 rises from a low level to a high level. And when the eighth clock signal transmitted by the eighth signal line HC8 drops from a high level to a low level, the sixteenth clock signal transmitted by the sixteenth signal line HC16 rises from a low level to a high level.

Specifically, when the first clock signal transmitted by the first signal line HC1 drops from a high level to a low level, the first shift register unit SR1 outputs a first start signal to the ninth shift register unit SR9 , the ninth shift register unit SR9 is turned on in response to the first start signal, and the first shift register unit SR1 is turned off after the first start signal is transmitted. When the second clock signal transmitted by the second signal line HC2 drops from a high level to a low level, the second shift register unit SR2 outputs a second start signal to the tenth shift register unit SR10, so that the first shift register unit SR1 The ten shift register unit SR10 is turned on in response to the second start signal, and the second shift register unit SR2 is turned off after the second start signal is transmitted. When the third clock signal transmitted by the third signal line HC3 drops from a high level to a low level, the third shift register unit SR3 outputs a third start signal to the eleventh shift register unit SR11, so that the The eleventh shift register unit SR11 is turned on in response to the third start signal, and the third shift register unit SR3 is turned off after the third start signal is transmitted. When the fourth clock signal transmitted by the fourth signal line HC4 drops from a high level to a low level, the fourth shift register unit SR4 outputs a fourth start signal to the twelfth shift register unit SR12, so that the The twelfth shift register unit SR12 is turned on in response to the fourth start signal, and the fourth shift register unit SR4 is turned off after the fourth start signal is transmitted.

When the fifth clock signal transmitted by the fifth signal line HC5 drops from a high level to a low level, the fifth shift register unit SR5 outputs a fifth start signal to the thirteenth shift register unit SR13, so that the The thirteenth shift register unit SR13 is turned on in response to the fifth start signal, and the fifth shift register unit SR5 is turned off after the fifth start signal is transmitted. When the sixth clock signal transmitted by the sixth signal line HC6 drops from a high level to a low level, the sixth shift register unit SR6 outputs a sixth start signal to the fourteenth shift register unit SR14, so that the The fourteenth shift register unit SR14 is turned on in response to the sixth start signal, and the sixth shift register unit SR6 is turned off after the sixth start signal is transmitted. When the seventh clock signal transmitted by the seventh signal line HC7 drops from a high level to a low level, the seventh shift register unit SR7 outputs the seventh start signal to the fifteenth shift register unit SR15, so that the The fifteenth shift register unit SR15 is turned on in response to the seventh start signal, and the seventh shift register unit SR7 is turned off after the seventh start signal is transmitted. When the eighth clock signal transmitted by the eighth signal line HC8 drops from a high level to a low level, the eighth shift register unit SR outputs the eighth start signal to the sixteenth shift register unit SR16, so that the The sixteenth shift register unit SR16 is turned on in response to the eighth start signal, and the eighth shift register unit SR8 is turned off after the eighth start signal is transmitted.

As can be seen from the foregoing description, in the shift register 300, the ninth clock signal of the ninth shift register unit SR9 does not affect the level of the first clock signal of the first shift register unit SR1, and the The tenth clock signal of the tenth shift register unit SR10 will not affect the level of the second clock signal of the second shift register unit SR2, and the eleventh clock signal of the eleventh shift register unit SR11 The level of the third clock signal of the third shift register unit SR3 will not be affected, and the twelfth clock signal of the twelfth shift register unit SR12 will not affect the level of the third clock signal of the fourth shift register unit SR4. The level of the four clock signals, the thirteenth clock signal of the thirteenth shift register unit SR13 will not affect the level of the fifth clock signal of the fifth shift register unit SR5, the fourteenth shift The fourteenth clock signal of the register unit SR14 will not affect the level of the sixth clock signal of the sixth shift register unit SR6, and the fifteenth clock signal of the fifteenth shift register unit SR15 will not affect the level of the sixth clock signal of the sixth shift register unit SR6. Affecting the level of the seventh clock signal of the seventh shift register unit SR7 and the sixteenth clock signal of the sixteenth shift register unit SR16 will not affect the eighth clock signal of the eighth shift register unit SR8 The level of the clock signal.

In short, the first clock signal and the ninth clock signal are staggered, the second clock signal and the tenth clock signal are staggered, the third clock signal and the eleventh clock signal are staggered, and the fourth clock signal and the eleventh clock signal are staggered. The twelfth clock signal is staggered, the fifth clock signal and the thirteenth clock signal are staggered, the sixth clock signal and the fourteenth clock signal are staggered, the seventh clock signal and the fifteenth clock signal are staggered, And the eighth clock signal and the sixteenth clock signal are staggered.

Please refer to FIG. 12, which depicts an embodiment of the architecture of the shift register of the present invention. In order to solve the situation that the levels of the clock signals affect each other and the bright and dark lines on the panel caused by the crossover between the signal lines, the present invention uses the first shift register unit SR1, the second shift register unit SR1, the second shift temporary The storage unit SR2, the third shift temporary storage unit SR3, the fourth shift temporary storage unit SR4, the fifth shift temporary storage unit SR5, the sixth shift temporary storage unit SR6, the seventh shift temporary storage unit SR7 and the The eight shift temporary storage units SR8 are horizontally connected, and the ninth shift temporary storage unit SR9, the tenth shift temporary storage unit SR10, the eleventh shift temporary storage unit SR11, the twelfth shift temporary storage unit SR12, The thirteenth shift temporary storage unit SR13 , the fourteenth shift temporary storage unit SR14 , the fifteenth shift temporary storage unit SR15 , and the sixteenth shift temporary storage unit SR16 are arranged and connected horizontally.

In the vertical direction, the present invention vertically arranges and connects the first shift register unit SR1 and the ninth shift register unit SR9, the second shift register unit SR2 and the tenth shift register unit SR2 and the tenth shift register unit SR2. The bit register unit SR10 is arranged and connected vertically, the third shift register unit SR3 and the eleventh shift register unit SR11 are vertically arranged and connected, the fourth shift register unit SR4 and the twelfth shift register unit SR12 are vertically arranged Arrangement and connection, the fifth shift register unit SR5 and the thirteenth shift register unit SR13 are vertically arranged and connected, the sixth shift register unit SR6 and the fourteenth shift register unit SR14 are vertically arranged and connected, and the seventh shift register unit SR14 is vertically arranged and connected. The bit register unit SR7 and the fifteenth shift register unit SR15 are vertically arranged and connected, and the eighth shift register unit SR8 and the sixteenth shift register unit SR16 are vertically arranged and connected.

Regarding the signal lines, in the present invention, two signal lines whose clock signals do not affect each other are arranged inside the same shift register unit. Specifically, please refer to FIG. 12 again, the first shift register unit SR1 and the ninth shift register unit SR9 include a first signal line HC1 and a ninth signal line HC9, the second shift register unit SR2 and The tenth shift register unit SR10 includes a second signal line HC2 and a tenth signal line HC10, and the third shift register unit SR3 and the eleventh shift register unit SR11 include a third signal line HC3 and a tenth signal line. A signal line HC11, the fourth shift register unit SR4 and the twelfth shift register unit SR12 include the fourth signal line HC4 and the twelfth signal line HC12, the fifth signal line HC5 and the thirteenth signal line HC13 , the sixth shift register unit SR6 and the fourteenth shift register unit SR14 internally include the sixth signal line HC6 and the fourteenth signal line HC14, the seventh shift register unit SR7 and the fifteenth shift register unit The unit SR15 includes the seventh signal line HC7 and the fifteenth signal line HC15, and the eighth shift register unit SR8 and the sixteenth shift register unit SR16 include the eighth signal line HC8 and the sixteenth signal line HC16. .

By arranging the signal lines inside the shift register unit, the number of jump lines between each signal line and other signal lines can be reduced from 15 jump lines to 1 jump line, and the level of the clock signal will be affected. The number of spans is reduced from 7 spans to 0 spans. In other words, by connecting the shift register units corresponding to the signal lines whose clock signals can influence each other in a horizontal arrangement, and setting up two signal lines within the same shift register unit that the clock signals will not influence each other , which can not only avoid the occurrence of bright and dark lines on the panel, but also reduce the risk of cross-line explosion.

In other embodiments, in response to the requirements of other panel designs, the number of the horizontally arranged and connected shift register units can also be designed to be four shift register units. In this structure, each shift register unit includes Four signal lines. In detail, please refer to FIG. 13, which depicts another embodiment of the architecture of the shift register of the present invention. In FIG. 13 , the first shift register unit SR1 to the fourth shift register unit SR4 are arranged and connected horizontally, the fifth shift register unit SR5 to the eighth shift register unit SR8 are arranged and connected horizontally, and the ninth shift register unit SR5 is arranged and connected horizontally. The bit temporary storage unit SR9 to the twelfth shift temporary storage unit SR12 are arranged and connected horizontally, and the thirteenth shift temporary storage unit SR13 to the sixteenth shift temporary storage unit SR16 are arranged and connected horizontally.

The first shift register unit SR1, the fifth shift register unit SR5, the ninth shift register unit SR9, and the thirteenth shift register unit SR13 are vertically arranged and connected, and the first signal line HC1, The fifth signal line HC5, the ninth signal line HC9 and the thirteenth signal line HC13. The second shift register unit SR2, the sixth shift register unit SR6, the tenth shift register unit SR10 and the fourteenth shift register unit SR14 are vertically arranged and connected, and the second signal line HC2, The sixth signal line HC6, the tenth signal line HC10 and the fourteenth signal line HC14. The third shift register unit SR3, the seventh shift register unit SR7, the eleventh shift register unit SR11, and the fifteenth shift register unit SR15 are vertically arranged and connected, and include a third signal line HC3 inside them , the seventh signal line HC7, the eleventh signal line HC11 and the fifteenth signal line HC15. The fourth shift register unit SR4, the eighth shift register unit SR8, the twelfth shift register unit SR12, and the sixteenth shift register unit SR16 are vertically arranged and connected, and include a fourth signal line HC4 therein , the eighth signal line HC8, the twelfth signal line HC12 and the sixteenth signal line HC16.

In the structure of the shift register 300, the first signal line HC1 is still affected by the high level of the fifth signal line HC5 when the high level drops to the low level, and the second signal line HC2 is affected by the high level when the high level drops to the low level. When the low level is still affected by the high level of the sixth signal line HC6, the third signal line HC3 will still be affected by the high level of the seventh signal line HC7 when the high level drops to the low level. The fourth signal The line HC4 will still be affected by the high level of the eighth signal line HC8 when the high level drops to the low level, and the ninth signal line HC9 will still be affected by the thirteenth signal line HC13 when the high level drops to the low level The influence of the high level, and the tenth signal line HC10 will still be affected by the high level of the fourteenth signal line HC14 when the high level drops to the low level, and the eleventh signal line HC11 is reduced to the low level when the high level The level will still be affected by the high level of the fifteenth signal line HC15, and the twelfth signal line HC12 will still be affected by the high level of the sixteenth signal line HC16 when the high level drops to the low level. However, compared with the shift register structure in which all the shift register units are arranged and connected vertically, in the shift register 300 in which the four shift register units are arranged and connected horizontally, each signal line is connected to other signals. The number of jump lines between lines is reduced from 15 jump lines to 3 jump lines, and the jump lines that affect the level of the clock signal are reduced from 7 jump lines to 1 jump line.

In addition, in other embodiments, the number of the horizontally arranged and connected shift register units can also be designed as two shift register units. Under this structure, each shift register unit includes eight signal lines. In detail, please refer to FIG. 14, which depicts another embodiment of the architecture of the shift register of the present invention. In FIG. 14, the first shift register unit SR1 and the second shift register unit SR2 are arranged and connected horizontally, the third shift register unit SR3 and the fourth shift register unit SR4 are arranged and connected horizontally, and the fifth shift register unit SR4 is arranged and connected horizontally. The bit temporary storage unit SR5 and the sixth shift temporary storage unit SR6 are horizontally arranged and connected, the seventh shift temporary storage unit SR7 and the eighth shift temporary storage unit SR8 are horizontally arranged and connected, and the ninth shift temporary storage unit SR9 and the tenth temporary storage unit are arranged and connected horizontally. The shift register unit SR10 is arranged and connected horizontally, the eleventh shift register unit SR11 and the twelfth shift register unit SR12 are arranged and connected horizontally, the thirteenth shift register unit SR13 and the fourteenth shift register unit The unit SR14 is arranged and connected horizontally, and the fifteenth shift temporary storage unit SR15 and the sixteenth shift temporary storage unit SR16 are arranged and connected horizontally.

The first shift temporary storage unit SR1, the third shift temporary storage unit SR, the fifth shift temporary storage unit SR5, the seventh shift temporary storage unit SR7, the ninth shift temporary storage unit SR9, the eleventh shift The temporary storage unit SR11, the thirteenth shift temporary storage unit SR13 and the fifteenth shift temporary storage unit SR15 are vertically arranged and connected, and the inside thereof includes a first signal line HC1, a third signal line HC3, a fifth signal line HC5, The seventh signal line HC7, the ninth signal line HC9, the eleventh signal line HC11, the thirteenth signal line HC13, and the fifteenth signal line HC15. The second shift temporary storage unit SR2, the fourth shift temporary storage unit SR4, the sixth shift temporary storage unit SR6, the eighth shift temporary storage unit SR8, the tenth shift temporary storage unit SR10, the twelfth shift temporary storage unit The temporary storage unit SR12, the fourteenth shift temporary storage unit SR14, and the sixteenth shift temporary storage unit SR16 are vertically arranged and connected, and the inside thereof includes a second signal line HC2, a fourth signal line HC4, a sixth signal line HC6, The eighth signal line HC8, the tenth signal line HC10, the twelfth signal line HC12, the fourteenth signal line HC14, and the sixteenth signal line HC16.

In the structure of the shift register 300, the first signal line HC1 is still affected by the high level of the third signal line HC3, the fifth signal line HC5, and the seventh signal line HC7 when the high level drops to the low level , the second signal line HC2 will still be affected by the high level of the fourth signal line HC4, the sixth signal line HC6, and the eighth signal line HC8 when the high level drops to the low level. When the level drops to a low level, it will still be affected by the high level of the eleventh signal line HC11, the thirteenth signal line HC13 and the fifteenth signal line HC15, and the tenth signal line HC10 drops to a low level when the high level is low. It will still be affected by the high level of the twelfth signal line HC12, the fourteenth signal line HC14 and the sixteenth signal line HC16. However, compared with the shift register structure in which all the shift register units are arranged and connected vertically, in the shift register 300 in which the four shift register units are arranged and connected horizontally, each signal line is connected to other signals. The number of jump lines between lines is reduced from 15 jump lines to 7 jump lines, and the jump lines that affect the level of the clock signal are reduced from 7 jump lines to 3 jump lines.

It should be noted that, in addition to the above-mentioned shift register structure including at least eight, twelve or sixteen shift register units, the present invention horizontally connects the shift register units and assigns signal lines to the shift register units. The structure inside the register unit is also applicable to shift registers including other numbers of shift register units.

To sum up, in the structure of the shift register of the present invention, by connecting the circuit of the shift register unit laterally and distributing the signal lines to the inside of the shift register unit, the charge in the amorphous silicon semiconductor layer is reduced due to the Uneven distribution causes capacitance mismatch and panel light and dark lines. In addition, through the structure of the shift register of the present invention, in the circuit layout, the number of wirings can be reduced to reduce the risk of cross-line explosion, and the shift register units can be increased after the horizontally arranged shift register units are stacked. The height of the unit to accommodate other taller elements.

The above-mentioned embodiments are only used to illustrate the embodiments of the present invention and to illustrate the technical characteristics of the present invention, and are not used to limit the protection scope of the present invention. Any changes or equality arrangements that can be easily accomplished by those skilled in the art fall within the claimed scope of the present invention, and the scope of protection of the present invention should be subject to the scope of the patent application.

100: Shift register 200: Shift register 300: Shift register HC1: The first signal line HC2: The second signal line HC3: The third signal line HC4: Fourth signal line HC5: Fifth signal line HC6: The sixth signal line HC7: Seventh signal line HC8: Eighth signal line HC9: ninth signal line HC10: Tenth signal line HC11: Eleventh signal line HC12: The twelfth signal line HC13: The thirteenth signal line HC14: The fourteenth signal line HC15: The fifteenth signal line HC16: The sixteenth signal line SR1: The first shift temporary storage unit SR2: The second shift temporary storage unit SR3: The third shift temporary storage unit SR4: Fourth shift temporary storage unit SR5: Fifth shift temporary storage unit SR6: sixth shift temporary storage unit SR7: seventh shift temporary storage unit SR8: Eighth shift temporary storage unit SR9: ninth shift temporary storage unit SR10: Tenth shift temporary storage unit SR11: Eleventh shift temporary storage unit SR12: The twelfth shift temporary storage unit SR13: Thirteenth shift temporary storage unit SR14: Fourteenth shift temporary storage unit SR15: The fifteenth shift temporary storage unit SR16: Sixteenth shift temporary storage unit SRn: nth shift temporary storage unit SRn-1: n-1th shift temporary storage unit SRn-2: n-2 shift temporary storage unit SRn-3: n-3 shift temporary storage unit SRn-4: n-4th shift temporary storage unit SRn-5: n-5th shift temporary storage unit SRn-6: n-6th shift temporary storage unit SRn-7: n-7th shift temporary storage unit

Figure 1 depicts a schematic diagram of a signal line jumper; 2 depicts a cross-sectional view of a jumper and a schematic diagram of the charge distribution of the first metal layer and the second metal layer with high/low potential or low/high potential, respectively; FIG. 3 depicts a schematic diagram of the structure of a conventional shift register; 4 depicts a clock diagram of clock signals transmitted to each shift register unit in the shift register; 5 depicts an embodiment of the architecture of the shift register of the present invention; 6 depicts a schematic diagram of the architecture of a conventional shift register; 7 depicts a clock diagram of the clock signals transmitted to each shift register unit in the shift register; 8 depicts an embodiment of the architecture of the shift register of the present invention; 9 depicts an embodiment of the architecture of the shift register of the present invention; FIG. 10 depicts a schematic diagram of the structure of a conventional shift register; FIG. 11 depicts a clock diagram of clock signals transmitted to each shift register unit in the shift register; Figure 12 depicts an embodiment of the architecture of the shift register of the present invention; Figure 13 depicts an embodiment of the architecture of the shift register of the present invention; and Figure 14 depicts an embodiment of the architecture of the shift register of the present invention.

none

200: Shift register

HC1: The first signal line

HC2: The second signal line

HC3: The third signal line

HC4: Fourth signal line

HC5: Fifth signal line

HC6: The sixth signal line

HC7: Seventh signal line

HC8: Eighth signal line

SR1: The first shift temporary storage unit

SR2: The second shift temporary storage unit

SR3: The third shift temporary storage unit

SR4: Fourth shift temporary storage unit

SR5: Fifth shift temporary storage unit

SR6: sixth shift temporary storage unit

SR7: seventh shift temporary storage unit

SR8: Eighth shift temporary storage unit

SRn: nth shift temporary storage unit

SRn-1: n-1th shift temporary storage unit

SRn-2: n-2 shift temporary storage unit

SRn-3: n-3 shift temporary storage unit

Claims (8)

A shift register, comprising: a first shift register unit coupled to a first signal line; a second shift register unit coupled to a second signal line; a third shift register a temporary storage unit, coupled to a third signal line; a fourth shift temporary storage unit, coupled to a fourth signal line; a fifth shift temporary storage unit, coupled to a fifth signal line; a a sixth shift register unit coupled to a sixth signal line; a seventh shift register unit coupled to a seventh signal line; and an eighth shift register unit coupled to a first shift register unit Eight signal lines; wherein, the first shift register unit, the second shift register unit, the third shift register unit and the fourth shift register unit are laterally connected, and the fifth shift register The temporary storage unit, the sixth shift temporary storage unit, the seventh shift temporary storage unit and the eighth shift temporary storage unit are horizontally connected; wherein, the first shift temporary storage unit and the fifth shift temporary storage unit The storage unit includes the first signal line and the fifth signal line, the second shift register unit and the sixth shift register unit include the second signal line and the sixth signal line, and the third shift register unit includes the second signal line and the sixth signal line. The shift register unit and the seventh shift register unit include the third signal line and the seventh signal line, and the fourth shift register unit and the eighth shift register unit include the first shift register unit. The fourth signal line and the eighth signal line. The shift register of claim 1, wherein the first The shift register unit and the fifth shift register unit are vertically connected, the second shift register unit and the sixth shift register unit are vertically connected, the third shift register unit and the seventh shift register unit are vertically connected The bit temporary storage unit is vertically connected, and the fourth shift temporary storage unit and the eighth shift temporary storage unit are vertically connected. The shift register of claim 1, wherein when a first clock signal transmitted by the first signal line drops from a high level to a low level, the fifth signal line transmits a first clock signal The fifth clock signal rises from the low level to the high level; when a second clock signal transmitted by the second signal line falls from the high level to the low level, the sixth signal line transmits the A sixth clock signal rises from the low level to the high level; when a third clock signal transmitted by the third signal line falls from the high level to the low level, the seventh signal line Sending a seventh clock signal rises from the low level to the high level; and when a fourth clock signal sent by the fourth signal line falls from the high level to the low level, the first An eighth clock signal transmitted by the eight signal lines rises from the low level to the high level. The shift register as claimed in claim 3, wherein when a first clock signal transmitted by the first signal line drops from a high level to a low level, the first shift register unit outputs the output a first start signal to the fifth shift register unit; when a second clock signal sent by the second signal line drops from the high level to the low level, the second shift register unit Output a second start signal to the sixth shift register unit; when a third clock signal sent by the third signal line drops from the high level to the low level, the first The three-shift register unit outputs a third start signal to the seventh shift register unit; and when a fourth clock signal transmitted by the fourth signal line drops from the high level to the low level , the fourth shift register unit outputs a fourth start signal to the eighth shift register unit. A shift register, comprising: a first shift register unit coupled to a first signal line; a second shift register unit coupled to a second signal line; a third shift register a temporary storage unit, coupled to a third signal line; a fourth shift temporary storage unit, coupled to a fourth signal line; a fifth shift temporary storage unit, coupled to a fifth signal line; a a sixth shift register unit, coupled to a sixth signal line; a seventh shift register unit, coupled to a seventh signal line; an eighth shift register unit, coupled to an eighth signal line signal line; a ninth shift register unit, coupled to a ninth signal line; a tenth shift register unit, coupled to a tenth signal line; an eleventh shift register unit, coupled to connected to an eleventh signal line; a twelfth shift register unit coupled to a twelfth signal line; a thirteenth shift register unit coupled to a thirteenth signal line; a A fourteenth shift register unit coupled to a fourteenth signal line; a fifteenth shift register unit coupled to a fifteenth signal line; and a sixteenth shift register unit, is coupled to a sixteenth signal line; wherein, the first shift register unit, the second shift register unit, The third shift temporary storage unit, the fourth shift temporary storage unit, the fifth shift temporary storage unit, the sixth shift temporary storage unit, the seventh shift temporary storage unit, and the eighth shift temporary storage unit The temporary storage unit is horizontally connected, and the ninth shift temporary storage unit, the tenth shift temporary storage unit, the eleventh shift temporary storage unit, the twelfth shift temporary storage unit, the thirteenth shift temporary storage unit The bit temporary storage unit, the fourteenth shift temporary storage unit, the fifteenth shift temporary storage unit and the sixteenth shift temporary storage unit are horizontally connected; wherein, the first shift temporary storage unit and the The inside of the nine shift register unit includes the first signal line and the ninth signal line, the second shift register unit and the tenth shift register unit include the second signal line and the tenth signal line , the third shift register unit and the eleventh shift register unit include the third signal line and the eleventh signal line, the fourth shift register unit and the twelfth shift register unit The storage unit includes the fourth signal line and the twelfth signal line, the fifth shift register unit and the thirteenth shift register unit include the fifth signal line and the thirteenth signal line, The sixth shift register unit and the fourteenth shift register unit include the sixth signal line and the fourteenth signal line, the seventh shift register unit and the fifteenth shift register unit The inside of the unit includes the seventh signal line and the fifteenth signal line, and the eighth shift register unit and the sixteenth shift register unit include the eighth signal line and the sixteenth signal line. The shift register of claim 5, wherein the first shift register unit and the ninth shift register unit are vertically connected, the second shift register unit and the tenth shift register unit cells are connected vertically, the third shift The temporary storage unit and the eleventh shift temporary storage unit are vertically connected, the fourth shift temporary storage unit and the twelfth shift temporary storage unit are vertically connected, the fifth shift temporary storage unit and the thirteenth shift temporary storage unit are vertically connected The shift temporary storage unit is vertically connected, the sixth shift temporary storage unit and the fourteenth shift temporary storage unit are vertically connected, the seventh shift temporary storage unit and the fifteenth shift temporary storage unit are vertically connected, and the eighth shift temporary storage unit and the sixteenth shift temporary storage unit are vertically connected. The shift register of claim 5, wherein when a first clock signal transmitted by the first signal line drops from the high level to the low level, the ninth signal line transmits a first clock signal The ninth clock signal rises from the low level to the high level; when a second clock signal transmitted by the second signal line falls from the high level to the low level, the tenth signal line transmits the A tenth clock signal rises from the low level to the high level; when a third clock signal transmitted by the third signal line falls from the high level to the low level, the eleventh signal An eleventh clock signal transmitted by the line rises from the low level to the high level; when a fourth clock signal transmitted by the fourth signal line falls from the high level to the low level, the A twelfth clock signal transmitted by the twelfth signal line rises from the low level to the high level; when a fifth clock signal transmitted by the fifth signal line falls from the high level to the low level When the thirteenth signal line transmits a thirteenth clock signal from the low level to the high level; when a sixth clock signal transmitted by the sixth signal line falls from the high level When the low level is reached, a fourteenth clock signal sent by the fourteenth signal line rises from the low level to the high level; when a seventh clock signal sent by the seventh signal line is sent by the When the high level drops to the low level, the fifteenth A fifteenth clock signal transmitted by the signal line rises from the low level to the high level; and when an eighth clock signal transmitted by the eighth signal line falls from the high level to the low level , a sixteenth clock signal transmitted by the sixteenth signal line rises from the low level to the high level. The shift register as claimed in claim 7, wherein when a first clock signal transmitted by the first signal line drops from a high level to a low level, the first shift register unit outputs A first start signal is sent to the ninth shift register unit; when a second clock signal sent by the second signal line drops from the high level to the low level, the second shift register unit outputting a second start signal to the tenth shift register unit; when a third clock signal sent by the third signal line drops from the high level to the low level, the third shift temporary The storage unit outputs a third start signal to the eleventh shift register unit; when a fourth clock signal sent by the fourth signal line drops from the high level to the low level, the fourth The shift register unit outputs a fourth start signal to the twelfth shift register unit; when a fifth clock signal transmitted by the fifth signal line drops from the high level to the low level, The fifth shift register unit outputs a fifth start signal to the thirteenth shift register unit; when a sixth clock signal transmitted by the sixth signal line drops from the high level to the low level When the 6th shift register unit outputs a sixth start signal to the 14th shift register unit; when a seventh clock signal transmitted by the seventh signal line drops from the high level to At the low level, the seventh shift register unit outputs a seventh start signal to the fifteenth shift register unit; and when the eighth signal line transmits an eighth clock signal from the high level down to the At a low level, the eighth shift register unit outputs an eighth start signal to the sixteenth shift register unit.

Images