KR101521656B1 - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device is disclosed.

The liquid crystal display according to the present invention can reduce power consumption by selectively applying charge sharing according to the gradation of input data.

Gradation, Charge Sharing, Power Consumption

Description

[0001] Liquid crystal display device [0002]

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of reducing power consumption.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal cells according to a video signal. An active matrix type liquid crystal display device is advantageous for displaying moving images by forming switching elements for each liquid crystal cell. As a switching element, a thin film transistor (TFT) is mainly used.

The liquid crystal display device is driven by an inversion method for reducing flicker and afterimage by periodically reversing the polarity of data charged in the liquid crystal cell. The inversion method includes a line inversion method for inverting the polarity of data between adjacent liquid crystal cells in the vertical line direction and a dot inversion method for inverting the polarity of data between adjacent liquid crystal cells in the horizontal line direction. Of these inversion methods, the dot inversion method is mainly selected because flicker hardly appears in the vertical and horizontal directions.

In the dot inversion method, the polarities of data supplied to the adjacent liquid crystal cells in the vertical direction are opposite to each other, and the polarities of data supplied to the adjacent liquid crystal cells in the horizontal direction are opposite to each other. The polarity of the data is inverted every frame. Such a dot-inversion method is most widely applied in liquid crystal displays at present because flicker is minimized in both vertical and horizontal directions.

In the 2-dot inversion method, the polarity of the data is inverted in units of two dots in the horizontal and vertical directions. The 2-dot inversion method has an advantage in that the power consumption is lower than that in the 1-dot inversion method. In this two-dot inversion system, a liquid crystal cell to which a positive voltage (or a negative voltage) rising from a negative voltage (or a positive voltage) is applied and a positive voltage (or a positive voltage Or a negative voltage) is applied to the liquid crystal cell, the charged amount of data charged in the liquid crystal cell becomes different. This is because the rising time (or the polling time) of the positive voltage (or the negative voltage) rising from the negative voltage (or the positive voltage) is long while the positive voltage The negative voltage) is relatively short in the rising time (or the polling time). Due to the difference in the charging characteristics, a luminance difference occurs even if the data voltage is of the same gradation.

Therefore, in a liquid crystal display device driven by a 2-dot inversion method, a charge sharing scheme is applied in order to equalize charging characteristics between adjacent two-dot units of pixels. The charge sharing scheme is a scheme in which a charge share voltage, which is an intermediate voltage between a positive data voltage and a negative data voltage, is supplied to a data line in accordance with a source enable (SOE) signal. The charge characteristics between the pixels of two dot units to which the data voltages of the same polarity are applied through the charge sharing scheme are equal to each other but the consumption current of the data driver is increased and the power consumption of the liquid crystal display device is increased .

An object of the present invention is to provide a liquid crystal display device capable of reducing power consumption by selectively applying a charge sharing scheme according to the gradation of input data.

A liquid crystal display according to an embodiment of the present invention includes a liquid crystal panel in which a plurality of gate lines and a plurality of data lines are arranged, a gate driver for driving the plurality of gate lines, A timing controller for generating a control signal for controlling the gate driver and the data driver, comparing the gray level of data supplied from an external system with a reference value, and determining whether the charge driver is driven in accordance with a result of the comparison, And the reference value is a black and white gradation in which it is difficult to judge image quality defects.

According to another aspect of the present invention, there is provided a liquid crystal display including a liquid crystal panel in which a plurality of gate lines and a plurality of data lines are arranged, a gate driver for driving the plurality of gate lines, and a plurality of output buffers, A data driver for supplying a data signal to the plurality of data lines through an output buffer, and a timing controller for controlling timing of the gate and the data driver and for supplying data from the external system to the data driver, Wherein the data driver receives data from the timing controller and compares the gray level value of the data with a preset reference value to determine whether or not charge sharing is driven according to a result of the comparison and the reference value includes black and white An analog corresponding to the gradation A pressure.

According to the present invention, it is determined whether the gradation of input data belongs to a gradation level at which a picture quality defect is judged by the naked eye, and the charge sharing scheme is selectively applied according to a result of the determination to reduce power consumption.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 102 in which a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm are arranged and displays an image, A gate driver 104 for supplying a scan signal to the plurality of gate lines GL1 to GLn, a data driver 106 for supplying a data signal to the plurality of data lines DL1 to DLm, And a timing controller 108 for controlling the timings of the driver 104 and the data driver 106. The liquid crystal display device according to the present invention is driven by a 2-dot inversion method.

The liquid crystal panel 102 includes pixels formed in regions divided by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. Each of these pixels includes a thin film transistor TFT formed at an intersection between a corresponding gate line GL and a corresponding data line DL and a thin film transistor TFT formed between the thin film transistor TFT and the common electrode Vcom, (Clc). The thin film transistor TFT switches the pixel data voltage to be supplied to the corresponding liquid crystal cell Clc from the corresponding data line DL in response to the gate scan signal on the corresponding gate line GL.

The gate driver 104 correspondingly supplies a plurality of scan signals to the plurality of gate lines GL1 to GLn in response to the gate control signals GCS from the timing controller 108. [ The plurality of scan signals cause the plurality of gate lines GL1 to GLn to sequentially enable one horizontal synchronization signal period.

In response to the data control signals DCS from the timing controller 108, the data driver 106 generates a plurality of pixel data voltages whenever one of the plurality of gate lines GL1 to GLn is enabled And supplies them to the plurality of data lines DL1 to DLm on the liquid crystal panel 102, respectively. To this end, the data driver 106 inputs pixel data for one line from the timing controller 108, and converts input pixel data of one line into an analog pixel data voltage using a gamma voltage set .

The timing controller 108 controls the gate driver 104 to control the gate driver 104 using synchronous signals Vsync and Hsync supplied from an external system and a data enable signal DE and a clock signal CLK. And generates a data control signal (DCS) for controlling the signal (GCS) and the data driver (106). The timing controller 108 sorts data supplied from an external system and supplies the sorted data to the data driver 106. Further, the timing controller 108 compares the gray level of the aligned data with a reference value, and generates a signal according to the comparison result, and supplies the signal to the data driver 106.

Specifically, the timing controller 108 generates the gate and data control signals (GCS) by using synchronous signals (Vsync, Hsync) supplied from an external system, a data enable (DE) signal, and a clock signal (CLK) A data alignment unit 111 for aligning the data supplied from the external system, a control signal generation unit 109 for generating a control signal, DCS, And a data gray scale comparator 113 for comparing the gray scale values of the data set to the gray scale value and generating a comparison signal according to the comparison result.

The data gradation comparator 113 compares the gradation value of the aligned data from the data aligner 111 with a preset gradation value. The reference value is a gradation value having the highest level in a data gradation level range in which image quality failure can not be visually judged. For example, in the case of data corresponding to 0 to 20 black gradations and 43 to 63 white gradations in black data, it is difficult to visually judge the image quality deficiency by the naked eye. For convenience, black gradation data will be described as an example. The reference value may be different depending on the model of the liquid crystal panel.

Therefore, the data gradation comparator 113 generates a comparison signal having a high logic level when data of a gradation level higher than the data of 20 gradations set as the reference value is input. The data gradation comparator 113 generates a comparison signal having a logic low when data having a level lower than or equal to the reference value is input. The comparison signal generated by the data gray level comparator 113 is supplied to the output terminal of the data driver 106.

The comparison signal is supplied to a charge sharing (not shown) portion formed at an output terminal of the data driver 106 and becomes a charge sharing control signal CSC for controlling charge sharing of the data driver 106.

2, the data driver 106 includes a latch unit 110, a level shifter unit 112, a digital-analog converter (DAC) unit 114, a plurality of buffers 116-1 And a charge sharing unit 122 that is connected between the plurality of buffers 116-1 to 116-m and the plurality of data lines DL1 to DLm.

The latch unit 110 includes a plurality of latches 110-1 to 110-m corresponding to the plurality of data lines DL1 to DLm and each of the latches 110-1 to 110- And supplies the sampled data signal to the level shifter 112. The level shifter 112 receives the sampled data signal from the timing controller 108,

The level shifter 112 is also comprised of a plurality of level shifters 112-1 to 112-m corresponding to the plurality of data lines DL1 to DLm. The level shifters 112-1 to 112- m converts the level of the data signal supplied from the latches 110-1 to 110-m and supplies the converted data signal to the digital-analog converter (DAC) 114.

The DAC 114 further includes a plurality of digital-to-analog converters 114-1 to 114-m corresponding to the plurality of data lines DL1 to DLm, and each of the digital-analog converters 114-1 to 114- The converters 114-1 to 114-m convert the data signals supplied from the level shifters 112-1 to 112-m into analog data voltages. The converted analog data voltage is supplied to a plurality of buffers 116-1 to 116-m corresponding to the plurality of digital-analog converters 114-1 to 114-m, respectively.

The plurality of buffers 116-1 to 116-m are connected to the plurality of data lines DL1 to DLm to generate analog data supplied from the plurality of digital-analog converters 114-1 to 114- And supplies a voltage to the plurality of data lines DL1 to DLm. Each of the plurality of buffers 116-1 to 116-m is connected to the data lines DL1 to DLm through the first switch element SW1 of the charge sharing unit 122, Respectively.

The charge sharing unit 122 includes a first switch element SW1 and an adjacent data line DL connected between the plurality of buffers 116-1 to 116-m and the plurality of data lines DL1 to DLm, And a second switch element SW2 connected between the first switch element SW1 and the second switch element SW2.

The first switch element SW1 is turned on / off according to a source output enable signal SOE of the data control signal DCS and the second switch element SW2 is turned on / (ON / OFF) by the charge sharing control signal CSC generated by the data gradation comparator 113 of the first embodiment.

The first switch element SW1 is turned on when the source output enable (SOE) signal is high and turned off when it is low. When the first switch element SW1 is turned on, analog data voltages from the plurality of buffers 116-1 to 116-m are applied to the plurality of data lines DL1 to DLm through the first switch element SW1, DLm).

The second switch element SW2 is turned on when the charge sharing control signal CSC is high logic and turned off when the charge sharing control signal CSC is low logic. When the second switch element SW2 is turned on, the plurality of data lines DL1 to DLm are short-circuited and driven by a charge sharing scheme. That is, the charge sharing unit 122 applies the charge sharing scheme by shorting the plurality of data lines DL1 to DLm only when the second switch element SW2 is turned on.

When the second switch element SW2 is turned on, the charge sharing control signal CSC is in a high logic state, and the charge sharing control signal CSC in a high logic state is an input And the gradation of the data is larger than the reference value (data of 20 gradations). As a result, when the gradation of the input data is larger than a reference value (20-gradation data) in which the image quality defect is not visually determined, the data driver 106 applies the charge sharing scheme.

When the second switching device SW2 is turned off, the charge sharing control signal CSC is low logic, and the charge sharing control signal CSC of the low logic is input When the gradation of the data is smaller than or equal to the reference value (20-gradation data). As a result, the data driver 106 does not apply the charge sharing scheme when the gradation of the input data is smaller than or equal to a reference value (20-gradation data) in which the image quality defect is not visually judged.

As a result, the liquid crystal display according to the present invention compares the gradation of the input data with the gradation of the data set as the reference value and selectively applies the charge sharing scheme according to the comparison result, thereby continuously performing the charge sharing The power consumption can be reduced as compared with the conventional liquid crystal display device using the method.

3 is a view illustrating a liquid crystal display device according to another embodiment of the present invention.

3, the liquid crystal display according to another exemplary embodiment of the present invention includes a liquid crystal panel 102 (see FIG. 3) for displaying an image, in which a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm are arranged, A gate driver 104 for supplying a scan signal to the plurality of gate lines GL1 to GLn; a data driver 206 for supplying a data signal to the plurality of data lines DL1 to DLm; And a timing controller 208 for controlling the timings of the gate driver 104 and the data driver 206. The liquid crystal display device according to the present invention is driven by a 2-dot inversion method.

The liquid crystal display device according to another embodiment of the present invention has the same components as the timing controller (108 in FIG. 1) and the data driver (106 in FIG. 1) of the liquid crystal display shown in FIG. Therefore, for the sake of convenience, description of the same components as those of the liquid crystal display device shown in FIG. 1 in the description of the liquid crystal display device according to another embodiment of the present invention will be omitted.

The timing controller 208 controls the gate driver 104 to control the gate driver 104 using synchronous signals Vsync and Hsync supplied from an external system and a data enable signal DE and a clock signal CLK. And generates a data control signal (DCS) for controlling the signal (GCS) and the data driver (106). In addition, the timing controller 108 arranges data supplied from an external system and supplies the sorted data to the data driver 106.

The data driver 206 is controlled by a data control signal DCS supplied from the timing controller 208 and supplies a data signal supplied from the timing controller 208 to the data lines DL1 to DLm do. The data driver 206 includes a latch 210, a level shifter 212, a digital-to-analog converter (DAC) 214, a plurality of buffers 216-1 to 216-m, And a charge sharing unit 222 connected between the buffers 216-1 to 216-m and the plurality of data lines DL1 to DLm. The data driver 206 further includes a reference gradation level data setting unit 218. [

The latch 210 and the level shifter 212, the digital-to-analog converter (DAC) 214 and the plurality of buffers 216-1 to 216-m correspond to the data driver 106, and therefore, a description thereof will be omitted.

The reference gradation level data setting unit 218 sets data having a high gradation level in a data gradation level range in which image quality failure can not be visually determined. The reference gradation level data set by the reference gradation level data setting unit 218 is supplied to the charge sharing unit 222. [ For example, in the case of data corresponding to 0 to 20 black gradations and 43 to 63 white gradations of black data, it is difficult to visually judge the image quality deficiency by the naked eye. For convenience, black gradation will be described as an example. The reference level level data may be different depending on the model of the liquid crystal panel.

Therefore, the reference gradation level data set in the reference gradation level data setting unit 218 can be 20 gradations. At this time, the reference gradation level data set in the reference gradation level data setting unit 218 is an analog voltage.

The charge sharing unit 222 includes a first switch element SW1 and an adjacent data line DL connected between the plurality of buffers 216-1 to 216-m and the plurality of data lines DL1 to DLm, And a second switch element SW2 connected between the first switch element SW1 and the second switch element SW2. The charge sharing unit 222 compares the reference gradation level data set from the reference gradation level data setting unit 218 with the analog data voltage supplied through the first switch element SW1, And further includes a plurality of comparators 220-1 to 220-m-1 for generating comparison signals. The number of the plurality of comparators 220-1 to 220-m-1 is provided corresponding to the number of the second switch elements SW2.

Each of the plurality of comparators 220-1 to 220-m-1 receives the analog data voltage supplied from the corresponding data line DL and the reference gradation level data supplied from the reference gradation level data setting unit 218 And a comparison signal having a specific logic is generated according to the comparison result. The comparison signals generated by the plurality of comparators 220-1 to 220-m-1 are supplied to the corresponding second switch element SW2.

The comparators 220-1 to 220-m-1 compare the analog data voltages supplied from the corresponding data lines DL with the reference gradation level data, . The comparators 220-1 to 220-m-1 may select a logic low level when the analog data voltage supplied from the corresponding data line DL is smaller than or equal to the reference gradation level data Thereby generating a comparison signal. The comparison signal of the high or low logic generated in each of the plurality of comparators 220-1 to 220-m-1 is supplied to the corresponding second switch element SW2.

The first switch element SW1 is turned on / off according to a source output enable signal SOE of the data control signal DCS and the second switch element SW2 is turned on / (ON / OFF) by the comparison signal generated by the comparators 220-1 to 220-m-1.

The first switch element SW1 is turned on when the source output enable (SOE) signal is high and turned off when it is low. When the first switch element SW1 is turned on, an analog data voltage from the plurality of buffers 216-1 to 216-m is applied to the data lines DL1 to DLm through the first switch element SW1, DLm).

The second switch element SW2 is turned on when the comparison signal is high logic and off when the comparison signal is low logic. When the second switch element SW2 is turned on, the plurality of data lines DL1 to DLm are short-circuited and driven by a charge sharing scheme. That is, the charge sharing unit 122 applies the charge sharing scheme by shorting the plurality of data lines DL1 to DLm only when the second switch element SW2 is turned on.

The data driver 206 applies the charge sharing scheme when the gradation of the input data is larger than the reference gradation level data on which the image quality defect is not visually judged. The data driver 206 does not apply the charge sharing scheme when the gradation of the input data is smaller than or equal to the reference gradation level data whose visual quality defect is not visually determined.

As a result, the liquid crystal display device according to the present invention compares the gradation level of the input data with the reference gradation level data and selectively applies the charge sharing scheme according to the comparison result to continuously apply the charge sharing scheme The power consumption can be reduced as compared with the conventional liquid crystal display device using the liquid crystal display device.

1 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.

Figure 2 shows the data driver of Figure 1;

3 is a view illustrating a liquid crystal display device according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

102: liquid crystal panel 104: data driver

106, 206: Data driver 108, 208: Timing controller

109: control signal generation unit 110, 210: latch unit

111: data arranging unit 112, 212: level shifter unit

113: Data gradation comparing unit 114, 214: DAC

116-1 to 116-m, 216-1 to 216-m: Buffers 122 and 222: Charge-

218: Reference gradation level data setting units 220-1 to 220-m-1:

Claims (6)

delete delete A liquid crystal panel in which a plurality of gate lines and a plurality of data lines are arranged; A gate driver for driving the plurality of gate lines; A data driver for supplying a data signal to the plurality of data lines; And And a timing controller for controlling timing of the gate and the data driver and for arranging data supplied from an external system and supplying the sorted data to the data driver, The data driver includes: A plurality of output buffers corresponding one-to-one to each of the plurality of data lines; A charge sharing unit comprising first switch elements electrically connecting the output buffer and the data line and second switch elements electrically connecting two adjacent data lines; A reference value setting unit storing a reference value; And A plurality of comparators for comparing each of the analog data voltages output from each of the plurality of output buffers with the reference value and generating a comparison signal according to a result of the comparison to control ON / OFF of each of the second switch elements; Including, Wherein the reference value is an analog voltage corresponding to black and white gradations that are difficult to determine image quality defects. The method of claim 3, The data driver includes: A latch unit for sampling, storing, and supplying the data signal supplied from the timing controller; A level shifter for converting the level of the data signal supplied from the latch unit; And A digital-to-analog converter for converting a level-converted data signal in the level shifter into an analog data voltage and supplying the analog data voltage to the plurality of output buffers;  The liquid crystal display device further comprising: 5. The method of claim 4, Wherein the plurality of comparison units generate a comparison signal having a logic high when the analog data voltages supplied from the plurality of output buffers are greater than the reference value and the analog data voltages supplied from the plurality of output buffers And generates a comparison signal of a logic low when the comparison result is smaller than or equal to the comparison result. 6. The method of claim 5, Wherein the reference value is an analog voltage corresponding to 0 to 20 black gradations and 43 to 63 white gradations.

Images