KR100880934B1 - Liquid Crystal Display Device And Driving Method Thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof in which the amount of voltage supplied to the liquid crystal cell can be equalized.

The driving method of the liquid crystal display device includes a liquid crystal for driving the liquid crystal cells such that a plurality of data lines and a plurality of gate lines intersect, liquid crystal cells are disposed at each intersection, and two or more adjacent liquid crystal pixel cells are charged with the same polarity. A method of driving a display device, comprising: generating a first data output enable signal and a first polarity control signal; Generating a second data output enable signal having a period longer than the first data output enable signal; Generating a second polarity control signal having a shorter period than the first polarity control signal by using the first data output enable signal and the first polarity control signal; Supplying a video signal to the data lines by controlling a data driver with the first data output enable signal and the second polarity control signal; And sequentially supplying gate signals to the gate lines.

Description

Liquid Crystal Display Device And Driving Method Thereof}             

1 illustrates a liquid crystal cell formed at an intersection of a data line and a gate line.

FIG. 2 is a block diagram illustrating a data driver for supplying a video signal applied to the data line shown in FIG. 1.

3 is a diagram illustrating a polar pattern of data signals supplied to liquid crystal cells in a one-dot inversion driving method.

4 is a diagram illustrating a polar pattern of data signals supplied to liquid crystal cells in a two-dot inversion driving method.

5 is a waveform diagram illustrating a gate signal and a video signal output according to a polarity control signal and a data output enable signal according to the polarity pattern shown in FIG. 4;

6 is a block diagram showing a liquid crystal display device according to the present invention;

FIG. 7 is a block diagram illustrating a data driver shown in FIG. 6. FIG.

FIG. 8 is a diagram illustrating a second data output enable signal generator shown in FIG. 7. FIG.                 

FIG. 9 is a waveform diagram illustrating an operation process of a second data output enable signal generator shown in FIG. 8; FIG.

FIG. 10 is a diagram illustrating a second polarity control signal generator shown in FIG. 7. FIG.

FIG. 11 is a waveform diagram illustrating an operation process of a second polarity control signal generation unit illustrated in FIG. 10.

Fig. 12 is a waveform diagram showing a video signal generated by the waveforms shown in Figs. 9 and 11;

<Description of Symbols for Main Parts of Drawings>

11,41: shift resist 12,42: first latch portion

13,43: second latch portion 14,44: digital-to-analog converter

15,45 buffer 16,46 multiplexer

17,47: Data register 18,48: Gamma voltage generator

19,49: polarity control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof in which the amount of voltage supplied to a liquid crystal cell can be equalized.

In general, a liquid crystal display (hereinafter referred to as "LCD") displays an image in response to a video signal using a pixel matrix arranged at an intersection between gate lines and data lines. Each of the pixels is a liquid crystal cell LC for adjusting light transmittance according to a video signal as shown in FIG. 1, and a thin film transistor for switching a video signal to be supplied to the liquid crystal cell LC from the data line DL. 2 and 4 and a gate line GL for supplying a gate driving signal so that a video signal supplied from the data line DL can be supplied to the liquid crystal cell LC. . In addition, the LCD is provided with gate and data drivers (not shown) for supplying driving signals to the gate line GL and the data line DL.

Referring to FIG. 2, the data driver 6 includes a first latch portion 12 connected to the data register 17, and a digital-analog connected between the second latch portion 13 and the data lines DL. A converter (hereinafter referred to as "DAC") 14, a buffer 15 and a multiplexer 16, and a shifter register 11 for addressing the first latch portion 12 are provided.

The first latch unit 12 is connected to the output terminal of the shift register 11 and sequentially driven according to the logic value of the output signal of the shift register 11 to sequentially store pixel data from the data register 17. do. Then, the data stored in the first latch portion 12 is moved to the second latch portion 13, the next data enters the first latch portion 12. When data enters the second latch unit 13 of the eight data drivers in this manner, the pixel data is simultaneously input in accordance with the SOE signal and transferred to the DAC unit 14. The DAC unit 14 converts the pixel data from the second latch unit 13 into an analog signal by sampling the gamma signal from the gamma voltage generator 18 and converts each of the converted pixel signals into a liquid crystal panel. Are supplied to each of the data lines DL. To this end, the DAC unit 14 consists of a PDAC and an NDAC. The PDAC inputs the gamma high voltage GMH from the gamma voltage generator 18 to sample the gamma high voltage GMH according to the pixel data from the second latch unit 13 to output the buffer 15 to the buffer 15. do. The NDAC inputs the gamma low voltage GML from the gamma voltage generation unit 18 and samples the gamma low voltage GML according to the pixel data from the second latch unit 13 to output the buffer 15 to the buffer 15. do. The multiplexer 16 selects one of the output signals of the PDAC and the NDAC according to the polarity control signal POL from the polarity control unit 19. The analog signals output from the multiplexer 16 are supplied to the data lines DL, respectively.

In the liquid crystal display, three driving methods such as a frame inversion method, a line inversion method, and a dot inversion method are mainly used to drive the liquid crystal cells on the liquid crystal panel. The frame inversion scheme reverses the polarity of the data signal supplied to the liquid crystal cells whenever the frame is changed. In the line inversion scheme, polarities of data signals supplied to liquid crystal cells are reversed according to a line on the liquid crystal panel, that is, a gate line. In the dot inversion scheme, data signals having opposite polarities are supplied to adjacent liquid crystal cells, and polarities of data signals supplied to the liquid crystal cells are inverted for each frame. Of these three methods, the dot-inversion method is adapted to the frame and line-inversion methods by supplying an arbitrary liquid crystal cell with a data signal having a polarity opposite to the data signals supplied to adjacent liquid crystal cells in the vertical and horizontal directions. Compared with this, it provides an image of excellent image quality. Accordingly, the dot inversion method is mainly used in recent years. The dot inversion method is divided into a 1 dot inversion method and a 2 dot inversion method.

As shown in FIG. 3, the one-dot inversion driving method includes liquid crystal cells LC positioned adjacent to each other with the gate line GL interposed therebetween, and liquid crystals positioned adjacent to each other with the data line DL interposed therebetween. The data signals of opposite polarities are supplied to all of the cells LC to display an image.

Accordingly, the 1-dot inversion method consumes a lot of power because the polarities of all adjacent liquid crystal cells are different. To compensate for this drawback, a two-dot inversion scheme is used.

A two-dot inversion scheme is described in detail with reference to FIGS. 4 and 5 as follows. The data driver 6 receiving the polarity control signal POL and the data output enable signal SOE generates the video signal DP in synchronization with the falling edge (or rising edge) of the data output enable signal SOE. The generated video signal DP is supplied to the data line DL. At this time, when the polarity control signal POL is positive polarity, two video signals DP are continuously supplied. The gate driver (not shown) is supplied with a gate output enable signal having the same frequency as the data output enable signal SOE, and the gate driver uses the gate output enable signal supplied thereto to provide the gate signal GP. Is generated, and the gate signal GP is sequentially supplied to the gate line GL. In this two-dot inversion driving method, as shown in FIG. 4, the positive, positive, negative, and negative polarities are alternately repeated on the vertical axis, and the positive and negative signals alternate on the horizontal axis. Is repeated. Therefore, the power consumption can be reduced compared to the one-dot inversion method in which opposite polarities are supplied to all of the liquid crystal cells LC.

However, in the conventional two-dot inversion method, the voltage value supplied to the A terminal A shown in FIG. 1 and the voltage value supplied to the B terminal B are different. This will be described in detail on the assumption that the positive video signal DP is supplied to the current data line DL and the voltage of 0 V or 0 V or less is supplied to the data line DL before. First, the gate signal GP is supplied to the n-th gate line GL, and the positive video signal DP synchronized with the gate signal GP is supplied to the data line DL. At this time, since the voltage of 0 V or 0 V or less is supplied to the data line DL before the positive video signal DP is input to the data line DL, the positive video signal DP is connected to the A terminal A. FIG. When supplied, a certain rise time is required. After the video signal DP is supplied to the A terminal A, the gate signal GP is supplied to the nth gate line GL, and the positive line video is synchronized with the gate signal GP to the data line DL. The signal DP is supplied. At this time, since the positive video signal DP is supplied to the data line DL, no voltage rise time is required. In other words, the load applied to the data line DL when the video signal DP is applied to the terminal A, and the data line DL when the video signal DP is applied to the B terminal B are applied. The load will be different. Accordingly, the voltage difference C is generated between the voltage applied to the A terminal A and the voltage applied to the B terminal B as shown in FIG. 5. As a result, even when the same video signal DP is supplied, the same voltage is not applied to the liquid crystal cell LC positioned adjacent to each other and receiving a video signal having the same polarity. Thus, a problem arises in that a luminance difference between lines occurs.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof in which the amount of voltage supplied to the liquid crystal cell can be equalized.

In order to achieve the above object, a method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of data lines and a plurality of gate lines that cross each other, and liquid crystal cells are disposed at each intersection thereof, and at least two adjacent liquid crystal pixel cells are adjacent to each other. CLAIMS What is claimed is: 1. A method of driving a liquid crystal display device for driving the liquid crystal cells so that they are charged with the same polarity, the method comprising: generating a first data output enable signal and a first polarity control signal; Generating a second data output enable signal having a period longer than the first data output enable signal; Generating a second polarity control signal having a shorter period than the first polarity control signal by using the first data output enable signal and the first polarity control signal; Supplying the video signal to the data lines by controlling the data driver with the first data output enable signal and the second polarity control signal; And sequentially supplying gate signals to the gate lines.
An LCD according to an exemplary embodiment of the present invention includes a plurality of data lines to which data is supplied, and a plurality of gate lines to which a gate signal is supplied and orthogonal to the data lines, and at least two polarities of the data. A driving device for a liquid crystal display device inverting at a gate line period, comprising: a control unit for generating a first data output enable signal and a first polarity control signal; A second SOE generation unit generating a second data output enable signal having a period longer than the first data output enable signal; A second polarity control unit generating a second polarity control signal having a shorter period than the first polarity control signal by using the first data output enable signal and the first polarity control signal; A data driver for supplying the video signal to the data lines under control of the first data output enable signal and the second polarity control signal; And a gate driver sequentially supplying a gate signal to the gate lines under the control of the controller.
In order to achieve the above object, the liquid crystal display according to the present invention has a gate driver for sequentially supplying a gate signal synchronized with data to the gate lines, and the data continuously supplied with the same polarity is turned on / off every gate line period. And a data driver to be turned off.

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And a controller for controlling the data driver and the gate driver.

The data driver may include a first control signal generator for generating a second data output enable signal based on a data output enable signal generated from a controller, and a polarity control signal and a second data output enable signal from the controller. And a second control signal generator for generating a two-polarity control signal.

The data driver includes a shifter register unit configured to sequentially output a sampling signal in response to control of a controller, a latch unit sequentially latching and simultaneously outputting n pixel data input from the controller in response to a control and sampling signal of the controller; Selects one of the positive and negative pixel signals in response to the second polarity control signal; and a digital-analog converter for converting n pixel data into positive and negative pixel signals using an input gamma voltage. and a multiplexer for outputting n pixel signals.

The first control signal generator includes a flip-flop to which a data output enable signal is applied to a clock terminal, a counter to which an output signal of the flip-flop is applied, an output signal of the counter, and an output signal of the flip-flop to which the data output enable signal is applied. An or gate and an X or gate to which an output signal of the or gate and an output signal of the counter are applied are provided.

The second control signal generator is characterized in that formed by the X-gate.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 12.

Referring to FIG. 6, a liquid crystal display according to the present invention supplies video data to a digital video card 31 for converting analog data into digital video data and to data lines DL of the liquid crystal panel 36. The data driver 33, the gate driver 34 for sequentially driving the gate lines GL of the liquid crystal panel 36, the data driver 33 supplying data, and the gate signal of the gate driver 34. A control unit 32 for controlling the supply is provided.

In the liquid crystal panel 36, liquid crystal is injected between two glass substrates, and the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for supplying an image signal input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the gate terminal of the TFT is connected to the gate line GL, and the source terminal of the TFT is connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The digital video card 31 converts an analog input video signal into digital video data and detects a synchronization signal included in the video signal.

The control unit 32 supplies the red (R), green (G) and blue (B) digital video data from the digital video card 31 to the data driver 33. In addition, the controller 32 generates the dot clock Dclk and the gate start pulse GSP using the horizontal / vertical synchronization signals H and V input from the digital video card 31 to generate the data driver 33. The data supply timing and the gate signal supply timing of the gate driver 34 are controlled. The dot clock Dclk is supplied to the data driver 33, and the gate start pulse GSP is supplied to the gate driver 34.

The gate driver 34 includes a shift register (not shown) that sequentially generates scan pulses in response to a gate start pulse (GSP) input from the controller 32, and a voltage of the scan pulses at a level suitable for driving the liquid crystal cell. And a level shifter (not shown) for shifting. In response to the scan pulse input from the gate driver 34, video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

The data driver 33 receives a dot clock Dclk together with video data of red (R), green (G), and blue (B) from the control unit 32. The data driver 33 latches the red (R), green (G) and blue (B) digital video data in synchronization with the dot clock Dclk, and then corrects the latched data in accordance with the gamma voltage Vγ. Done. The data driver 33 converts the data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.                     

As illustrated in FIG. 7, the data driver 33 includes a first latch portion 42 connected to the data register 47 and a second portion connected between the first latch portion 42 and the data line DL. A latch portion 43, a digital-to-analog conversion portion (hereinafter referred to as "DAC" 44), a buffer 45 and a multiplexer 46 are provided.

The first latch portion 42 is connected to the output terminal of the shift register 41, and is sequentially driven according to the logic value of the output signal of the shift register 41 to sequentially store pixel data from the data register 47. do. Then, the data stored in the first latch portion 42 is moved to the second latch portion 43, and the next data enters the first latch portion 42. When data enters the second latch unit 43 of the eight data drivers in this manner, the pixel data is simultaneously input in accordance with the SOE signal and transferred to the DAC unit 44.

The DAC unit 44 converts the pixel data from the second latch unit 43 into an analog signal by sampling the gamma signal from the gamma voltage generator 48 and converts each of the converted pixel signals into a liquid crystal panel. Supply to each of the data lines (DL) of (36). To this end, the DAC unit 44 is composed of a PDAC and an NDAC. The PDAC receives the gamma high voltage GMH from the gamma voltage generator 48 and samples the gamma high voltage GMH according to the pixel data from the second latch unit 43 and outputs the gamma high voltage GMH to the buffer 45. . The NDAC receives the gamma low voltage GML from the gamma voltage generator 48 and samples the gamma low voltage GML according to the pixel data from the second latch unit 43 and outputs the gamma low voltage GML to the buffer 45. .

The multiplexer 46 selects and outputs any one of the PDAC and the NDAC according to the second polarity control signal POL2 generated from the second polarity control unit 52. The analog signals output from this multiplexer 46 are supplied to data lines DL1, DL2, DL3 ...., respectively.

The second polarity controller 52 controls the second data output enable signal SOE2 of the second data output enable signal generator 51 and the first polarity control signal POL1 of the first polarity controller 49. By using the second polarity control signal POL2 is generated.

The second data output enable signal generator 51 generates a second data output enable signal SOE2 using the first data output enable signal SOE1. As shown in FIG. 8, the second data output enable signal generator 51 includes a deflip-flop 53, a counter 54, an or gate 55, and an x or gate 56.

The first data output enable signal SOE1 is input to the clock terminal CLK of the flip-flop 53, and the input terminal D and the inverting output terminal Q 'of the flip-flop 53 are connected to each other. It is. Accordingly, when the first data output enable signal SOE1 is input to the clock terminal CLK of the flip-flop 53, the flip-flop 53 may have a high level output signal as shown in FIG. 9. Is output. Then, when the first data output enable signal SOE1 is input after one horizontal period 1H, a low level output signal is output.

The output signal Qs of the flip-flop 53 is input to the counter 54. The counter 54 delays and outputs the output signal Qs of the flip-flop 53 by a period corresponding to the first data output enable signal SOE1. The output signal Ks of the counter 54 and the output signal Qs of the flip-flop 53 are input to the two input terminals of the or gate 55. The output signal As of the or gate 55 and the output signal Ks of the counter 54 are input to two input terminals of the X or gate 56 to generate the second data output enable signal SOE2. . The second data output enable signal SOE2 has a second horizontal period 2H, and the first data output enable signal SOE1 is formed to have a first horizontal period 1H.

The second data output enable signal SOE2 is applied to the second polarity controller 52 as shown in FIG. 7. As shown in FIG. 10, the second polarity controller 52 is formed of an exclusive OR gate (XOR) so that the first polarity control signal POL1 together with the second data output enable signal SOE2 is provided. Is entered. As shown in FIG. 11, the second polarity control signal POL2 generated by the second polarity controller 52 has a logic value different from that of the first polarity control signal POL1 and the second data output enable signal SOE2. When it has, it has a high level value, and when it has the same logic value, it has a low level value.

The data driver 33 receiving the second polarity control signal POL2 and the first data output enable signal SOE1 is positioned on the falling edge of the first data output enable signal SOE1 as shown in FIG. 12. In synchronization, a video signal is generated, and the generated video signal is supplied to the data line DL.

By the second polarity control signal for controlling the polarity of the video signal, the video signal is formed at the same time as the turn-on time of the gate signal by the gate signal. Accordingly, the voltages charged in the liquid crystal cells positioned adjacent to each other and receiving the video signals having the same polarity are the same.

 As described above, the liquid crystal display and the driving method thereof according to the embodiment of the present invention are located adjacent to each other by matching the data pulse and the gate pulse on / off time to charge the liquid crystal cell receiving data pulses of the same polarity. The voltage to be formed is the same. As a result, it is possible to suppress the difference in luminance between lines during two-dot inversion driving.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A driving method of a liquid crystal display device which drives the liquid crystal cells such that a plurality of data lines and a plurality of gate lines intersect, liquid crystal cells are disposed at each intersection thereof, and two or more adjacent liquid crystal pixel cells are charged with the same polarity. Generating a first data output enable signal and a first polarity control signal; Generating a second data output enable signal having a period longer than the first data output enable signal; Generating a second polarity control signal having a shorter period than the first polarity control signal by using the first data output enable signal and the first polarity control signal; Supplying a video signal to the data lines by controlling a data driver with the first data output enable signal and the second polarity control signal; And And sequentially supplying gate signals to the gate lines. The method of claim 1, Supplying the first data output enable signal and the first polarity control signal to the data driver; And And generating the second data output enable signal by using the first data output enable signal. delete And a plurality of gate lines supplied with data, a plurality of gate lines supplied with a gate signal, and orthogonal to the data lines, and inverting polarities of the data at least two gate line periods. To A controller for generating a first data output enable signal and a first polarity control signal; A second SOE generation unit generating a second data output enable signal having a period longer than the first data output enable signal; A second polarity control unit generating a second polarity control signal having a shorter period than the first polarity control signal by using the first data output enable signal and the first polarity control signal; A data driver for supplying a video signal to the data lines under the control of the first data output enable signal and the second polarity control signal; And And a gate driver for sequentially supplying a gate signal to the gate lines under the control of the controller. delete The method of claim 4, wherein And the second SOE generation unit and the second polarity control unit are built in the data driver. The method of claim 6, The data driver, A shifter register unit configured to sequentially output a sampling signal in response to a control of the controller; A latch unit for sequentially latching and simultaneously outputting n pixel data input from the controller in response to the control of the controller and the sampling signal; A digital-to-analog converter for converting the n pixel data into positive and negative pixel signals using an input gamma voltage; And a multiplexer for selecting and outputting any one of the positive and negative pixel signals in response to the second polarity control signal. The method of claim 6, The second SOE generation unit A flip-flop to which the first data output enable signal is applied to a clock terminal; A counter to which the output signal of the flip-flop is applied; An or gate to which the output signal of the counter and the output signal of the flip-flop are applied; And an X-orgate to which an output signal of the or gate and an output signal of the counter are applied. The method of claim 6, And the second polarity controller includes an exclusive gate configured to perform an exclusive OR operation on the first data output enable signal and the first polarity control signal.

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