KR100849098B1 - Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of minimizing electromagnetic waves (EMI) and power consumption.

The liquid crystal display includes a system driver which generates a low voltage differential signal (LVDS) in which a plurality of data are compressed, and rearranges the compressed data through the low voltage differential signal into red, green, and blue data according to a liquid crystal panel. A column driver configured to include a data alignment unit and to supply the rearranged data to the data lines of the liquid crystal panel, and a timing controller to control driving of the column driver, wherein the column driver includes: An address shift resist for generating address information under control; a first latch for temporarily storing red, green, and blue data rearranged through the data alignment unit; and a first latch at a position corresponding to address information from the address shift resist. 1 Stores and saves the data supplied from the latch A second latch for outputting one long line of data; a digital-analog converter for selecting gamma voltages corresponding to the data from the second latch; and buffering the gamma voltages from the digital-analog converter. And an output buffer for supplying the data lines.

According to the present invention, a plurality of data signals from the system driver are directly applied to the column driver without going through a timing controller using the compressed LVDS. As a result, the number of lines between the system driver and the column driver is reduced, and the data signal transmission path is simplified, thereby preventing transmission errors or data malfunction due to electromagnetic interference caused by data transmission. In addition, the data signal transmission path is simplified to lower power consumption.

Description

Liquid Crystal Display Device             

1 is a block diagram showing a conventional liquid crystal display device.

2 is a waveform diagram showing a conventional LVDS.

3 is a block diagram showing a conventional timing controller in detail.

4 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a block diagram illustrating in detail a timing controller according to an exemplary embodiment of the present invention.

Figure 6 is a block diagram showing in detail the column driver according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1,31: System driver 2,32: Timing controller

3,33: column driver 4,34: gamma voltage generator

5,35: low driver 6,36: liquid crystal panel

12,50: data sorter 14,54: timing control signal generator

16,56: polarity control signal generator

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of minimizing electromagnetic waves and power consumption.

In general, a liquid crystal display (LCD) displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. Among the liquid crystal display devices, an active matrix type in which switching elements are provided for each liquid crystal cell is suitable for displaying a moving image. In an active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used as a switching element.

The liquid crystal display device includes a system driver 1 for converting into digital video data as shown in FIG. 1, a column driver 3 for supplying a data signal to data lines DL of the liquid crystal panel 6, and a liquid crystal panel. A row driver 5 for sequentially driving the gate lines GL of (6), a timing controller 2 for controlling the column driver 3 and the row driver 5, and a column driver 3 A gamma voltage generator 4 is provided to supply gamma voltage to the gamma voltage generator.

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 6 is formed such that the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image signal input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the gate terminal of the TFT is connected to the gate line GL, and the source terminal is connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

An interface (not shown) is disposed between the digital video card (not shown) and the timing controller 2 disposed inside the system driver 1. This interface converts an analog input video signal into a digital video signal and detects a synchronization signal included in the video signal. The data signals R, G, and B of the digital video card disposed inside the system driver are supplied to the timing controller 2 by using a low voltage differential signal (LVDS). . The LVDS compresses several data signals in one line and is input to the timing controller 2. The data signals R, G, and B transmitted from the system driver 1 to the timing controller 2 inevitably increase in frequency as the image resolution increases, that is, as the number of pixels increases. As the frequency increases, the electromagnetic interference (EMI) phenomenon becomes severe. In order to solve the electromagnetic wave phenomenon, a method of transmitting a differential signal has been proposed, and the differential signal is a signal having a relationship as shown in FIG. 2 having the same amplitude and opposite phase. When adjacent lines of about 0.5V positive signal S + and about -0.5V negative signal S- are simultaneously used, the electric field generated in each adjacent line is canceled by interaction. Specifically, when the positive signal S + is converted from the low level to the high level, the negative signal S− is converted from the high level to the low level. At this time, the directions of the currents flowing in the two lines are opposite to each other, and the electric field is canceled by forming the opposite direction of the electric field by the Fleming law. The offset of the electric field minimizes the emission of the electric field. Accordingly, the system driver 1 can supply the data signals R, G, and B to the timing controller 2 at the original voltage.

The timing controller 2 supplies the data signals of red (R), green (G), and blue (B) from the system driver 1 to the column driver 3. In addition, the timing controller 2 generates the dot clock Dclk and the gate start pulse GSP using the horizontal / vertical synchronization signals H and V input from the system driver 1 to generate the column driver 3 and the column driver 3. The row driver 5 is timing-controlled. The dot clock Dclk is supplied to the column driver 3, and the gate start pulse GSP is supplied to the row driver 5.

The row driver 5 is also referred to as a gate driver, and includes a shift register that sequentially generates scan pulses in response to a gate start pulse GSP input from the timing controller 2, and a scan pulse voltage suitable for driving a liquid crystal cell. Level shifter and the like for shifting to the level. In response to the scan pulse input from the row driver 5, the data signal on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

The column driver 3 is also called a data driver, and a dot clock Dclk is input to the column driver 3 together with data signals of red (R), green (G), and blue (B) from the timing controller 2. do. The column driver 3 latches the red (R), green (G), and blue (B) data signals in synchronization with the dot clock Dclk, and then gammas the latched data signals (R, G, B). Correction is made according to the voltage Vγ. The column driver 3 converts the data signal corrected by the gamma voltage Vγ into an analog data signal and supplies the data line DL by one line.

The gamma voltage generator 4 generates a gamma voltage Vγ corresponding to the grayscale value of the data in consideration of the electrical and optical characteristics of the liquid crystal panel 6. The gamma voltage Vγ is a voltage divided by the gamma voltage generator 4 corresponding to the gradation level. Therefore, the gamma voltage Vγ generated from the gamma voltage generator 4 is set to have a different voltage level in response to the gray level value selected in the expressible range.

Referring to FIG. 3, the timing controller 2 generates predetermined signals for driving the liquid crystal display using the LVDS inputted from the system driver 1 and the vertical and horizontal synchronization signals H and V. Referring to FIG.

The data sorter 12 generates aligned red (R), green (G), and blue (B) data signals by using LVDS in which a plurality of data signals input from the system driver 1 are compressed. This sorted data signal is supplied to the column drive 3.

The timing control signal generator 14 generates timing control signals using the vertical and horizontal synchronization signals H and V input from the system driver 1. These timing control signals are supplied to the column drive 3 and the row driver 5.

The control signals supplied to the column driver 3 among these timing control signals are source sampling clock ("SSC") and source output enable ("SOE"). And a source start pulse (hereinafter referred to as "SSP").

Control signals supplied to the low driver 5 include a gate shift clock (hereinafter referred to as "GSC"), a gate output enable (hereinafter referred to as "GOE"), and a gate start pulse (gate start). Pulse: hereinafter referred to as "GSP").

The polarity control signal generator 16 receives the horizontal and vertical synchronization signals H and V to generate the polarity control signal and supplies the same to the column drive 3.

Polarity control signals include polarity reverse ("POL") and data polarity selection ("REV").

The liquid crystal display device supplies data signals and control signals from the system driver 1 to the column driver 3 and the low driver 5 through the timing controller 2. Accordingly, there is a problem that a transmission error occurs due to an increase in the transmission path and transmission time of the data signal. In addition, there is a problem that the transmission path is increased, the power consumption of the timing controller 2 for processing the data signal increases. In addition, the higher the resolution, the higher the operating frequency, and accordingly, various control signals and data signals increase, thereby increasing the number of lines in the printed circuit board for applying various control signals and data signals to the LCD module.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of minimizing electromagnetic waves and power consumption.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes a system driver for generating a low voltage differential signal (LVDS) in which a plurality of data are compressed, and the data compressed through the low voltage differential signal. A column driver for realigning the data with the red, green, and blue data according to the data, and supplying the rearranged data to the data lines of the liquid crystal panel; and a timing controller for controlling driving of the column driver. The column driver includes: an address shift resist for generating address information under the control of the timing controller, a first latch for temporarily storing red, green, and blue data rearranged through the data alignment unit; At a position corresponding to address information from the shift resist. A second latch for storing data supplied from the first latch and outputting one line of stored data; a digital-to-analog converter for selecting gamma voltages corresponding to the data from the second latch; And an output buffer for buffering the gamma voltages from the analog transformer to the data lines.
According to an exemplary embodiment of the present invention, a liquid crystal display device includes a system driver for generating a low voltage differential signal (LVDS) in which a plurality of data are compressed, and red, green, and blue colors corresponding to the liquid crystal panel. A timing driver for controlling driving of the column driver, a column driver configured to provide a data sorting unit to reorder the data of the LCD panel, and to supply the rearranged data to data lines of the liquid crystal panel; A polarity control signal generator for generating a polarity control signal for controlling the polarity of data supplied to the data lines using the synchronization signals input from the system driver, and the synchronization signals input from the system driver; To generate data control signals for controlling the column driver And a timing control signal generator.

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Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 6.

Referring to FIG. 4, in the liquid crystal display according to the present invention, data signals are directly input from the system driver 31 and the system driver 31 for converting the digital data into data lines DL of the liquid crystal panel 6. Column driver 33 for supplying a data signal to the?, A row driver 35 for sequentially driving the gate lines GL of the liquid crystal panel 36, and a column driver 33 and the row driver 35 ) And a gamma voltage generator 34 for supplying a gamma voltage to the column driver 33.

In the liquid crystal panel 36, liquid crystal is injected between two glass substrates, and the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image signal input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the gate line GL is connected to the gate terminal of the TFT, and the data line DL is connected to the source terminal of the TFT. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

An interface (not shown) is disposed between the digital video card (not shown) disposed in the system driver 31 and the timing controller 32. This interface converts an analog input video signal into a digital video signal and detects a synchronization signal included in the video signal. The red (R), green (G), and blue (B) data signals from the digital video card disposed in the system driver 31 are supplied to the column driver 33 using LVDS. LVDS can reduce the number of lines than the conventional one by compressing several data signals in one line and supplying them to the column driver from the system driver.

The row driver 35 may also be referred to as a gate driver. The row driver 35 may include a shift register that sequentially generates scan pulses in response to a gate start pulse GSP input from the timing controller 32, and adjusts the scan pulse voltages to drive the liquid crystal cell. Level shifter and the like for shifting to the level. In response to the scan pulse input from the row driver 35, the data signal on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

The gamma voltage generator 34 generates a gamma voltage Vγ corresponding to the grayscale value of the data in consideration of the electrical and optical characteristics of the liquid crystal panel 36. The gamma voltage Vγ is a voltage divided by the gamma voltage generator 34 corresponding to the gradation level. Accordingly, the gamma voltage Vγ generated from the gamma voltage generator 34 is set to have a different voltage level in response to the gray level value selected in the expressible range.

As illustrated in FIG. 5, the timing controller 32 generates predetermined control signals for driving the liquid crystal display using the horizontal / vertical synchronization signals H and V input from the system driver 31.

The timing control signal generator 54 generates the timing control signals using the vertical and horizontal synchronization signals H and V input from the system driver 31. These timing control signals are supplied to the column drive 33 and the row driver 35.

Among the timing control signals, data control signals supplied to the column driver 33 include SSC, SOE, and SSP. Gate control signals supplied to the low driver 35 include GSC, GOE, and GSP.

The polarity control signal generator 56 receives the horizontal and vertical synchronization signals H and V to generate a polarity control signal and supplies the same to the column drive 33. Polarity control signals include POL and REV.

The column driver 33 is also called a data driver. The column driver 33 is compressed with the red (R), green (G) and blue (B) data signals from the system driver 31 through the LVDS. At the same time, the dot clock Dclk is input from the timing controller 32. The column driver 33 latches the red (R), green (G), and blue (B) data signals in synchronization with the dot clock Dclk, and then corrects the latched data according to the gamma voltage Vγ. do. The column driver 33 converts the data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.

As shown in FIG. 6, the column driver 33 includes a data alignment unit 50, a first latch 40, a second latch 46, a digital-to-analog converter (DAC) 44, an output buffer 48, and the like. An address shift register 42 is provided.

The data alignment unit 50 restores the data signal compressed by the system driver 31 to the original data and inputs the original data to the first latch 40.                     

The first latch 40 temporarily stores the red, green, and blue data signals input from the data alignment unit 50 and supplies the stored data to the second latch 46 every horizontal period.

The second latch 46 stores data supplied from the first latch 40 at a position corresponding to the address information from the address shift register 42 and converts the stored first line data into the digital-analog converter 44. To feed.

The digital-analog converter 44 selects a gamma voltage Vγ corresponding to the data from the second latch 46 and supplies it to the output buffer 48.

The output buffer 48 is implemented as a voltage follower (not shown) connected between the digital-to-analog converter 44 and the data line DL. The output buffer 48 generates an output voltage having the same voltage level and polarity as the voltage input from the digital-to-analog converter 44, suppresses the variation of the output voltage, and supplies it to the data line DL.

The output buffer 48 and the second latch 46 have a timing controller to invert the polarity of the data according to inversion driving methods, for example, dot inversion, line (column) inversion and frame inversion driving methods. The polarity inversion signal is input from (32).

The address shift register 42 generates address information for data stored in the second latch 46 to control the second latch 46.

 As described above, the liquid crystal display according to the present invention is directly applied to the column driver without going through a timing controller using LVDS in which a plurality of data signals are compressed from the system driver. As a result, the number of lines between the system driver and the column driver is reduced, and the data signal transmission path is simplified, thereby preventing transmission errors or data malfunction due to electromagnetic interference caused by data transmission. In addition, the data signal transmission path is simplified to lower power consumption. In addition, the number of lines transmitting data signals and control signals is reduced, so that the number of lines in the printed board for applying data signals and control signals to the LCD module is reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

delete delete A system driver for generating a low voltage differential signal (LVDS) in which a plurality of data are compressed; A column driver for realigning the data compressed by the low voltage differential signal into red, green, and blue data according to the liquid crystal panel, and supplying the realigned data to the data lines of the liquid crystal panel; Wow, A timing controller for controlling driving of the column driver; The column driver includes an address shift resist for generating address information under the control of the timing controller, a first latch for temporarily storing red, green, and blue data rearranged through the data sorting unit, and from the address shift resist. A second latch for storing data supplied from the first latch at a position corresponding to the address information and outputting one line of stored data; and a digital-selection for selecting gamma voltages corresponding to the data from the second latch. And an analog converter and an output buffer for buffering the gamma voltages from the digital-analog converter to the data lines. A system driver for generating a low voltage differential signal (LVDS) in which a plurality of data are compressed; A column driver for realigning the data compressed by the low voltage differential signal into red, green, and blue data according to the liquid crystal panel, and supplying the realigned data to the data lines of the liquid crystal panel; Wow, A timing controller for controlling driving of the column driver; The timing controller may include a polarity control signal generator for generating a polarity control signal for controlling the polarity of data supplied to the data lines by using the synchronization signals input from the system driver, and a synchronization input from the system driver. And a timing control signal generator for generating data control signals for controlling the column driver using signals. The method of claim 3, wherein And the first latch stores the data signal input from the data alignment unit and supplies the data to the second latch every horizontal period. The method of claim 3, wherein And the output buffer has a voltage follower connected between the digital-analog converter and the data line. delete

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