KR20060065224A - Source driver of liquid crystal display device capable of inserting black data for improving the quality of moving images stably - Google Patents

Abstract

A source driver of a liquid crystal display device capable of stably inserting black data for improving video quality is provided. The source driver relates to a circuit including a plurality of line drivers for outputting a source line driving signal for driving the source lines of the liquid crystal display, respectively, wherein each line driver is configured to decode digital normal data and digital decoding in response to an output control signal. And a decoder to select one of the black data, and a decoder to select one of gamma reference voltages corresponding to the digital data selected by the data selector to output analog gray voltages corresponding to the source line driving signal. The source driver is used in common by the respective line drivers, and further includes a data decoder for decoding the black data input from the outside to generate digitally decoded black data. The source driver is commonly used by all line drivers and includes a data decoder that generates digitally decoded black data, thereby reducing chip size and input delay of the output buffer and simplifying the structure of the output multiplexer. .

Description

Source driver of liquid crystal display device capable of inserting black data for improving the quality of moving images stably}

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a block diagram illustrating a line driver included in a source driver of a liquid crystal display device performing a black insertion function according to the related art.

2 is a block diagram illustrating a line driver included in a source driver of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a table showing an example of the first and second black data input from the outside of the source driver according to the present invention and the black insertion data decoded from them.

<Description of the reference numerals for the main parts of the drawings>

230: data selector 250: decoder

310: digital buffer 320: data decoder

The present invention relates to a liquid crystal display device, and more particularly, to a source driver of a liquid crystal display device capable of stably inserting black data for improving video quality.

Liquid crystal display devices (LCDs) have advantages of miniaturization, thinness, and low power consumption, and are used in notebook computers and LCD TVs. In particular, an active matrix type liquid crystal display device using a thin film transistor as a switch element is suitable for displaying a moving image.

Unlike a display device using an impulse type cathode ray tube (CRT), the liquid crystal display holds and displays image data for one frame period, so that when a frame is switched ( That is, afterimages may occur during the vertical blanking time. In order to remove such an afterimage, black data is applied (or inserted) between frames to display a black image on the screen. Such black insertion technology can greatly improve the image quality of an LCD TV on which a video is displayed. Therefore, the source driver integrated circuit used in the LCD TV includes a circuit for performing a black insertion function.

1 is a block diagram illustrating a line driver included in a source driver of a liquid crystal display device performing a black insertion function according to the related art.

Referring to FIG. 1, a line driver 100 includes a data register unit 110, an input multiplexer MUX_I 120, and a level shifter unit 130. ), A decoder unit 140, an output multiplexer MUX_O 150, and an output buffer 160. The conventional source driver includes a plurality of line drivers including the same components as those of the line driver 100 and having different outputs (for example, a source line driving signal of Yn + 1).

The data register unit 110 includes a first data register DR1 and a second data register DR2 and is digital image data D_DAT which is RGB (Red, Green, Blue) data transmitted from a graphic card. Save). The first data register DR1 stores digital data corresponding to an analog gray level voltage of positive polarity, and the second data register DR2 is an analog of negative polarity. Digital data corresponding to the gradation level voltage is stored. The positive voltage refers to the voltage between VDD (power supply voltage) and VDD / 2, and the negative voltage refers to the voltage between VDD / 2 and VSS (ground voltage). Here, VDD / 2 is a common voltage applied to one terminal of a liquid crystal capacitor included in a pixel of the LCD.

The MUX_I 120 selects one of digital data stored in the first data register DR1 and digital data stored in the second data register DR2 in response to a polarity control signal POL. Output to 130. The polarity control signal POL is a signal for controlling the polarity of the liquid crystal to be inverted every one frame to prevent deterioration of the LCD panel.

The level shifter unit 130 includes first to fourth level shifters LS1 to LS4. The first level shifter LS1 increases and outputs the voltage level of the normal data of positive polarity included in the digital data D_DAT, and the second level shifter LS2 is a negative part included in the digital data D_DAT. The voltage level of the normal data of polarity is raised and output. The output normal data NDAT1 and negative data NDAT2 of the negative polarity may have a value of 10 bits. The third level shifter LS3 increases and outputs the voltage level of the positive black data included in the digital data D_DAT, and the fourth level shifter LS4 includes the negative black data included in the digital data D_DAT. Raise the voltage level and output. The output positive black data BDAT1 and negative black data BDAT2 may each have a value of 2 bits.

The decoder 140 is a gamma decoder unit, and includes a first positive gray voltage decoder PDEC1, a first sub gray voltage decoder NDEC1, a second positive gray voltage decoder PDEC2, and a second sub gray scale decoder PDEC2. The gray voltage decoder NDEC2 is included.

The first positive gray voltage decoder PDEC1 selects one of the gamma reference voltages VGMA corresponding to the positive normal data NDAT1 output from the first level shifter LS1 to select the positive normal voltage. The analog gray voltage VNA1 is output, and the first sub gray voltage decoder NDEC1 is one of the gamma reference voltages VGMA corresponding to the negative normal data NDAT2 output from the second level shifter LS2. Select to output a negative normal gray scale voltage VNA2. In addition, the second positive gray voltage decoder PDEC2 selects one of the gamma reference voltages VGMA corresponding to the positive black data BDAT1 output from the third level shifter LS3 to generate a positive black analog gray voltage. Outputs VBA1, and the second sub-gradation voltage decoder NDEC2 selects one of the gamma reference voltages VGMA corresponding to the negative black data BDAT2 output from the fourth level shifter LS4. A negative black analog gray scale voltage VBA2 is output. Here, the number of gamma reference voltages VGMA is 1024 when the normal data NDAT1 having positive polarity has a value of 10 bits.

The MUX_O 150 of the normal gray voltages VNA1 and VNA2 and the black gray voltages VBA1 and VBA2 in response to the polarity control signal POL, the black polarity control signal BPOL, and the output control signal BOUT. Select one and print it out. The black polarity control signal BPOL is a signal for controlling the polarity inversion of the black data. The output control signal BOUT controls the output of normal data or the output of black data. For example, black data is output when the output control signal BOUT is activated at a high level, and normal data is output when the output control signal BOUT is inactivated at a low level.

The output buffer 160 amplifies the output voltage of the MUX_O 150 to generate a source line driving signal Yn for driving the source line of the LCD panel. Where n is one of natural numbers.

However, the source driver including the conventional line driver 100 needs to add separate gamma decoders (that is, PDEC2 and NDEC2) for each line driver in order to insert black data into the screen. Increase the chip size of the driver IC). In addition, the structure of the output multiplexer 150 is complicated by the addition of separate gamma decoders PDEC2 and NDEC2.

On the other hand, when the gamma decoders PDEC2 and NDEC2 are commonly used in all line drivers included in the conventional source driver to reduce the chip size of the source driver IC, parasitic resistance and parasitic The gray scale voltage input to the output buffer included in the line driver may be delayed according to the layout characteristic of the source driver chip such as capacitance. This input delay generates a slew rate offset of the output voltage of the respective output buffers and thereby streaks on the LCD panel with multiple channels (ie, multiple source lines). It may cause a phenomenon to reduce the quality of the screen. Therefore, there is a problem that an analog buffer should be added to compensate for the input delay.

Accordingly, an aspect of the present invention is to provide a source driver of a liquid crystal display device including an output multiplexer having a simple structure and capable of reducing chip size and an input delay of an output buffer.

In order to achieve the above technical problem, a source driver according to the present invention relates to a source driver including a plurality of line drivers for outputting a source line driving signal for driving a source line of a liquid crystal display, respectively. A data selector configured to select one of digital normal data and digital decoded black data in response to the output control signal; And a decoder configured to select one of gamma reference voltages corresponding to the digital data selected by the data selector and to output analog gray voltages corresponding to the source line driving signal, and common by the respective line drivers. And a data decoder for decoding the black data input from the outside and generating the digitally decoded black data.

According to a preferred embodiment, the data decoder is disposed in the center of the source driver chip, the black data input to the data decoder has a value of 2 bits.

According to a preferred embodiment, the source driver further comprises a digital buffer for amplifying the black data decoded by the data decoder and outputting the black data as the digital decoded black data. The digital buffer includes two inverters connected in series.

According to a preferred embodiment, the decoder unit may include a positive gray voltage decoder configured to output positive gray voltages included in the analog gray voltages corresponding to positive data included in the digital data selected by the data selector; And a negative gray voltage decoder configured to output negative gray voltages included in the analog gray voltages corresponding to the negative data included in the digital data selected by the data selector.

According to an exemplary embodiment, each of the line drivers may include a first data register for storing data corresponding to a positive analog gray level voltage among digital normal image data transmitted from a graphics card and a negative analog gray level among the digital normal image data. A data register section including a second data register for storing data corresponding to a voltage; An input multiplexer for selecting one of digital data stored in the first data register and digital data stored in the second data register to output the digital normal data; Included in the first level shifter and the digital normal data or the digital decoded black data, respectively, which increase the voltage level of the positive data included in the digital normal data or the digital decoded black data and output the same to the constant gray voltage decoder. A level shifter unit including a second level shifter that increases a voltage level of negative data and outputs the voltage level to the negative gray voltage decoder; An output multiplexer for selecting one of an output voltage of the positive gray voltage decoder and an output voltage of the sub gray voltage decoder; And an output buffer for amplifying an output voltage of the output multiplexer to generate the source line driving signal.

According to a preferred embodiment, the input multiplexer operates in response to a polarity control signal for controlling liquid crystal polarity inversion of the liquid crystal display, and the output multiplexer controls the polarity inversion of the polarity control signal and the digital decoding black data. It operates in response to the black polarity control signal.

The source driver of the liquid crystal display according to the present invention includes a data decoder which is commonly used by all line drivers and generates black insertion data which is a digital signal, thereby reducing the chip size and the input delay of the output buffer. The structure of the output multiplexer can be simplified. Therefore, since black data can be stably inserted into the LCD panel with a minimum delay time, the fringes occurring in the LCD panel having multiple channels can be eliminated and the screen quality can be improved.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram illustrating a line driver included in a source driver of a liquid crystal display according to an exemplary embodiment of the present invention.

2, the line driver 200 includes a data register unit 210, an input multiplexer (MUX_I, 220), a data selection unit 230, a level shifter unit 240, and a decoder unit 250. ), An output multiplexer (MUX_O, 260), and an output buffer 270. The source driver according to the present invention includes a plurality of line drivers including the same components as those of the line driver 200 and having different outputs (for example, a source line driving signal of Yn + 1).

The data register unit 210 includes a first data register DR1 and a second data register DR2 and stores digital normal image data NDAT, which is RGB data transmitted from a graphics card. The first data register DR1 stores digital data corresponding to a positive analog gray voltage, and the second data register DR2 stores digital data corresponding to a negative analog gray voltage. The positive voltage refers to the voltage between VDD (power supply voltage) and VDD / 2, and the negative voltage refers to the voltage between VDD / 2 and VSS (ground voltage). Here, VDD / 2 is a common voltage applied to one terminal of the liquid crystal capacitor included in the pixel of the LCD.

The MUX_I 220 selects data by selecting one of the digital data NDAT1 stored in the first data register DR1 and the digital data NDAT2 stored in the second data register DR2 in response to the polarity control signal POL. Output to the unit 230. The polarity control signal POL is a signal for controlling the polarity of the liquid crystal to be inverted every frame to prevent degradation of the LCD panel.

The data selector 230 includes first and second multiplexers MUX1 and MUX2. The first multiplexer MUX1 selects one of the positive normal data NDAT1 and the digital decoding black data BDATA in response to the output control signal BOUT. The second multiplexer MUX2 selects one of the negative normal data NDAT2 and the digital decoding black data BDATA in response to the output control signal BOUT. For example, black data is output when the output control signal BOUT is activated at a high level, and normal data is output when the output control signal BOUT is inactivated at a low level. The positive normal data NDAT1, the negative normal data NDAT2, and the decoding black data BDATA may be 10-bit digital signals.

The decoding black data BDATA is generated by a data decoder 320 and a digital buffer 310 disposed in an area between the input multiplexer 220 and the data selector 230, respectively. This arrangement minimizes the length of the path required for the insertion of the black data BDAT <1>, BDAT <2>.

The data decoder 320 uses the power supply voltage VDD and the ground voltage VSS as operating voltages. The magnitudes of the VDD and the VSS are relatively smaller than the operating voltages used in the decoder 250, the output multiplexer 260, and the output buffer 270. The data decoder 320 decodes the first and second black data BDAT <1> and BDAT <2> input from the outside of the source driver according to the present invention to generate black insertion data. The first and second black data BDAT <1> and BDAT <2> may each have a value of 1 bit, and the black insertion data may have a value of 10 bits. 3 shows an example of the first and second black data BDAT <1> and BDAT <2> inputted from the outside of the source driver according to the present invention and the black inserted data decoded thereof. In the table of FIG. 3, the hexadecimal value corresponding to the binary value of the black insertion data is described.

Referring again to FIG. 2, the digital buffer 310 includes inverters 312 and 314 connected in series. The digital buffer 310 buffers (or amplifies) black insertion data, which is an output of the data decoder 320, to generate decoded black data BDATA.

On the other hand, the data decoder 320 is disposed in the center of the source driver chip according to the present invention and commonly used (ie, shared) by the respective line drivers. The data selector included in the line driver adjacent to the line driver 200 receives the decoding black data BDATA, which is an output of the data decoder 320, through a digital buffer such as the digital buffer 310.

The level shifter unit 240 includes first and second level shifters LS1 and LS2. The first level shifter LS1 increases and outputs the voltage level of the output signal of the first multiplexer MUX1, and the second level shifter LS2 increases and outputs the voltage level of the output signal of the second multiplexer MUX2. do.

The decoder 250 includes a positive gray voltage decoder PDEC and a negative gray voltage decoder NDEC as a gamma decoder. The positive gradation voltage decoder PDEC selects one of the gamma reference voltages VGMA corresponding to the positive digital data output from the first level shifter LS1 to output the analog gradation voltage VA1 of the positive polarity. The gray voltage decoder NDEC selects one of the gamma reference voltages VGMA corresponding to the negative digital data output from the second level shifter LS2 and outputs the negative analog gray voltage V A2. Gamma reference voltages VGMA are input through a voltage divider from a timing controller disposed outside the source driver according to the present invention. For example, the number of gamma reference voltages VGMA is 1024 when the digital data NDAT1 having positive polarity has a value of 10 bits.                     

The MUX_O 260 selects and outputs one of the positive analog gray voltage VA1 and the negative analog gray voltage VA2 in response to the polarity control signal POL and the black polarity control signal BPOL. The black polarity control signal BPOL is a signal for controlling the polarity inversion of the black data.

The output buffer 270 amplifies the output voltage of the MUX_O 260 to generate a source line driving signal Yn for driving the source line of the LCD panel. Where n is one of natural numbers.

As described above, the source driver of the liquid crystal display according to the present invention includes a data decoder which is commonly used by all line drivers and generates black insertion data which is a digital signal, thereby reducing the chip size and the input delay of the output buffer. It can reduce and simplify the structure of the output multiplexer. Therefore, black data can be stably inserted into the LCD panel with minimal delay time, thereby eliminating streaks occurring in LCD panels having multiple channels (ie, multiple source lines), thereby improving screen quality. Can be.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Herein, specific terms have been used, but they are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The source driver of the liquid crystal display according to the present invention includes a data decoder which is commonly used by all line drivers and generates black insertion data which is a digital signal, thereby reducing the chip size and the input delay of the output buffer and outputting The structure of the multiplexer can be simplified. Therefore, since black data can be stably inserted into the LCD panel with a minimum delay time, the fringes occurring in the LCD panel having multiple channels can be eliminated and the screen quality can be improved.

Claims (7)

In the source driver including a plurality of line drivers for outputting a source line driving signal for driving each of the source line of the liquid crystal display device, Each of the line drivers A data selector for selecting one of digital normal data and digital decoded black data in response to the output control signal; And A decoder configured to select one of gamma reference voltages corresponding to the digital data selected by the data selector and output analog gray voltages corresponding to the source line driving signal; And a data decoder which is commonly used by the respective line drivers, and which decodes black data input from the outside to generate the digitally decoded black data. The method of claim 1, The data decoder is disposed in the center of the source driver chip, and the black data input to the data decoder has a value of 2 bits. The method of claim 1, wherein the source driver And a digital buffer for amplifying the black data decoded by the data decoder and outputting the black data decoded as the digital decoded black data. The method of claim 3, wherein the digital buffer is A source driver comprising two inverters connected in series. The method of claim 3, wherein the decoder unit A positive gradation voltage decoder configured to output positive gradation voltages included in the analog gradation voltages corresponding to positive polarity data included in the digital data selected by the data selector; And And a negative gray voltage decoder for outputting negative gray voltages included in the analog gray voltages corresponding to negative data included in the digital data selected by the data selector. The method of claim 5, wherein each of the line drivers A first data register storing data corresponding to a positive analog gray voltage of digital normal image data transmitted from a graphics card and a second data register storing data corresponding to a negative analog gray voltage of the digital normal image data A data register unit comprising a; An input multiplexer for selecting one of digital data stored in the first data register and digital data stored in the second data register to output the digital normal data; Included in the first level shifter and the digital normal data or the digital decoded black data, respectively, which increase the voltage level of the positive data included in the digital normal data or the digital decoded black data and output the same to the constant gray voltage decoder. A level shifter unit including a second level shifter that increases a voltage level of negative data and outputs the voltage level to the negative gray voltage decoder; An output multiplexer for selecting one of an output voltage of the positive gray voltage decoder and an output voltage of the sub gray voltage decoder; And And an output buffer for amplifying an output voltage of the output multiplexer to generate the source line driving signal. The method of claim 6, The input multiplexer operates in response to a polarity control signal for controlling liquid crystal polarity inversion of the liquid crystal display, And the output multiplexer operates in response to the polarity control signal and a black polarity control signal for controlling polarity inversion of the digitally decoded black data.

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