KR20080050313A - Liquid crystal display device and driving method thereby - Google Patents

Abstract

An LCD device and a driving method thereof are provided to prevent the reduction of image quality by synchronizing the termination time of the tail of gate voltage with the input time of valid data signal. An LCD(Liquid Crystal Display) device includes an LCD panel(116), a timing controller(110), and gate and data drivers(112,114). The LCD panel includes plural gate and data lines and thin film transistors. The timing controller receives data and vertical/horizontal synchronous signals from outside, and generates control signals. The gate driver outputs gate signals to the gate lines of the LCD panel according to the control signals from the timing controller. The data driver outputs image signals to the data lines of the LCD panel according to the control signals of the timing controller. The control signals include a high signal corresponding to a previous interval before inputting a valid image signal to the LCD panel and a masking signal for masking image signals before inputting the valid image signal.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREBY}

The present invention relates to a liquid crystal display and a driving method thereof, and more particularly, to generate an SOE masking signal (Source Output Enable Masking Signal) to prevent abnormalities of the screen such as vertical lines generated during the initial driving of the liquid crystal display. The present invention relates to a liquid crystal display and a driving method thereof.

Recently, with the widespread use of portable information devices, research and commercialization of lightweight flat panel displays (FPDs), which replace the conventional cathode ray tube (CRT), have been focused. .

In particular, among the flat panel display devices, the liquid crystal display device is an apparatus for displaying an image using optical anisotropy of liquid crystal, and has been actively applied to a monitor or a television of a laptop or a desktop computer due to its excellent resolution, color display, and image quality. .

In general, as shown in FIG. 1, the liquid crystal display includes a liquid crystal panel 2 in which a plurality of liquid crystal cells defined by a plurality of gate lines GL1 -GLn and data lines DL1 -DLm are arranged in a matrix form. A gate driver 4 for applying a gate scan signal to the gate lines GL1 to GLn of the liquid crystal panel 2, and a data driver 6 for applying a pixel signal to the data lines DL1 to DLm of the liquid crystal panel 2; And a timing controller 10 that controls the gate driver 4 and the data driver 6.

The liquid crystal panel 2 is formed in a plurality of liquid crystal cells defined by a plurality of gate lines GL1 to GLn and data lines DL1 to DLm, and each of the liquid crystal cells to form the gate lines GL1 to GLn and data lines. A thin film transistor (TFT) connected to (Dl1-DLm) is provided.

The TFT is turned on when a scan signal from the gate lines GL1 to GL, that is, a gate high voltage Vgh is supplied, and applies a pixel signal applied from the data lines DL1 to DLm to the liquid crystal cell. On the other hand, when the gate low voltage Vgl is supplied from the gate lines GL1 to GLn, it is turned off to maintain the pixel signal charged in the liquid crystal cell.

Usually, the liquid crystal cell includes a pixel electrode connected to a TFT to receive a pixel signal and a common electrode facing the pixel electrode to form a liquid crystal capacitor Clc. In addition, a storage capacitor Cst is formed in the liquid crystal cell so as to stably maintain the pixel signal until one pixel signal is charged and the next pixel signal is charged. The liquid crystal display device configured as described above changes the arrangement state of liquid crystal molecules having dielectric anisotropy according to the pixel signal input through the TFT, and realizes gradation by adjusting the light transmittance according to the arrangement state of the liquid crystal molecules.

Gate control signals GSP, GSC, and GOE are input to the gate driver 4 from the timing controller 10, and the control signals GSP, GSC, and GOE are sequentially input to the gate lines GL1 to GLn. The gate high voltage Vgh is outputted to drive each TFT connected to the gate lines GL1 to GLn.

The data driver 6 outputs pixel signals to the data lines DL1 to DLm as the data control signals SSP, SSC, SOE, and POL are input from the timing controller 10.

In this case, the data driver 6 converts the red (R), green (G), and blue (B) digital signals provided from the timing controller 10 into analog pixel signals, and then converts the digital signals to the data lines DL1-Dlm. Supply.

However, the following problems occur in driving the liquid crystal display as described above.

Typically, since the gate high voltage Vgh input to the TFT of the liquid crystal display is a square wave having a set width, the TFT is turned on for the set period as the gate high voltage Vgh is applied. As such, the pixel signal is applied to the data lines DL1-Dlm through the TFT in the data driver 6 while the TFT is turned on. However, the gate high voltage Vgh input to the TFT during the initial driving of the liquid crystal display device is a waveform in which tails are formed at regular intervals rather than a typical square wave. Therefore, in the initial driving of the liquid crystal display, the TFT is turned on not only for a set time but also for an undesired time. Therefore, the pixel signal is applied to the liquid crystal cell during the initial driving of the liquid crystal display, that is, when the screen of the display device is turned on, so that an image is displayed on the screen.

As described above, when the black signal or the white signal is applied to the liquid crystal cell through the TFT during the initial driving of the liquid crystal display, the image quality does not occur. However, when the image signal of the gray scale voltage is applied, the screen is turned on when the LCD is turned on. Image quality degradation such as streaks occur instantaneously.

It is an object of the present invention to provide a liquid crystal display device and a method for driving the same, which generate a SOE masking signal and prevent streaks and the like from being generated when a gray voltage is applied during initial driving of the liquid crystal display device.

In order to achieve the above object, the liquid crystal display device according to the present invention generates a control signal by receiving a liquid crystal panel including a plurality of gate lines, data lines, thin film transistors, and data and vertical / horizontal synchronization signals from the outside. A timing controller, a gate driver for outputting a gate signal to a gate line of the liquid crystal panel according to a control signal from the timing controller, and a data driver for outputting a data signal to a data line of the liquid crystal panel according to a control signal of the timing controller The control signal may include a masking signal for masking a data signal before the valid data signal is input, including a high signal corresponding to a section before the valid data signal is input to the liquid crystal panel. .

In addition, the method of driving the liquid crystal display according to the present invention generates a control signal by receiving data and vertical / horizontal synchronization signals from the outside, and sequentially generates a gate high voltage for one horizontal period according to the control signal. Supplying the input signal, preventing the arbitrary data from being output in synchronization with the masking period during initial driving by receiving the SOE masking signal, and applying the data according to the gate and the SOE masking signal to implement an image. It is composed.

In the present invention, since the SOE masking signal is generated and applied, the image signal is not input to the liquid crystal panel during the initial driving of the liquid crystal display. Therefore, during the initial driving of the liquid crystal display, an arbitrary gray scale voltage is applied from the data drive to the data line, thereby preventing the image quality from being degraded due to the occurrence of vertical lines or the like on the screen.

Hereinafter, a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings. 2 is a view showing the structure of a driving unit of the liquid crystal display according to the present invention.

As shown in FIG. 2, the liquid crystal display according to the present invention includes a timing controller 110, a gate driver 112 and a data driver to which a signal is applied from the timing controller 110 to output a gate signal and a pixel signal. And a liquid crystal panel 116 to which a signal output from the gate driver 112 and the data driver 114 is applied.

In the liquid crystal panel 116, a plurality of liquid crystal cells defined by a plurality of gate lines GL1 -GLn and data lines DL1 -DLm are arranged in a matrix form, and TFTs are formed in the liquid crystal cells, respectively. .

The timing controller 110 may include a data alignment unit 110a for aligning video data input through a graphics card in a system driver not shown, and a gate driver 112 and data according to a signal input from the graphics card. SOE for generating an SOE masking signal using a control signal generator 110b for generating a control signal, such as a timing signal for controlling timing of the driver 114, and an SOE signal provided from the control signal generator 110b. And a masking signal generation unit 110c.

The graphics card in the system driving unit converts the input video data into a resolution suitable for the resolution of the liquid crystal display and outputs it to the liquid crystal display. In this case, the video data is composed of red, green, and blue data. In addition, the graphics card generates control signals such as a clock signal DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal, and the like.

The timing controller 110 arranges the video data converted from the graphics card in the data alignment unit 110a and supplies the data to the data driver 114. The control signal generator 110b controls the graphics card. Gate Shift Clock (GSC), Gate Output Enable (GOE), Gate Start Pulse (Gate Start Pulse) to control the timing of the gate driver 112 and the data driver 114 according to the signal. Gate control signal such as GSP, Source Sampling Clock (SSC), Source Output Enable (SOE), Source Start Pulse (SSP), Polarity Reverse: POL), data polarity selection (Data Reverse: REV), odd / even pixel data (Odd / Even Data) signals, and the like.

In this case, the GSC is a signal for determining the time when the gate of the thin film transistor is turned on (On / Off), the GOE is a signal for controlling the output of the gate driver 112, GSP is one of the vertical synchronization signal of the screen This signal indicates the first driving line. The SSC is used as a sampling clock for latching data in the data driver 114 and determines a driving frequency of the data drive IC. The SOE simultaneously transmits data corresponding to one horizontal line latched by the SSC to the liquid crystal panel, and the SSP is a signal indicating the start of latching or sampling of data during one horizontal synchronizing period. In addition, POL is a polarity signal for driving the liquid crystal positively and negatively for inversion driving of the liquid crystal, and REV is a signal for selecting the polarity of the transmitted data, and odd / even pixel data is used for the odd pixel. This signal represents odd data and even data of even pixels.

In the SOE masking signal generation unit 110c, an SOE signal is input from the control signal generation unit 110b to generate an SOE masking signal. The SOE masking signal is an SOE signal having a masking period for a predetermined time during initial driving of the liquid crystal display, and the masking period is a data of the gray scale voltage from the data driver 114 during the initial driving of the liquid crystal display. In the drawing, the SOE masking signal generation unit 110 is formed integrally with the data alignment unit 110a and the control signal generation unit 110b in the timing controller 110. The SOE masking signal generator 110 may be formed outside the timing controller 110 separately from the data sorter 110a and the control signal generator 110b.

On the other hand, the gate driver 112 controls the gate terminal of the thin film transistors arranged on the liquid crystal panel 116 on / off line by line in response to the control signals input from the timing controller 110 to control the data driver (1). The analog image signal supplied from 114 is applied to the corresponding liquid crystal cell through the thin film transistor.

In addition, the data driver 114 samples the video data R, G, and B input from the timing controller 110, latches the sampled data, and then converts the data stored in the latch into a gray voltage to convert the data into a gray scale voltage. 116).

Although not shown in the drawing, the data driver 114 includes a data register into which data RGB is input from the timing controller 110, a shift register for generating a sampling clock, the shift register, and m data lines. A gamma gradation voltage circuit for dividing the first latch, the second latch and the gamma reference voltages connected between (DL1 to DLm) and supplying the digital to analog converter (DAC), a digital / analog converter, An output section and an output control section 114a.

The data register temporarily stores the data RGB input from the timing controller 110 and supplies the stored data RGB to the first latch, and the shift register includes a source start pulse input from the timing controller 110. SSP is shifted according to the source sampling clock SSC to generate a sampling signal. The shift register shifts the source start pulse SSP to transfer a carry signal CAR to the next shift register. The first latch samples the digital video data RGB input from the data register in response to a sampling signal sequentially input from the shift register, and latches the sampled digital video data RGB by one line. The second latch latches the digital data RGB input from the first latch and simultaneously outputs the latched digital video data RGB to the data line in response to the SOE masking signal input from the timing controller 110. Let's do it. The gamma gradation voltage circuit divides the gamma reference voltages divided by the reference voltage generation unit again using the voltage input from the external power supply voltage generation unit to generate gamma gradation voltages corresponding to each gradation.

The DAC selects and outputs a gray level voltage of a corresponding level supplied from the gamma gray voltage circuit in response to the video data RGB input from the second latch. In this case, the gray voltage is output as one of positive and negative polarity according to the polarity control signal output from the timing controller.

The output circuit temporarily stores the analog R, G, and B pixel voltages selected and output from the DAC in an internal buffer. The output control unit 114a is formed of a switch that interlocks with the buffer of the output circuit. The SOE masking signal applied to the second latch is applied to control the switch, so that arbitrary data is generated during the initial driving of the liquid crystal display. It is possible to prevent the output to the panel 116.

Hereinafter, the configuration and operation principle of the SOE masking signal generation unit 110c in the timing controller 110 according to the present invention will be described in more detail with reference to FIGS. 3 and 4. First, as illustrated in FIG. 3, the SOE masking signal generation unit 110c includes a masking signal generation unit 210 and an operation unit 220 including an OR gate. In addition, the masking signal generator 210 generates an oscillator 211 that generates a clock having periodicity at predetermined intervals, and a counting signal that counts the clock generated by the oscillator 211 and periodically inverts at predetermined intervals. When the counter unit 213 and the counting signal input from the counter unit 213 are less than or equal to the reference value of the counting signal, a high masking signal is generated and output to the calculating unit 220. When the reference value is equal to or greater than, the comparator 215 generates a masking signal in a low state and outputs the masking signal to the calculator 220.

The generation of the SOE masking signal in the SOE masking signal generation unit 110c will be described with reference to the waveform diagram shown in FIG. 4. In the following description, the generation of the SOE masking signal is described using a specific frequency or a signal section as an example, but this is merely for convenience of description and the present invention is not limited to this specific frequency or signal section.

As shown in FIG. 4, when an oscillation signal of 100 Hz is generated by the oscillator 211, the counter unit 213 is synchronized with the initial driving of the liquid crystal display, corresponding to a time corresponding to the first 5 ms (n = The signal to be inverted is inverted every 500). In addition, the comparison unit 215 sets a reference value corresponding to 5ms, and generates a masking signal that maintains the high state before the first reference value and the low state after the reference value. That is, by counting the clock by the counter unit 213, the comparator 215 outputs a high state signal before the reference clock and the comparator 215 outputs a low state signal after the reference clock. Meanwhile, as described above, the counter unit 213 may output the masking signal in the high state during the initial driving of the liquid crystal display, but may output the masking signal in the low state. When the clock counted by the counter unit 213 is before the reference clock, a low signal is output, and after the reference clock, the high signal is output. The calculator 220 includes an OR gate, and the timing controller 110. The SOE signal input from the control signal generator 110b and the masking signal input from the masking signal generator 210 are logically generated to generate the SOE masking signal.

The SOE masking signal is input to the data driver 116. As shown in FIG. 5A, the data driver 114 includes an output control unit 114a, a buffer unit 114b, and a switching signal generator 114c. The output control unit 114a includes a first switch SW1 and a second switch SW2. The SOE masking signal output from the calculator 220 is applied to the output controller 114a through the buffer 114b of the data driver 114. In addition, as the SOE masking signal is input, the switching signal generator 114c controls a switching signal for controlling the first switch SW1 and the second switch SW2 of the output controller 114a as shown in FIG. 5B. Output

The switching signal generator 114c may be formed in the data driver 114 together with the buffer unit 114a and the output control unit 114b as described above, but may be formed separately from the data driver 114, that is, in the timing controller. Could be

 In the initial operation of the liquid crystal display device, an image signal including an effective image voltage is input to a pixel of the liquid crystal display device. In this case, the effective image voltage means a voltage for an actual desired image. In other words, the effective image voltage means an actual image signal that implements a desired image by excluding an initial image signal.

As shown in FIG. 5B, a first switching signal and a second switching signal are respectively input to the first switch SW1 and the second switch SW2 during initial driving. As shown in FIG. 5B, the second switching signal maintains a low state during initial driving of the liquid crystal display. Therefore, the second switch SW2 is maintained in the off state, and thus the pixel signal is not input to the data line through the second switch SW2. In this case, a first switching signal in a low state is applied to the first switch SW1 so that the first switch SW1 is turned off.

As described above, since the second switch SW2 is turned off during the initial driving of the liquid crystal display, an image signal is not input to the liquid crystal panel (a section in which the image signal is not input in this manner is called a masking section). Therefore, during the initial driving of the liquid crystal display, an arbitrary gray scale voltage is applied from the data drive to the data line, thereby preventing the image quality from being degraded due to the occurrence of vertical lines or the like on the screen.

After the initial driving as described above, that is, after the masking period, a low signal is applied to the first switch SW1 so that the first switch SW1 is turned off and a high signal is applied to the second switch Sw2 so that the second switch SW2 is applied. When turned on, the pixel signal of the effective image voltage is applied to the pixel of the liquid crystal panel to implement an image. Thereafter, when a high signal is input to the first switch SW1 and the first switch SW1 is turned on and a low signal is input to the second switch SW2, the second switch SW2 is turned off. The output line of each buffer unit 114b and the adjacent line are shorted to each other to output the intermediate level of the voltage between both lines.

6 is a waveform diagram showing the states of the gate signal voltage, the data signal, and the SOE masking signal during the initial driving of the liquid crystal display according to the present invention. As shown in FIG. 6, when the gate voltage is turned off during the initial driving to become the gate-low voltage Vgl from the gate-high voltage Vgh, the ideal gate voltage forms a square wave but the actual gate voltage. Will form a tail. In FIG. 6, the tail is generated in the tail section t. The tail of the gate voltage is not turned on only during the set time but not turned on during the initial driving of the liquid crystal display. A masking section is formed in the tail period, and the switches constituting the output control section of the data driver are turned off momentarily for a predetermined time in synchronization with the rising edge of the masking section, thereby preventing any data output in the masking section. The normal pixel voltage is output from the data driver in synchronization with the SOE section.

As described above, in the present invention, since the SOE masking signal is generated and applied, the image signal is not input to the liquid crystal panel during the initial driving of the liquid crystal display device. Therefore, during the initial driving of the liquid crystal display, an arbitrary gray scale voltage is applied from the data drive to the data line, thereby preventing the image quality from being degraded due to the occurrence of vertical lines or the like on the screen.

In addition, this invention is not limited only to the above-mentioned description.

According to the present invention, the tail is generated at the gate-high voltage to prevent the image quality from being degraded by turning on the TFT at a time when the liquid crystal display device is not initially set. Therefore, any configuration may be possible as long as the image quality deterioration due to the tail of the gate-high voltage can be prevented.

For example, as illustrated in FIG. 7, the driving time of the gate voltage Vg is delayed for a predetermined period τ to prevent the TFT from being turned on in the tail of the data signal, thereby preventing deterioration of image quality. . That is, by synchronizing the timing at which the tail of the gate voltage Vg is terminated with the timing at which the valid data signal is input, it is possible to prevent the image quality from being degraded by turning on the TFT at an unset time during the initial driving of the liquid crystal display. will be.

1 is a block diagram showing a driving system of a conventional liquid crystal display device.

2 is a block diagram showing a driving system of a liquid crystal display device according to the present invention;

FIG. 3 is a block diagram illustrating a structure of the SOE masking signal generation unit of FIG. 2. FIG.

FIG. 4 is a diagram illustrating an operation waveform of a sub-block of the SOE masking signal generation unit shown in FIG. 3.

FIG. 5A is a view illustrating a coupling relationship between a data driver and a liquid crystal panel illustrated in FIG. 2.

5B is a waveform diagram illustrating a switching control signal applied to the data driver of FIG. 5A;

6 is a waveform diagram of a liquid crystal display device according to the present invention;

7 is another waveform diagram of a liquid crystal display according to the present invention;

Claims (15)

Liquid crystal panel including a plurality of gate lines, data lines, and thin film transistors A timing controller configured to receive data and vertical / horizontal synchronization signals from the outside to generate a control signal; A gate driver configured to output a gate signal to a gate line of the liquid crystal panel according to a control signal from the timing controller; And a data driver for outputting an image signal to a data line of the liquid crystal panel according to the control signal of the timing controller. And the control signal comprises a masking signal for masking an image signal before the valid image signal is input, including a high signal corresponding to a section before the effective image signal is input to the liquid crystal panel. The method of claim 1, wherein the timing controller Data alignment means for receiving and rearranging R, G, and B data from the outside; Control signal generation means for receiving a vertical / horizontal synchronization signal from the outside to generate a control signal including a GOE (Gate Output Enable) and a SOE signal; And And an SOE masking signal generating means for receiving an SOE signal from the control signal generating means and combining the masking signal with the SOE signal to generate an SOE masking signal. The method of claim 1, wherein the data driver A shift register for generating a sampling signal by shifting a source start pulse input from a timing controller according to a source sampling clock signal; A data register for temporarily storing digital video data (RGB) input from the timing controller; A first latch for latching digital video data from the data register line by line in response to a sampling signal sequentially input from the shift register; A second latch for latching digital data input from the first latch and simultaneously outputting the latched data in response to an SOE section of an SOE masking signal input from a timing controller; A gradation voltage generator for dividing a reference voltage from the outside to generate gradation voltages of positive and negative polarities; A DAC for selecting and outputting a gray voltage corresponding to the data latched in the second latch from the gray voltage generator according to the polarity control signal input from the timing controller; An output unit which holds a gray voltage from the DAC in a buffer; And And an output control unit which receives the SOE masking signal at the same time and blocks the output of the image signal before the effective image signal. The liquid crystal display device according to claim 1, wherein the predetermined time (T) is 0 < The liquid crystal display of claim 1, wherein the SOE masking signal starts in a high state during initial driving. The method of claim 2, wherein the SOE masking signal generating means An oscillator for generating a clock at a predetermined cycle; A counter for inverting the clock every predetermined number of times; A comparator outputting a high when the clock counted by the counter is less than or equal to a reference value and outputting a low when the clock counted by the counter is less than or equal to a reference value; And And a calculator for calculating a signal output from the comparator with an SOE signal. 7. The liquid crystal display device according to claim 6, wherein the calculator is an OR gate. A control signal first control signal generator receiving a vertical / horizontal synchronization signal from the outside; And And a SOE masking signal generating means for receiving the SOE signal and combining the masking signal with the SOE signal to generate a new SOE masking signal. The timing controller of claim 8, wherein the SOE masking signal starts in a high state during initial driving. The method of claim 8, wherein the SOE masking signal generating means An oscillator for generating a clock at a predetermined cycle; A counter for inverting the clock every predetermined number of times; A comparator for comparing the clock with its reference value such that the counter remains high only for a predetermined number of times; And And a calculator for calculating an output signal from the comparator with an SOE signal. The timing controller of claim 8, wherein the calculator is an OR gate. Generating a control signal by receiving data and a vertical / horizontal synchronization signal from the outside; Sequentially supplying a gate high voltage for one horizontal period according to the control signal; Preventing the arbitrary data from being output in synchronization with the masking section during initial driving by receiving the SOE masking signal; And applying data according to the gate and the SOE masking signal to implement an image. The method of claim 12, wherein the generating of the control signal comprises: Generating a masking signal; And And generating a signal of the SOE masking signal by the SOE signal enabling the masking signal and the image signal. Inputting a gate signal and a data signal as the liquid crystal display is turned on; Generating a masking signal including a high signal in a section before a valid data signal is input to the liquid crystal display; Masking an initial section of the data signal by the masking signal; And And implementing an image by the masked data signal. Generating a control signal by receiving data and a vertical / horizontal synchronization signal from the outside; Sequentially supplying a gate high voltage for one horizontal period according to the control signal; And And applying data according to the gate signal to implement an image. And a time point at which the tail generated at the gate high voltage ends is synchronized with a time point at which a valid data signal is input.

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