KR101016754B1 - Gate driver including dual shift resistor, method and apparatus of driving liquid crystal display panel using the same - Google Patents

Abstract

The present invention provides a gate driver including a dual shift register and a liquid crystal panel driving apparatus and method using the same, which enable driving a liquid crystal panel in a progressive manner and an interlaced manner.

To this end, the dual shift register according to the present invention comprises: an odd shift register configured to have an odd stage connected to an odd output line among a plurality of output lines, the slave shift register being connected to a first start pulse input line; An even shift register configured to be evenly connected to a second start pulse input line and respectively connected to an even output line of the plurality of output lines; When the first and second start pulses are simultaneously enabled, the odd shift register and the even shift register sequentially drive the output line, and in the first period, the first start pulse is enabled and the second start pulse is depressed. When enabled, the odd shift register sequentially drives the odd output line, and in the second period alternated with the first period, the second start pulse is enabled, and when the first start pulse is disabled, the even shift register. Drives the even output line sequentially.

Description

GATE DRIVER INCLUDING DUAL SHIFT RESISTOR, METHOD AND APPARATUS OF DRIVING LIQUID CRYSTAL DISPLAY PANEL USING THE SAME}             

1 is a block diagram showing a conventional gate driver.

2 is a diagram illustrating a dot inversion form of a liquid crystal panel displaying a video signal of a conventional interlaced system over time.

3A and 3B are diagrams illustrating charging characteristics of the first and second liquid crystal cells illustrated in FIG. 2 over time.

4 is a block diagram illustrating a gate driver including a dual shift register according to an exemplary embodiment of the present invention.

FIG. 5 is a block diagram illustrating a liquid crystal panel driving apparatus according to an exemplary embodiment of the present invention using the gate driver illustrated in FIG. 5.

<Description of Symbols for Main Parts of Drawings>

2: liquid crystal panel 4: gate driver

6: data driver 8: timing controller

10: shift register 20, 40: level shifter                 

30: dual shift register 32: odd shift register

34: Even shift registers ST1 to STn: First to nth stages

The present invention relates to a liquid crystal display device, and more particularly, to a gate driver including a dual shift register capable of both progressive and interlaced driving, and a liquid crystal panel driving device and method using the same.

A typical liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a liquid crystal cell matrix for displaying an image, and a driving circuit for driving the liquid crystal panel. BACKGROUND ART An active matrix type liquid crystal display device that independently drives liquid crystal cells using thin film transistors is widely used not only for display devices of personal computers (PCs) but also for televisions (hereinafter, referred to as TVs).

Methods of displaying an image signal on a display device are roughly classified into a progressive driving method and an interlace driving method.

The progressive driving method displays image signals of one screen frame by frame as if the film is projected on the screen. Representative display devices using such a progressive driving method include digital display devices such as computer monitors, plasma display panels (PDPs), and liquid crystal displays.

On the other hand, the interlace driving method divides one screen, that is, one frame into an odd field displaying odd horizontal lines and an even field displaying even horizontal lines, and sequentially divides the odd field and the even field. On the screen. A representative display device using such an interlace driving method is a TV. In other words, the TV video signal is supplied in an interlaced manner.

In the case where a TV video signal supplied in an interlaced manner is to be displayed on a liquid crystal display device, a computer system driving the liquid crystal display device converts the interlaced TV video signal into a progressive method and supplies it to the liquid crystal display device. This is because the liquid crystal display is sequentially driven in line using the gate driver shown in FIG. 1. (Gate Start Pulse; GSP) to Gate Shift Clock (GSC)

Referring to FIG. 1, a conventional gate driver shifts a gate start pulse (GSP) according to a gate shift clock (GSC) to generate a scan signal, and a shift register. And a level shifter 20 for level shifting and outputting the scan signal from (10).

The shift register 10 has n stages ST1 to STn connected to the input line of the gate start pulse GSP and connected in common to the gate shift clock GSC input line. The n stages ST1 to STn sequentially shift the gate start pulse SP in response to the gate shift clock signal GCLK to output scan pulses SP1 to SPn. The level shifter 20 level shifts the scan pulses SP1 to SPn from the shift register 10 and outputs them to each of the gate lines GL1 to GLn.

As such, since the gate driver sequentially driving the gate lines GL1 to GLn is used, the liquid crystal display may not display an interlaced image signal in which the odd line and the even line are selectively driven.

Accordingly, the computer system utilizes a method of progressively converting an interlaced video signal into an odd field and even field combination and supplying the result to a liquid crystal display device. There is a disadvantage that a conversion unit must be added.

In order to solve this disadvantage, recently, as shown in FIG. 2, a method of adding dummy data to an interlaced video signal and displaying the same on a progressively driven liquid crystal display device has been proposed.

Referring to FIG. 3, an odd frame (OF) and an even frame (EF) displayed on a liquid crystal panel by adding dummy data to pixel data supplied by an interlace method are repeated.

In the odd frame OF, real pixel data is filled in the odd horizontal lines of the liquid crystal panel, and dummy pixel data (for example, white or black pixel data) is filled in the even horizontal lines. In the even frame EF, the odd horizontal lines of the liquid crystal panel are filled with dummy pixel data (for example, white pixel data), and the even horizontal lines are filled with actual pixel data.

In addition, the liquid crystal panel has a polarity in which each of the liquid crystal cells has opposite polarities with respect to the common voltage Vcom with other liquid crystal cells adjacent to the liquid crystal cells to improve display quality, and the polarities of the liquid crystal cells are inverted in units of frames. It is driven in an inversion manner.

In detail, as illustrated in FIG. 3A, the first liquid crystal cell P1 of the odd horizontal line uses the actual pixel data having positive polarity (+) based on the common voltage Vcom in the odd frame OF, and in the even frame EF. White pixel data of negative polarity, which is dummy pixel data, is charged. As shown in FIG. 3B, the second liquid crystal cell P2 of the even horizontal line has negative pixel (-) white pixel data which is dummy pixel data in the odd frame OF, and positive electrode (+) in the even frame EF. Charge the pixel data. The first and second liquid crystal cells P1 and P2 repeat the polar inversion as the odd and even frames OF and EF are repeated. In this case, the actual pixel data supplied to the first and second liquid crystal cells P1 and P2 may have the same polarity, that is, the positive polarity (+), and the dummy pixel data may have the negative polarity (−). In addition, the actual pixel data having positive polarity (+) is supplied to supply voltages applied to the first and second liquid crystal cells P1 and P2, and the dummy pixel data having negative polarity (-) is supplied to provide the first and second liquid crystal cells. It can be seen that the difference with the voltage applied to (P1, P2) is large. Due to this voltage difference, as time passes, voltages applied to the first and second second liquid crystal cells P1 and P2 are biased toward the positive polarity (+). In other words, as time passes, the first and second second liquid crystal cells P1 and P2 are induced to have a positive voltage (DC) biased with positive polarity, as shown by the dotted lines shown in FIGS. 3A and 3B. do. As a result, a problem of deterioration of image quality such as an afterimage occurs.

Accordingly, there is a need for a method of displaying an interlaced video signal as it is on a liquid crystal display, and further, a method of displaying both an interlaced video signal and a progressive video signal.

Accordingly, an object of the present invention is to provide a gate driver including a dual shift register and a liquid crystal panel driving apparatus and method using the same, which enable driving a liquid crystal panel in a progressive manner and an interlaced manner.

In order to achieve the above object, the dual shift register according to the present invention comprises: an odd shift register configured to be connected to a first start pulse input line and an odd stage each connected to an odd output line of a plurality of output lines; An even shift register configured to be evenly connected to a second start pulse input line and respectively connected to an even output line of the plurality of output lines; When the first and second start pulses are simultaneously enabled, the odd shift register and the even shift register sequentially drive the output line, and in the first period, the first start pulse is enabled and the second start pulse is depressed. When enabled, the odd shift register sequentially drives the output line, and when the second start pulse is disabled in the second period alternated with the first period, the even shift when the first start pulse is disabled. A register drives the even output line sequentially.

The odd shift register shifts the first start pulse in response to a first clock signal, and the even shift register shifts the second start pulse in response to a second clock signal inverting the first clock signal.

According to an exemplary embodiment of the present disclosure, a gate driver may include: an odd shift register configured to have an odd stage connected to an odd gate line among a plurality of gate lines and slavely connected to a first start pulse input line; A dual shift register composed of an even shift register configured to have an even stage connected to an even gate line of the plurality of gate lines, the second shift register being slavely connected to a second start pulse input line; When the first and second start pulses are simultaneously enabled, the odd shift register and the even shift register sequentially drive the gate line, and in the first period, the first start pulse is enabled and the second start pulse is depressed. When enabled, the odd shift register sequentially drives the odd gate line, and when the second start pulse is enabled in the second period alternated with the first period, when the first start pulse is disabled, the even shift register. Sequentially drives the even gate line.

The odd shift register shifts the first start pulse in response to a first clock signal, and the even shift register shifts the second start pulse in response to a second clock signal inverting the first clock signal.

The gate driver further includes a level shifter connected between the dual shift register and the gate line.

An apparatus for driving a liquid crystal panel according to an exemplary embodiment of the present invention includes an image display unit having a liquid crystal cell matrix; The gate driver for driving the gate line of the image display unit; A data driver for supplying a data signal to the image display unit; And a timing controller for controlling the gate driver and the data driver, and supplying the data signal supplied in a progressive or interlaced manner to the data driver.

The timing controller simultaneously enables the first and second start pulses when the data signal is supplied in the progressive manner. When the data signal is supplied in the interlace manner, the first and second start pulses are alternately enabled in the first and second periods.

A method of driving a liquid crystal panel according to an exemplary embodiment of the present invention includes the steps of: inputting a data signal of at least one of a progressive data signal and an interlaced data signal; Enabling first and second start pulses simultaneously when the progressive data signal is input; The first start pulse is shifted using a first clock signal in an odd shift register connected to an odd gate line among a plurality of gate lines, and the second start pulse is second clocked in an even shift register connected to an even gate line. Displaying the progressive data signal by shifting using a signal to sequentially drive the plurality of gate lines; Enabling the first start pulse and enabling the second start pulse in an odd field when the data signal of the interlace method is input; Displaying the data signal of the odd field by shifting the first start pulse using the first clock signal in the odd shift register to drive the odd gate line; Enabling the second start pulse and enabling the first start pulse in an even field; Shifting the second start pulse using the second clock signal in the even shift register to drive the even gate line to display a data signal of the even field.

The first clock signal and the second clock signal are phase inverted.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 and 5.

4 is a block diagram illustrating a gate driver including a dual shift register according to an exemplary embodiment of the present invention.

The gate driver shown in FIG. 4 includes a dual shift register 30 for generating a scan signal, and a level shifter 40 for level shifting the scan signal to supply the gate lines GL1 to GLn.                     

The dual shift register 30 generates an odd shift register 32 for generating an odd scan pulse SLP1, SP3, ..., SPn-1 to be supplied to the odd gate lines GL1, GL3, ..., GLn-1. And an even shift register 34 for generating even scan pulses SP2, SP4, ..., SPn to be supplied to the even gate lines GL2, GL4, ... GLn.

The odd shift register 32 is dependent on the first gate start pulse GSP1 input line and is commonly connected to the gate shift clock GSC input line, and the odd stages ST1, ST3, ..., STn-1 It is provided. The odd stages ST1, ST3,..., STn-1 sequentially shift the first gate start pulse SP in response to the gate shift clock signal GSC to perform the odd gate lines GL1, GL3,... , GLn-1) generates the odd scan pulses SP1, SP3, ..., SPn-1. In the odd stages ST1, ST3,..., And STn-1, the first stage ST1 shifts the first gate start pulse GSP1 in response to the first gate clock signal GSC1, and the remaining odd stages. (ST3, ST5, ..., STn-1) shifts the scan pulse of the previous stage stage as a start pulse.

The even shift register 34 is dependently connected to the second gate start pulse GSP2 input line and is commonly connected to the inverted gate shift clock (/ GSC) input line through the inverter INV. , ..., STn). The even stages ST2, ST4,..., And STn sequentially shift the second gate start pulse GSP2 in response to the inverted gate shift clock signal / GSC, thereby allowing the even gate lines GL2, GL4,... Generates the odd scan pulses SP2, SP4, ..., SPn to be supplied to GLn). In the even stages ST2, ST4,..., And STn, the second stage ST2 shifts the second gate start pulse GSP2 in response to the inverted gate clock signal / GSC, and the remaining even stages ST2. , ST4, ..., STn) are shifted by inputting the scan pulse of the previous even stage as a start pulse.

The dual shift register 30 is driven in a progressive manner and an interlaced manner.

First, when driven in a progressive manner, the enabled first and second gate start pulses GSP1 and GSP2 are simultaneously supplied to the odd shift register 32 and the even shift register 34. The gate shift clock GSC is supplied to the odd shift register 32, and the gate shift clock / GSC inverted in phase is supplied to the even shift register 34. The toggle shift points at which scan pulses are generated in the odd shift register 32 and the even shift register 34 are alternated by the gate shift clocks GSC and / GSC, so the odd stages ST1, ST3, ..., STn-1 ) And even stages ST2, SR4, ..., STn alternately generate scan pulses SP1 to SPn. The scan pulses SP1 to SPn are level-shifted through the level shifter 40 and supplied to the gate lines GL1 to GLn, so that the gate lines GL1 to GLn are sequentially driven.

When driven in an interlaced manner, only the first gate start pulse GSP1 supplied to the odd shift register 32 in the odd field is enabled, and the second gate start pulse GSP2 supplied to the even shift register 34 is It is disabled. Accordingly, only the odd shift register 32 is driven to generate odd scan pulses SP1, SP3, ... SPn-1. The odd scan pulses SP1, SP3,..., SPn-1 are level-shifted through the level shifter 40 and supplied to the odd gate lines GL1, GL3,..., GLn-1. Only the lines GL1, GL3, ..., GLn-1 are driven sequentially.

In the even field, only the first gate start pulse GSP1 supplied to the odd shift register 32 is deactivated, and the second gate start pulse GSP2 supplied to the even shift register 34 is enabled. Accordingly, only the even shift register 34 is driven to generate even scan pulses SP2, SP4,... SPn. The even scan pulses SP2, SP4,..., And SPn are level shifted through the level shifter 40 and supplied to the even gate lines GL2, GL4,..., GLn, thereby providing the even gate lines GL2. , GL4, ..., GLn) are driven sequentially.

Accordingly, the gate driver may be driven in a progressive manner and an interlace manner.

FIG. 5 is a block diagram illustrating a liquid crystal display of the present invention having a gate driver shown in FIG. 4 and driven in a progressive manner and an interlaced manner.

The liquid crystal display shown in FIG. 5 includes a liquid crystal panel 2 having a pixel matrix, a gate driver 4 for driving gate lines GL1 to GLn of the liquid crystal panel 2, and a liquid crystal panel 2. A data driver 6 for driving the data lines DL1 to DLm, and a timing controller 8 for controlling the driving timing of the gate driver 4 and the data driver 6.

The liquid crystal panel 2 includes a pixel matrix composed of pixels formed at regions defined by intersections of the gate lines GL and the data lines DL. Each of the pixels includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell Clc. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. In addition, the liquid crystal cell Clc further includes a storage capacitor (not shown) so that the charged pixel signal is stably maintained until the next pixel signal is charged. In the liquid crystal cell Clc, an array state of liquid crystals having dielectric anisotropy varies according to pixel signals charged through the thin film transistor TFT, thereby adjusting grayscale.

The gate driver 4 drives the gate lines GL1 to GLn using the first and second gate start pulses GSP1 and GSP2 and the gate shift clock GSC from the timing controller 8. Specifically, when the first and second gate start pulses GSP1 and GSP2 are simultaneously enabled to be driven in a progressive manner, the gate driver 4 may perform the gate shift clock GSC and the inverted gate shift clock as described above. The gate lines GL1 to GLn are sequentially driven using the GSC. When the first and second gate start pulses GSP1 and GSP2 alternately enable the odd field and the even field to be driven in an interlaced manner, the odd gate lines are performed in the odd field and the even gate lines in the even field. Will be driven.

The data driver 6 shifts the source start pulse SSP from the timing controller 8 in accordance with the source shift clock SSC to generate a sampling signal. The data driver 6 latches the progressive or interlaced pixel data RGB input according to the source shift clock SSC according to the sampling signal, and then source output enable SOE. Supply line by line in response to the signal. The data driver 6 converts pixel data RGB, which is supplied in units of lines, into analog pixel signals using different gamma voltages, and supplies them to the analog pixel signals and supplies them to the data lines DL1 through DLm. Here, the data driver 6 determines the polarity of the pixel signal in response to the polarity control signal POL from the timing controller 8 when converting the pixel data into the pixel signal.

The timing controller 8 generates the first and second gate start pulses GSP1 and GSP2 and the gate shift clock GSC for controlling the gate driver 4, and the source start pulse for controlling the data driver 6. (SSP), source shift clock (SSC), source output enable signal (SOE), polarity control signal (POL), and the like. In addition, the timing controller 8 supplies the pixel data RGB supplied from the outside in a progressive manner or an interlaced manner to the data driver 6.

As described above, the gate driver including the dual shift register according to the present invention can be driven both in a progressive manner and in an interlace manner by simultaneously driving or alternately driving a separately configured odd and even shift register. Therefore, the apparatus and method for driving a liquid crystal panel using the dual shift register according to the present invention display a progressive video signal, and do not use a method of combining video signals input in an interlaced method or adding dummy data. It is possible to display video signals in an interlaced manner.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (9)

An odd shift register configured to be connected to a first start pulse input line and having an odd stage connected to an odd output line among a plurality of output lines, respectively; An even shift register configured to be evenly connected to a second start pulse input line and respectively connected to an even output line of the plurality of output lines; When the first and second start pulses are simultaneously enabled, the odd shift register and the even shift register sequentially drive the output line, When the first start pulse is enabled in the first period and the second start pulse is disabled, the odd shift register sequentially drives the odd output line and the second period in the second period alternated with the first period. And if the start pulse is enabled and the first start pulse is disabled, the even shift register sequentially drives the even output line. The method of claim 1, The odd shift register shifts the first start pulse in response to a first clock signal, And the even shift register shifts the second start pulse in response to a second clock signal inverting the first clock signal. An odd shift register configured to have an odd stage connected to an odd gate line among the plurality of gate lines, the odd shift register being slavely connected to the first start pulse input line; A dual shift register composed of an even shift register configured to have an even stage connected to an even gate line of the plurality of gate lines, the second shift register being slavely connected to a second start pulse input line; When the first and second start pulses are simultaneously enabled, the odd shift register and the even shift register sequentially drive the gate line, When the first start pulse is enabled in the first period and the second start pulse is disabled, the odd shift register sequentially drives the odd gate line, and the second period in the second period alternated with the first period. And if the start pulse is enabled and the first start pulse is disabled, the even shift register sequentially drives the even gate line. The method of claim 3, wherein The odd shift register shifts the first start pulse in response to a first clock signal, And said even shift register shifts said second start pulse in response to a second clock signal inverting said first clock signal. The method of claim 3, wherein And a level shifter coupled between the dual shift register and the gate line. An image display unit having a liquid crystal cell matrix; A gate driver according to any one of claims 3 to 5 for driving a gate line of the image display unit; A data driver for supplying a data signal to the image display unit; And a timing controller for controlling the gate driver and the data driver and for supplying a data signal supplied in a progressive or interlaced manner to the data driver. The method of claim 6, The timing controller Enabling the first and second start pulses simultaneously when the data signal is supplied in the progressive manner. And when the data signal is supplied in the interlace method, enabling the first and second start pulses alternately in the first and second periods. Inputting at least one of a progressive data signal and an interlaced data signal; Enabling first and second start pulses simultaneously when the progressive data signal is input; The first start pulse is shifted using a first clock signal in an odd shift register connected to an odd gate line among a plurality of gate lines, and the second start pulse is second clocked in an even shift register connected to an even gate line. Displaying the progressive data signal by shifting using a signal to sequentially drive the plurality of gate lines; Enabling the first start pulse and enabling the second start pulse in an odd field when the data signal of the interlace method is input; Displaying the data signal of the odd field by shifting the first start pulse using the first clock signal in the odd shift register to drive the odd gate line; Enabling the second start pulse and enabling the first start pulse in an even field; And driving the even gate line by shifting the second start pulse using the second clock signal in the even shift register to display a data signal of the even field. . The method of claim 8, And the first clock signal and the second clock signal are inverted in phase.

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