KR20120133881A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a driving method thereof are provided to reduce the load of a common voltage compensation circuit in a specific pattern by outputting a compensated common voltage when image data of the specific pattern is not inputted. CONSTITUTION: A display panel(10) includes data lines, gate lines, a lower substrate, and an upper substrate. A data driver circuit(120) converts inputted image data into a data voltage. A gate driver circuit(110) outputs a gate pulse to the gate lines. A pattern recognizing unit(150) outputs a control signal of a first logic or a second logic value by determining a specific pattern of the image data. A common voltage compensation circuit(160) outputs a compensated common voltage or a common voltage.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to a liquid crystal display including a common voltage compensation circuit and a driving method thereof.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

The liquid crystal cells of the liquid crystal display display an image on the display panel by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode. In order to reduce afterimages and prevent deterioration of the liquid crystal display, the liquid crystal display device is driven in an inversion scheme that periodically inverts the polarity of the data voltage applied to the liquid crystal. Recently, the LCD has been driven by a Z-inversion method that can prevent flicker of the display panel and reduce power consumption.

1 is a diagram illustrating a pattern type displayed on a display panel when driven in a Z-inversion manner. 2A and 2B are waveform diagrams showing data voltages supplied to data lines of a display panel when driven in a Z-inversion manner. When a black pattern, a mosaic pattern, and a white pattern are displayed on the display panel, the data driving circuit supplies data by direct current as shown in FIG. 2A. When the monochrome pattern, the vertical line pattern, the horizontal line pattern, and the sub vertical line pattern are displayed on the display panel, the data driving circuit supplies data by alternating current as shown in FIG. 2B.

Meanwhile, since the data line and the lower common voltage line cross each other on the lower substrate of the display panel, a common voltage compensation circuit exists to compensate that the common voltage of the lower common voltage line is affected by the data voltage of the data line. At this time, when a specific pattern such as a monochromatic pattern, a vertical line pattern, a horizontal line pattern, and a sub vertical line pattern is displayed on the display panel, since the data driving circuit supplies data with alternating current as shown in FIG. The problem arises that the load of.

The present invention provides a liquid crystal display device and a driving method thereof capable of reducing the load of the common voltage compensation circuit in a specific pattern.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a lower substrate on which data lines, gate lines intersecting the data lines, lower common voltage lines parallel to the gate lines, and an upper substrate on which upper common voltage lines are formed. A display panel comprising; A data driving circuit converting the input image data into a data voltage and outputting the converted data data to the data lines; A gate driving circuit sequentially outputting a gate pulse synchronized with the data voltage to the gate lines; When a specific pattern of the image data supplied to the data driving circuit is determined, a control signal of a first logic value is output when the image data of the specific pattern is not input, and a second logic when the image data of the specific pattern is input. A pattern recognition unit outputting a control signal of a value; And receiving a feedback common voltage of the lower common voltage line when the control signal of the first logic value is input, and outputting a compensated common voltage, and outputting a common voltage when the control signal of the second logic value is input. It includes a common voltage compensation circuit.

According to an exemplary embodiment of the present invention, a driving method of a liquid crystal display device includes data lines, gate lines intersecting the data lines, a lower substrate having lower common voltage lines parallel to the gate lines, and upper common voltage lines formed. A liquid crystal display comprising a display panel including an upper substrate, comprising: converting input image data into a data voltage and outputting the data voltage to the data lines; Sequentially outputting gate pulses synchronized with the data voltages to the gate lines; The control signal of the first logical value is output when the image data of the specific pattern is not input by determining the specific pattern of the image data, and the control signal of the second logic value is output when the image data of the specific pattern is input. Making; And receiving a feedback common voltage of the lower common voltage line when the control signal of the first logic value is input, and outputting a compensated common voltage, and outputting a common voltage when the control signal of the second logic value is input. Steps.

The present invention outputs a compensated common voltage only when image data of a specific pattern is not input, and does not output a compensated common voltage when image data of a specific pattern is input. As a result, the present invention can not only reduce the load of the common voltage compensation circuit in a specific pattern, but also reduce the power consumption generated due to the increase in the load of the common voltage compensation circuit.

1 is a diagram illustrating a pattern type displayed on a display panel when driven in a Z-inversion manner.
2A and 2B are waveform diagrams showing data voltages supplied to data lines of a display panel when driven in a Z-inversion manner.
3 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
4 is a view showing a Z-inversion driving method according to an embodiment of the present invention.
5 is a circuit diagram showing in detail a common voltage compensation circuit according to an embodiment of the present invention.
6A is a waveform diagram illustrating output waveforms of a control signal, a data voltage, a feedback common voltage, a DC common voltage, and a common voltage compensator of a first logic value.
6B is a waveform diagram illustrating output waveforms of a control signal, a data voltage, a feedback common voltage, a DC common voltage, and a common voltage compensator of a second logic value.
7 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. Component names used in the following description may be selected in consideration of ease of specification, and may be different from actual product part names.

3 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention. Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a gate driving circuit 110, a data driving circuit 120, a timing controller 130, a host system 140, The pattern recognition unit 150, the common voltage compensation circuit 160, and the like are included.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two substrates. The TFT array substrate of the liquid crystal display panel 10 has data lines D, gate lines G crossing the data lines D, and intersections of the data lines D and the gate lines G. FIG. TFTs formed therein, liquid crystal cells Clc connected to the TFTs, storage capacitors Cst, and the like are formed. The liquid crystal cells Clc are connected to a TFT and driven by an electric field between the pixel electrode 1 and the upper common electrode 2. The storage capacitor Cst is connected to the pixel electrode 1 and the lower common electrode to maintain the voltage charged in the pixel electrode 1 for a predetermined period of time. The black matrix, the color filter, the common electrode 2, and the like are formed on the color filter array substrate of the liquid crystal display panel 10. The lower common voltage line Vcom Line (B) is connected to the lower common electrode to supply a common voltage, and the upper common voltage line Vcom Line (U) is connected to the upper common electrode to supply a common voltage. The lower common voltage line Vcom Line (B) may be formed to be parallel to the gate lines.

A polarizing plate is attached to each of the TFT array substrate and the color filter array substrate of the liquid crystal display panel 10. On each of the TFT array substrate and the color filter array substrate, the alignment layer for setting the pre-tilt angle of the liquid crystal molecules is formed on the surface in contact with the liquid crystal layer. The liquid crystal display panel 10 has been described focusing on being implemented in twisted nematic (TN) mode.

The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The data driver circuit 120 includes a plurality of source drive ICs. The data driving circuit 120 latches the image data RGB input from the timing controller 130 in response to a data timing control signal described later. The data driving circuit 120 converts the image data RGB into an analog positive / negative gamma compensation voltage in response to the polarity control signal POL to generate a positive / negative data voltage. The positive / negative data voltages output from the data driving circuit 120 are supplied to the data lines D. The source drive ICs of the data driving circuit 120 may be connected to the data lines D of the liquid crystal display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driving circuit 110 sequentially supplies gate pulses synchronized with the data voltage to the gate lines G in response to gate timing control signals described later. The gate driving circuit 110 may be formed directly on the TFT array substrate of the liquid crystal display panel 10 by using a gate in panel (GIP) method or may be connected to the gate lines G of the liquid crystal display panel 10 by a TAB method. have.

The timing controller 130 supplies the image data RGB input from the host system 140 to the data driving circuit 120. The timing controller 130 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable (DE), and a dot clock CLK from the host system 140. Timing control signals for controlling the operation timing of the driving circuit 120 and the gate driving circuit 110 are generated. The timing control signals include a gate timing control signal for controlling the operation timing of the gate driving circuit 110 and a data timing control signal for controlling the operation timing of the data driving circuit 120 and the polarity of the data voltage.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, a source output enable signal SOE, and the like. The source start pulse SSP controls the data sampling start timing of the data driving circuit 120. The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source drive ICs based on a rising or falling edge. The source output enable signal SOE controls the output timing of the data driver circuit 120. The polarity control signal POL indicates the polarity inversion timing of the data voltage output from the data driving circuit 120.

The host system 140 includes a system on chip (hereinafter referred to as "SoC") in which a scaler is built, and displays image data RGB inputted from an external video source device on the display panel 10. You can convert to a data format of a resolution suitable for display. The host system 140 transmits image data RGB and timing signals Vsync, Hsync, DE, and CLK through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. 130).

The pattern recognition unit 150 receives the image data RGB from the timing controller 130 and analyzes the pattern of the input image data RGB. The pattern recognition unit 150 determines whether the input image data RGB is a specific pattern of the monochrome pattern, the vertical line pattern, the horizontal line pattern, and the sub vertical line pattern of FIG. 1. The pattern recognition unit 150 generates the control signal Sc of the first logic value when the input image data RGB is not a specific pattern. The pattern recognition unit 150 generates a control signal Sc of a second logic value when the input image data RGB is a specific pattern. For example, the control signal Sc of the first logic value may occur at a high logic level H (or '1'), and the control signal Sc of the second logic value may be a low logic level L ( Or '0').

For example, the pattern recognition unit 150 looks at a method of recognizing the sub vertical line pattern of FIG. 1 as a specific pattern. First, the pattern recognizing unit 150 may include the Nth line of the Lth line of the display panel 10 (where L is 1 ≦ L ≦ p and p is the number of gate lines of the display panel 10). N ≦ q, q is the number of data lines of the display panel 10) and the gray level of the N + 1th pixel data is compared. Second, the pattern recognizing unit 150 has a case where the N + 1th pixel data is black gray when the Nth pixel data is white gray, and when the N + 1th pixel data is white gray when the Nth pixel data is black gray. Counts. Third, when the count is greater than or equal to a predetermined threshold, the pattern recognition unit 150 determines whether the first pixel data of the L-th line and the first pixel data of the L + 1th line are both white gray or black gray. To judge. Fourth, when the first pixel data of the L th line and the first pixel data of the L + 1 th line are both white or black gradations, the pattern recognition unit 150 may input the image data RGB of FIG. 1. It is determined that the sub vertical line pattern. The pattern recognition unit 150 may recognize the monochrome pattern, the vertical line pattern, and the horizontal line pattern of FIG. 1 as a specific pattern in a similar manner.

The common voltage compensation circuit 160 receives the control signal Sc from the pattern recognition unit 150, and either one of the DC common voltage Vcom_DC and the compensated common voltage Vcom_Comp according to the input control signal Sc. Outputs In detail, the common voltage compensating circuit 160 converts the compensated common voltage Vcom_comp into the lower common voltage line Vcom Line (B) and the upper common voltage line when the control signal Sc of the first logic value is input. To Vcom Line (U)). When the control signal Sc of the second logic value is input, the common voltage compensating circuit 160 converts the DC common voltage Vcom_DC into the lower common voltage line Vcom Line (B) and the upper common voltage line Vcom Line (U). Output to)). A detailed description of the common voltage compensation circuit 160 will be described later with reference to FIG. 5.

4 is a view showing a Z-inversion driving method according to an embodiment of the present invention. 4 shows the polarity of the data voltage supplied to some of the pixels of the display panel 10 in the odd frame.

Referring to FIG. 4, in Z-inversion driving, the data driving circuit 120 supplies a positive data voltage to odd data lines in a odd frame and a negative data voltage to even data lines. In this case, the pixels of the display panel 10 are driven by a dot inversion method in which polarities are inverted every one dot. That is, in the Z-inversion method, although the data driving circuit 120 is driven in the column inversion method, the pixels of the display panel 10 are driven in the dot inversion method.

Meanwhile, when driving the monochrome pattern, the vertical line pattern, the horizontal line pattern, and the sub vertical line pattern of FIG. 1 in a Z-inversion manner, the data driving circuit 120 applies a data voltage as shown in FIG. 2B by alternating current. . As a result, the lower common voltage line Vcom Line (B) intersecting with the data lines of the display panel 10 is affected by a short period of approximately 1 to 2 horizontal periods. Therefore, a problem arises in that the load of the common voltage compensation circuit 160 to compensate for the common voltage Vcom of the lower common voltage line Vcom Line (B) becomes large. However, according to the present invention, the pattern recognition unit 150 and the common voltage compensation circuit 160 recognize a specific pattern in question and do not perform common voltage compensation when the image data RGB of the specific pattern is input. The load of the common voltage compensation circuit 160 can be reduced. Hereinafter, the operation of the common voltage compensation circuit 160 according to the control signal Sc of the pattern recognition unit 150 of the present invention will be described in detail with reference to FIGS. 5 to 7.

5 is a circuit diagram showing in detail a common voltage compensation circuit according to an embodiment of the present invention. Referring to FIG. 5, the common voltage compensating circuit 160 according to the control signal Sc of the pattern recognizing unit 150 of the DC common voltage Vcom_DC and the lower common voltage line Vcom Line (B). The switch circuit 161 outputs any one of the feedback common voltages Vcom_FB and a common voltage compensator 162 that outputs the common voltage Vcom_comp compensated according to the input feedback common voltage Vcom_FB.

The switch circuit 161 includes an inverter Inv, a first switch SW1, and a second switch SW2. The inverter Inv inverts the control signal Sc. That is, the inverter Inv inverts the control signal Sc of the first logic value to the second logic value and inverts the control signal Sc of the second logic value to the first logic value.

The first switch SW1 receives the control signal Sc as it is from the pattern recognition unit 150. Accordingly, the first switch SW1 is turned on when the control signal Sc of the first logic value is input to the switch circuit 160, and the control signal Sc of the second logic value is switched to the switch circuit 160. It is turned off when entered.

In contrast, the second switch SW2 receives the control signal Sc inverted by the inverter Inv. That is, the control signal Sc of the first logic value is inverted to the second logic value and input to the second switch SW2, and the control signal Sc of the second logic value is inverted to the first logic value and thus the first logic value. It is input to the switch SW1. Accordingly, the second switch SW2 is turned off when the control signal Sc of the first logic value is input to the switch circuit 160, and the control signal Sc of the second logic value is switched to the switch circuit 160. When entered, it is turned on.

The common voltage compensator 162 includes an inverting amplifier OP-amp, a first resistor R1, and a second resistor R2. The inverting amplifier OP-amp is input to the negative terminal to which the output of the switch circuit 161 is input, the positive terminal to which the DC common voltage Vcom_DC is input, and the negative terminal and the positive terminal. And an output terminal (out) for inverting and amplifying the difference in voltage at a predetermined compensation ratio. The output terminal out of the inverting amplifier OP-amp is connected to the upper common voltage line Vcom Line (U) and the lower common voltage line Vcom Line (B). The first resistor R1 is connected to the input terminal of the (-) terminal and the switch circuit 161, and the second resistor R2 is connected to the input terminal and the output terminal (out) of the (-) terminal.

The inverting amplifier OP-amp inverts and outputs a difference between the voltage input to the negative terminal and the voltage input to the positive terminal as shown in Equation 1 at a predetermined compensation ratio.

In Equation 1, Vout means a voltage output to the output terminal (out), Vp means a voltage input to the (+) terminal, Vn means a voltage input to the (-) terminal. The predetermined compensation ratio is R2 / R1, and the predetermined compensation ratio may be predetermined through a preliminary experiment.

When the feedback common voltage Vcom_FB is input from the switch circuit 161 to the negative terminal of the inverting amplifier OP-amp, Vp is the DC common voltage Vcom_DC and Vn is the feedback common voltage Vcom_FB. )to be. In this case, the inverting amplifier Op-amp outputs the output voltage Vout calculated by Equation 1 as the compensated common voltage Vcom_comp. In addition, when the DC common voltage Vcom_DC is input from the switch circuit 161 to the negative terminal of the inverting amplifier OP-amp, Vp represents the DC common voltage Vcom_DC and Vn represents the DC common voltage. It can be calculated as (Vcom_DC). In this case, since Vp and Vn are the same in Equation 1, the inverting amplifier OP-amp outputs Vp, that is, a DC common voltage Vcom_DC. The feedback common voltage Vcom_FB, the DC common voltage Vcom_DC, and the compensated common voltage Vcom_comp will be described in detail with reference to FIGS. 6A and 6B.

The common voltage compensation circuit 160 includes a third resistor R3 connected to the connection terminal of the upper common voltage line Vcom Line (U) and the connection terminal of the lower common voltage line Vcom Line (B). The third resistor R3 is greater than the total resistance of the common voltage compensator 162. This is to allow the feedback common voltage Vcom_FB of the lower common voltage line Vcom Line (B) to be input to the switch circuit 161 instead of the output terminal (out) of the inverting amplifier OP-amp.

6A is a waveform diagram illustrating output waveforms of a feedback common voltage, a DC common voltage, and a common voltage compensation circuit input to a control signal, a data voltage, and a common voltage compensation circuit of a first logic value. Referring to FIG. 6A, the control signal Sc is generated at the high logic level H, which is the first logic value. The data voltage Vdata has been described based on the supply to the data lines in the sub vertical line pattern of FIG. 1. At this time, the data voltage Vdata alternately generates a positive white gray voltage and a black gray voltage at intervals of one horizontal period. The feedback common voltage Vcom_FB of the lower common voltage line Vcom Line (B) input to the common voltage compensation circuit 160 is affected every time the data voltage Vdata rises to the white gray voltage. The DC common voltage Vcom_DC is supplied with a DC voltage of a common voltage level. The output voltage Vout of the common voltage compensator 162 of the common voltage compensation circuit 160 is a compensated common voltage Vcom_comp obtained by inverting and amplifying the feedback common voltage Vcom_FB at a predetermined compensation ratio.

In summary, when the control signal Sc of the first logic value is input, the common voltage compensation circuit 160 is input to the voltage input to the negative terminal of the inverting amplifier OP-amp and to the positive terminal. The voltage difference is inverted and amplified and output to the output terminal (out). Accordingly, the voltage output from the inverting amplifier OP-amp is the compensated common voltage Vcom_comp obtained by inverting and amplifying the feedback common voltage Vcom_FB at a predetermined compensation ratio as shown in FIG. 6A.

6B is a waveform diagram illustrating output waveforms of a control signal, a data voltage, a feedback common voltage, a DC common voltage, and a common voltage compensator of a second logic value. Referring to FIG. 6B, the control signal Sc is generated at the low logic level L, which is the second logic value. The data voltage Vdata has been described based on the supply to the data lines in the sub vertical line pattern of FIG. 1. At this time, the data voltage Vdata alternately generates a positive white gray voltage and a black gray voltage at intervals of one horizontal period. The feedback common voltage Vcom_FB of the lower common voltage line Vcom Line (B) input to the common voltage compensation circuit 160 is affected every time the data voltage Vdata rises to the white gray voltage. The DC common voltage Vcom_DC is supplied with a DC voltage of a common voltage level. As the output voltage Vout of the common voltage compensator 162 of the common voltage compensation circuit 160, the DC common voltage Vcom is output as it is.

In summary, when the control signal Sc of the second logic value is input, the common voltage compensating circuit 160 is input to the voltage input to the negative terminal of the inverting amplifier OP-amp and to the positive terminal. The voltage is the same as the DC common voltage Vcom. Therefore, the voltage Vout output from the inverting amplifier OP-amp is a DC common voltage Vcom_DC as shown in FIG. 6B.

7 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention. Hereinafter, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3, 5, and 7.

First, the pattern recognizing unit 150 determines whether the input image data RGB is a specific pattern of the monochrome pattern, the vertical line pattern, the horizontal line pattern, and the sub vertical line pattern of FIG. 1. The pattern recognition unit 150 generates a control signal Sc of the first logic value when the image data RGB is not a specific pattern, and controls the control signal of the second logic value when the image data RGB is a specific pattern. Sc). (S1 to S3)

Secondly, the first switch SW1 of the switch circuit 161 of the common voltage compensation circuit 160 is turned on in response to the control signal Sc of the first logic value. Since the control signal Sc of the first logic value is inverted and input to the second switch SW2 by the inverter Inv, the second switch SW2 is turned in response to the control signal Sc of the first logic value. -Not on. That is, since the first switch SW1 is turned on in response to the control signal Sc of the first logic value, the switch circuit 161 supplies the feedback common voltage Vcom_FB of the lower common voltage line Vcom Line (B). )

The feedback common voltage Vcom_FB is input to the negative terminal of the inverting amplifier OP-amp of the common voltage compensation circuit 162 of the common voltage compensation circuit 160, and the DC common voltage Vcom_DC is input to the positive terminal of the common voltage compensation circuit 160. Is input. The output terminal of the inverting amplifier OP-amp outputs the compensated common voltage Vcom_comp to the upper common voltage line Vcom Line (U) and the lower common voltage line Vcom Line (B). (S4)

Third, the first switch SW1 of the switch circuit 161 of the common voltage compensation circuit 160 is not turned on in response to the control signal Sc of the second logic value. Since the control signal Sc of the second logic value is inverted and input to the second switch SW2 by the inverter Inv, the second switch SW2 is applied to the inversion signal of the control signal Sc of the second logic value. It is turned on in response. That is, since the second switch SW2 is turned on in response to the inverted signal of the control signal Sc of the second logic value, the switch circuit 161 outputs the DC common voltage Vcom_DC.

The DC common voltage Vcom_DC is input to the negative terminal of the inverting amplifier OP-amp of the common voltage compensation unit 162 of the common voltage compensation circuit 160, and the DC common voltage Vcom_DC is input to the positive terminal. Is input. The output terminal of the inverting amplifier OP-amp outputs a DC common voltage Vcom_DC to the upper common voltage line Vcom Line (U) and the lower common voltage line Vcom Line (B) as shown in Equation 2. (S5)

As described above, the present invention outputs a compensated common voltage only when image data of a specific pattern is not input, and does not output a compensated common voltage when image data of a specific pattern is input. As a result, the present invention can not only reduce the load of the common voltage compensation circuit in a specific pattern, but also reduce the power consumption generated due to the increase in the load of the common voltage compensation circuit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 110: gate driving circuit
120: data driving circuit 130: timing controller
140: host system 150: pattern recognition unit
160: common voltage compensation circuit 161: switch circuit
162: common voltage compensation unit

Claims (9)

A display panel including data lines, gate lines crossing the data lines, a lower substrate having lower common voltage lines parallel to the gate lines, and an upper substrate having upper common voltage lines formed thereon;
A data driving circuit converting the input image data into a data voltage and outputting the converted data data to the data lines;
A gate driving circuit sequentially outputting a gate pulse synchronized with the data voltage to the gate lines;
When a specific pattern of the image data supplied to the data driving circuit is determined, a control signal of a first logic value is output when the image data of the specific pattern is not input, and a second logic when the image data of the specific pattern is input. A pattern recognition unit outputting a control signal of a value; And
When the control signal of the first logic value is input, the common common voltage is output by receiving the feedback common voltage of the lower common voltage line and the common voltage is output when the control signal of the second logic value is input. Liquid crystal display comprising a voltage compensation circuit. The method of claim 1,
The common voltage compensation circuit,
An inverter for inverting the control signal, a first switch that is turned on when the control signal of the first logic value is input and outputs the feedback common voltage, and a turn when the control signal of the second logic value is input A switch circuit comprising a second switch turned on to output a DC common voltage; And
The difference between the (-) terminal to which the output of the switch circuit is input, the (+) terminal to which the DC common voltage is input, the voltage input to the (-) terminal and the voltage input to the (+) terminal are predetermined. And a common voltage compensator including an output terminal for inverting and amplifying and outputting the inverted amplification at a compensation ratio of. The method of claim 2,
Wherein the common-
A first resistor connected to the switch circuit and an input terminal of the negative terminal; And
And a second resistor connected to the input terminal of the (-) terminal and the output terminal. The method of claim 3, wherein
Wherein the predetermined compensation ratio is a value obtained by dividing the second resistor by the first resistor. The method of claim 3, wherein
The common voltage compensation circuit,
And a third resistor connected to the connection terminal of the lower common voltage line and the connection terminal of the upper common voltage line. The method of claim 5, wherein
The total resistance of the common voltage compensator is smaller than the third resistor. The method of claim 1,
The pattern recognition unit,
Recognize any one of a monochrome pattern, a vertical line pattern, a horizontal line pattern, and a sub vertical line pattern as the specific pattern, or recognize the monochrome pattern, a vertical line pattern, a horizontal line pattern, and a sub vertical line pattern as the specific pattern. Liquid crystal display characterized in that. And a display panel including data lines, gate lines crossing the data lines, a lower substrate on which lower common voltage lines are parallel to the gate lines, and an upper substrate on which upper common voltage lines are formed. In the liquid crystal display device,
Converting the input image data into a data voltage and outputting the converted data data to the data lines;
Sequentially outputting gate pulses synchronized with the data voltages to the gate lines;
The control signal of the first logical value is output when the image data of the specific pattern is not input by determining the specific pattern of the image data, and the control signal of the second logic value is output when the image data of the specific pattern is input. Making; And
Outputting a compensated common voltage by receiving a feedback common voltage of the lower common voltage line when the control signal of the first logic value is input, and outputting a common voltage when the control signal of the second logic value is input; Method of driving a liquid crystal display device comprising a. The method of claim 8,
The control signal of the first logical value is output when the image data of the specific pattern is not input by determining the specific pattern of the image data, and the control signal of the second logic value is output when the image data of the specific pattern is input. The steps are
Recognize any one of a monochrome pattern, a vertical line pattern, a horizontal line pattern, and a sub vertical line pattern as the specific pattern, or recognize the monochrome pattern, a vertical line pattern, a horizontal line pattern, and a sub vertical line pattern as the specific pattern. The driving method of the liquid crystal display device characterized in that the step.

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