KR101217511B1 - Liquid Crystal Display device and display methode using the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and an image realization method thereof capable of resolving partial luminance unevenness in a GIP liquid crystal display device. will be.

To this end, the present invention is a liquid crystal panel for displaying an image in a frame unit including a blanking period, the horizontal and vertical pixel array in the form of a matrix in the vertical and horizontal arrangement of the gate line and the data line; Polarity inversion indicating an alternating frame control signal, data, and an odd number of polarity inversion peaks in the blanking section and a positive and negative polarity inversion peaks corresponding to each horizontal pixel string in the frame. A timing controller for generating an image control signal including a signal; A gate driver which generates a gate signal for sequentially enabling the horizontal pixel array based on the frame control signal and scans and supplies the gate line to the gate line; A liquid crystal display device including a data driver configured to generate a data signal indicating a polarity state according to the polarity inversion signal and to charge each of the enabled horizontal pixel columns based on the data and the image control signal and to supply the data signal to the data line; It provides an image realization method thereof.

Description

Liquid Crystal Display Device and display methode using the same}

1 is a block diagram of a general liquid crystal display device.

2 is a timing diagram of a general GIP liquid crystal display device.

3 is a conceptual diagram of an image realization method of a general GIP liquid crystal display device;

4 is a partial block diagram of a liquid crystal display according to the present invention.

5 is a conceptual diagram of an image realization method of the liquid crystal display according to the present invention;

<Description of the symbols for the main parts of the drawings>

110: liquid crystal panel 112: gate line

114: data line 140: drive circuit

142: timing controller 162: gate driver

172: Data Driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and an image realization method thereof capable of resolving partial luminance unevenness in a GIP liquid crystal display device. will be.

The liquid crystal display device, which is most active in the field of TVs and monitors because of its advantage in moving image display and high contrast ratio, is characterized by optical anisotropy and polarization properties of liquid crystals. The principle of image realization using polarization is shown as an essential component of a liquid crystal panel bonded through a liquid crystal layer between two substrates, and the arrangement direction of liquid crystal molecules is changed by an electric field in the liquid crystal panel. The difference is generated and the difference in transmittance of the liquid crystal panel is projected to the outside with a separate back light emitted from the back light to display a desired image.

Recently, an active matrix type, in which pixels, which are basic units of image expression, are arranged in a matrix and individually controlled by using a thin film transistor (TFT), is widely used. 1 is a block diagram of a general liquid crystal display device, and may be divided into a liquid crystal panel 10 for direct image realization and a driving circuit unit 40 for supplying various electric signals required for image realization thereof.

First, the liquid crystal panel 10 includes a liquid crystal layer and first and second substrates bonded side by side with a liquid crystal layer interposed therebetween, and a plurality of gate lines 12 and data are formed on an inner surface of a first substrate called an array substrate. Lines 22 are arranged in an alternating manner to define vertical and horizontal pixel columns in a matrix form, and thin film transistors T are provided at each intersection thereof to correspond one-to-one with pixel electrodes mounted in each pixel P. FIG. Connected. The second substrate, called a color-filter substrate, is provided with a common electrode facing the pixel electrode with a color filter and a liquid crystal layer interposed therebetween for color realization. In addition, the pixel electrode and the common electrode form a liquid crystal capacitor Clc.

Next, the driving circuit 40 includes an interface 42, a timing controller 44, a gate driver 52 and a data driver 62, and a reference voltage generator 72, a power supply voltage generator 74, etc., the interface 42 relays an external drive system such as a personal computer and the timing controller 44, and the timing controller 44 generates data and control signals. To the gate and data drivers 52 and 62. In addition, the gate driver 52 and the data driver 62 are connected to the gate line 12 and the data line 22, respectively, and the gate driver 52 responds to the frame control signal input from the timing controller 44. Each gate line 12 is sequentially enabled for each frame by one horizontal synchronizing time, so that the thin film transistor T for each gate line 12 is controlled on / off and the data driver Reference numeral 62 selects the reference voltages corresponding to the data in response to the data and the image control signal input from the timing controller 44 and supplies it to the data line 22. As a result, when the thin film transistor T selected for each gate line 12 is turned on by the gate signal of the gate driver 52, the data signal of the data driver 62 is pixeld through each thin film transistor T. The liquid crystal is driven to (P), and the liquid crystal is driven by the electric field between the pixel electrode and the common electrode. During this process, the reference voltage generation unit 72 generates a digital to analog converter (DAC) reference voltage of the data driver 62, and the power supply voltage generation unit 74 operates for each element of the driving circuit unit 40. The power supply and the common electrode voltage of the liquid crystal panel 10, that is, the common voltage are supplied.

On the other hand, when a direct current (DC) voltage is applied to the liquid crystal for a long time, ionic impurities in the liquid crystal are fixed by an electric field, and when deepen, the pre-tilt value of the liquid crystal molecules changes, making it difficult to control the purpose. As a result, deterioration of image quality such as image sticking is followed. In order to prevent this, an inversion method of inverting the polarity of a data signal, which is a liquid crystal driving voltage, is adopted. Frame inversion for inverting the overall polarity of the data signal for each frame, line inversion for inverting the polarity of the data signal for each gate line 12 within the same frame, or up, down, left, or right. There is a dot inversion for inverting the polarity of the data signal for each pixel P such that adjacent pixels P exhibit opposite polarities to each other.

Meanwhile, the liquid crystal display device may be classified into amorphous silicon (a-Si) and polysilicon (poly silicon: poly-Si) according to the material type of the semiconductor layer serving as the conductive channel in the thin film transistor (T). When the amorphous silicon is used, the gate driver 52 and the data driver 62 are separately provided outside the liquid crystal panel 10 as shown in the drawing, respectively, and the gate line 12 may be provided through a tape carrier package (TCP) or the like. Is connected to the data line 22, but recently introduced a GIP (Gate In Panel) liquid crystal display device that mounts part or all of the gate driver 52 into the liquid crystal panel 10 while using amorphous silicon. It became.

In addition, the GIP liquid crystal display adopts an overlap driving method of overlapping a portion of the gate signal scanned to each gate line 12 so as to compensate for the low electric field mobility of the amorphous silicon. FIG. 2 is a timing diagram illustrating an overlap driving method of a general GIP liquid crystal display, and VG1 to VGn are respectively scanned from the first G1 gate line to the last Gn gate line to implement a frame of the GIP liquid crystal display. The gate signal is represented, Vcom is a common voltage, and VD is a data signal supplied to the horizontal pixel column of each gate line. At this time, each gate line is enabled by the high potential voltage of the gate signal, and the data signal has a line inversion scheme as an example (see FIG. 1).

As a result, the horizontal pixel array of the first G1 gate line is enabled during T1 by the high potential voltage of the VG1 gate signal, and is charged with any negative polarity for 1H by the data signal synchronized with the VG1 gate signal. )do. In the horizontal pixel column of the second G2 gate line, the high potential voltage of the VG2 gate signal, which has the same input timing as the VG1 gate signal, is supplied during T2 (T2> T1), and overlaps the high potential voltage of the VG1 gate signal. The high potential voltage front end of the VG2 gate signal constitutes a preliminary overlap section (a) for sufficiently opening the thin film transistor connected to the G2 gate line. Thus, when the horizontal pixel array of the G2 gate line is enabled to the desired degree, the VG2 gate The negative polarity data signal is charged by the charging end section b of the signal high potential voltage. In addition, the VG3 gate signal for the G3 gate line represents the high potential voltage of T2 partially overlapping the high potential voltage of the VG2 gate signal. The data signal is charged for 1H by forming the overlap section (a) to enable sufficiently and the charging section (b) at the rear end, wherein the data signal supplied to the horizontal pixel column of the G3 gate line is the horizontal pixel column of the G2 gate line. Unlike that supplied to, the polarity is inverted, and as a result, the data signal of positive polarity is charged for 1H in the horizontal pixel column of the G3 gate line. The overlapping relationship between the VG2 and VG3 gate signals is sequentially shown up to the GVn gate signal including the VG3 and VG4 gate signals, and the polarity of the data signal is the trailing end of the high potential voltage of the GVn gate signal below the GV3 gate signal. Inverted in accordance with the interval b.

At this time, as can be seen from the drawings and the above description, in the general GIP liquid crystal display, the data signal supplied to the horizontal pixel columns of the first G1 gate line and the second G2 gate line shows the same polarity, which is the polarity inversion of the data signal. The cause can be found after the G2 gate line, that is, proceeding from the horizontal pixel row of the G3 gate line, which causes local luminance unevenness in the display image in association with the overlap driving of the GIP liquid crystal display.

More specifically, the reason why the polarity inversion of the data signal proceeds from the horizontal pixel array of the G3 gate line is to control the polarity inversion timing uniformly throughout the liquid crystal panel, although the polarity inversion of the data signal is the horizontal pixel of the G2 gate line. It is possible to realize the polarity reversal of the data signal of all horizontal pixel columns if it is made from the column.However, the polarity reversal timing of the data signal is determined by the various factors such as the signal delay and the unique characteristics of the device. It is virtually impossible to control precisely from the column. Therefore, the polarity inversion of the data signal is artificially delayed by 1H, so that it is controlled to proceed based on the horizontal pixel column of the G3 gate line.

However, the current resolution of the liquid crystal display device is 1,024 × 768, 800 × 600, 640 × 480, and the number of horizontal pixel columns is even, so the above-mentioned phenomenon, that is, the first horizontal pixel column and the second horizontal pixel The same polarity of data signal for the column is repeated every frame, and when it is associated with the overlap driving method of the GIP LCD, the second horizontal pixel column eventually results in charging the data signal of the same polarity for 2H. It causes a partial luminance non-uniformity phenomenon in which the luminance of the horizontal pixel rows is changed.

3 is a conceptual diagram showing the timing of some signals and the polarity inversion state of the liquid crystal panel for displaying an arbitrary n frame and a subsequent n + 1 frame in image implementation of a general GIP liquid crystal display device. For convenience, it is assumed to be XGA (1024 × 768) resolution with 1024 horizontal pixels, and DE (Data Enable) indicating valid data intervals in horizontal pixels and when to deliver latched data by horizontal pixels In order to indicate polarity inversion of data signals for each SOE (Source Output Enable) and horizontal pixel sequence, a polarity reverse (POL) signal in which positive and negative polarity inversion peaks are alternately displayed is displayed.

As seen from this, the polarity of the last data signal at the end of the n-frame, that is, the data signal supplied to the 1024th horizontal pixel column, represents a negative polarity by the negative polarity inversion peak of the POL. Since the positive polarity inversion peak of the POL is invariant during the blanking interval, the data signal polarity of the first horizontal pixel sequence of the n + 1 frame also represents positive polarity. Considering the 1H delay of the POL, the second horizontal pixel sequence of the n + 1 frame is also charged with the same positive polarity data signal as the first horizontal pixel sequence. From the third horizontal pixel sequence of the n + 1 frame, the negative polarity inversion peak and the positive polarity inversion peak of the POL alternately appear in synchronization with the SOE. The polarity and the positive polarity are alternately shown.

For the same reason, the data signals of the first and second horizontal pixel columns of n frames also have the same polarity.

Based on this, it can be seen that in general GIP liquid crystal display, the data signal polarity of the first and second horizontal pixel columns is the same in every frame. In relation to the overlap driving, the second horizontal pixel column has the same polarity for 2H. As the data signal is supplied, the charging time of the corresponding horizontal pixel column is relatively increased, so that the liquid crystal driving is relatively large, which causes a luminance unevenness in which the luminance of the second horizontal pixel column is incorrect.

Accordingly, an object of the present invention is to solve the above problems, and to solve a partial luminance non-uniformity phenomenon of the GIP liquid crystal display device.

According to an aspect of the present invention, there is provided a liquid crystal panel which displays an image in units of frames including a blanking section and defines horizontal and vertical pixel columns in a matrix form in a vertical and horizontal arrangement of gate lines and data lines; Polarity inversion indicating an alternating frame control signal, data, and an odd number of polarity inversion peaks in the blanking section and a positive and negative polarity inversion peaks corresponding to each horizontal pixel string in the frame. A timing controller for generating an image control signal including a signal; A gate driver which generates a gate signal for sequentially enabling the horizontal pixel array based on the frame control signal and scans and supplies the gate line to the gate line; A liquid crystal display device comprising a data driver configured to generate a data signal indicating a polarity state according to the polarity inversion signal and to charge each of the enabled horizontal pixel columns based on the data and the image control signal, and supply the data signal to the data line; to provide.

The horizontal pixel column may be divided into a first horizontal pixel column in which the data signal is initially charged and a second or less horizontal pixel column in which the data signal is subsequently charged, and all horizontal pixel columns including the first horizontal pixel column are In addition, each of the adjacent horizontal pixel rows and the opposite polarity is characterized in that the charge.

The image control signal may further include an odd number of data latch signals in the blanking section for synchronizing the odd number of polarity inversion peaks in the blanking section.

The liquid crystal panel may further include a thin film transistor provided at an intersection point of the gate line and the data line and having a semiconductor layer made of amorphous silicon, wherein the gate driver is mounted in the liquid crystal panel. The gate signals scan-transferred to the respective gate lines overlap each other.

In addition, the present invention is an image realization method of a liquid crystal display device comprising a liquid crystal panel in which horizontal and vertical pixel columns are defined in a matrix so as to display an image in a frame unit subsequent to the blanking period, wherein an odd number of polarities in the blanking period are provided. Generating a polarity inversion signal alternately representing positive (+) and negative (-) polarity inversion peaks for polarity inversion within the frame including an inversion peak; And each horizontal pixel column is sequentially enabled in the frame, and each of the enabled horizontal pixel columns is charged according to the polarity inversion state of the polarity inversion signal. to provide.

In this case, the horizontal pixel column is divided into a first horizontal pixel column in which the data signal is initially charged and a second or less horizontal pixel column in which the data signal is subsequently charged, and all horizontal pixel columns including the first horizontal pixel column are adjacent to each other. It is characterized in that the horizontal pixel array and the opposite polarity is charged.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

4 is a block diagram illustrating a part of the liquid crystal display according to the present invention, in which part of the driving circuit unit 140 including the liquid crystal panel 110 is shown.

In this case, the liquid crystal panel 110 includes a liquid crystal layer and two substrates bonded side by side with the liquid crystal layer interposed therebetween, of which the gate line 112 in the horizontal direction and the data line 114 in the vertical direction cross vertically and horizontally on the inner surface of the first substrate. Thus, a matrix form of horizontal and vertical pixel columns is defined, and thin film transistors T are provided at intersections of the gates and data lines 112 and 114 so as to correspond one-to-one with pixel electrodes mounted in each pixel P. In addition, a color filter and a common electrode for color implementation are provided on the inner surface of the second substrate, whereby the pixel electrode, the common electrode, and the liquid crystal layer form a liquid crystal capacitor Clc.

Next, the driving circuit unit 140 includes a timing controller 142 and gates and data drivers 162 and 172. In addition, although not shown in the drawings, an interface and a data driver relaying an external driving system and the timing controller 142 may be provided. A reference voltage generator for generating a reference voltage used in the operation 172, a power supply voltage generator for supplying a common voltage of the liquid crystal panel 110 and an operating power source for each component of the driving circuit unit 140 may be provided.

Accordingly, data and various control signals transmitted from an external driving system are transmitted to the timing controller 142 by an interface. The data includes luminance information of an image to be displayed through the pixels P of the liquid crystal panel 110. Various control signals include a vertical synchronous signal (Vsync) indicating the start or end of the frame screen, a horizontal synchronous signal (Hsync) indicating the start or end of the horizontal pixel sequence, and a horizontal synchronous signal within the horizontal pixel sequence. DE (Data Enable) for indicating the valid data interval, Data Clock (DCLK) for displaying the period of the valid data, and the like.

These data and various signals are transformed into appropriate forms by the timing controller 142 and supplied to the gate and the data drivers 162 and 172. The gate driver 162 enables the gate signal to enable the horizontal pixel array every frame. Is generated and scanned and transmitted to the gate line 112, and the data driver 172 generates a data signal that charges the horizontal pixel column opened by the gate signal and transmits the data signal to each data line 114.

As a result, when the pixel P selected for each horizontal pixel column is opened by the gate signal of the gate line 112, the data signal of the data line 114 is charged to display an image. For this purpose, the timing controller 142 may display an image. SSC (Source Sampling Clock) to align the data and latch the data of each horizontal pixel column, SOE which is a data latch signal to indicate the time of transfer of data latched by the SSC, and SSP to indicate the starting point of data among one horizontal signal ( Source start pulse) and an image control signal containing a POL or the like which alternately represents a positive (+) and a negative (-) polarity inversion peak for determining the polarity of the data signal as a polarity inversion signal synchronized with the SOE. 172), the gate shift clock (GSC) specifying the time that the thin film transistor (T) is turned on, the gate output enable (GOE) controlling the output of the gate driver 162, the start line of the screen among one vertical signal Let me know Transmits a frame control signal, such as a nested (Gate Start Pulse) GSP to the gate driver 162.

Meanwhile, the liquid crystal display according to the present invention uses amorphous silicon as the semiconductor layer of the thin film transistor (T) and at the same time, a part or all of the gate driver 162 is mounted in the liquid crystal panel 110 as shown in the drawing. In order to overcome the limitation caused by the low field mobility of the amorphous silicon, an overlap driving method of overlapping a portion of the gate signal scanned and transmitted to each gate line 112 may be taken.

In addition, the liquid crystal display according to the present invention, in order to reduce the possibility of signal timing mismatch due to signal delay or device characteristics and design reasons, and to control the polarity inversion timing of the data signal uniformly for the entire liquid crystal panel 110. Although the polarity inversion of the data signal for each frame can be started from the third horizontal pixel column, the polarities of the data signals for the first and second horizontal pixel columns are different from each other. It is resolving the luminance deterioration that may occur.

To this end, the timing controller 142 of the liquid crystal display according to the present invention is characterized by modulating and outputting a required signal including a POL in a predetermined form at a predetermined point of time, and more specifically, SOE in the blanking section before or after the frame or between the frames. Odd number of data latches of POL and odd number of polarity inverted peaks of POL are generated. As a result, POL alternates between positive and negative polarity inverted peaks according to each horizontal pixel sequence in the frame, including odd number in the blanking interval. Represented by

More specifically, Figure 5 is attached to the timing of the DE, SOE, POL for any n frames and subsequent n + 1 frame in the image implementation using the GIP liquid crystal display according to the present invention and the liquid crystal panel by As a conceptual diagram showing the polarity inversion state, for convenience, it is assumed that the horizontal pixel number of the liquid crystal display according to the present invention is XGA (1024 x 768) resolution having 1024 horizontal pixels, and according to the blanking interval, n frames and subsequent n + 1 frames are assumed. In particular, in the blanking section, odd-numbered data latches by SOE and odd-numbered polarity inverted peaks of POLs synchronized therewith can be found.

As a result, the data signal supplied to the 1024th horizontal pixel column as the end point of the n-frame display image shows negative polarity due to the negative polarity inversion peak of the POL. The polarity inversion peak appears, but the polarity inversion peak of the POL occurs odd number of times in the blanking section before the n + 1 frame starts, so that the data signal supplied to the first horizontal pixel column of the n + 1 frame is negative. As a result, the first horizontal pixel column of the n + 1 frame is charged with a negative polarity data signal.

In addition, odd polarity peaks of the POL appearing during the blanking period and odd number of data latches are formed by SOE. Thus, the polarity inversion peak of the POL is positive in the second horizontal pixel column of the n + 1 frame. The polarity is converted to the polarity, and the positive polarity data signal is charged. After that, the normal polarity inversion by the POL appears from the third horizontal pixel column, and the negative and positive polarity data signals are applied to each horizontal pixel column. It is reversed.

As a result, the n + 1 frame can be inverted so that the polarities of the data signals are reversed from each other from the first horizontal pixel sequence for all horizontal pixel sequences. do.

At this time, although the data latch due to SOE and its inversion peak of the POL appear only once in the blanking section, the data latch due to SOE and the polarity inversion peak of the POL may be performed an odd number of times exceeding one time.

In addition, although only a blanking section between n frames and n + 1 frames is shown in the drawing, assuming that the n frame is the first frame, a blanking section exists even before n frames, and in this case, blanking between each frame including the first frame. It will be apparent to those skilled in the art that if the data latch due to SOE and the polarity inversion peak of the POL appear odd-numbered in the interval, the polarity of the data signal is inverted by the horizontal pixel sequence for every frame.

As a result, the charging time of the data signal for each horizontal pixel column can be adjusted to be equal, thereby eliminating partial luminance unevenness.

As described above, the GIP liquid crystal display according to the present invention can solve the partial luminance unevenness, that is, the luminance unevenness due to the same polarity of the data signal for the first and second horizontal pixel columns of each frame. In addition, there is an advantage that uniform luminance can be implemented for all images.

Claims (9)

A liquid crystal panel which displays an image in a frame unit including a blanking section and defines horizontal and vertical pixel columns in a matrix form in a vertical and horizontal arrangement of gate lines and data lines; Polarity inversion indicating an alternating frame control signal, data, and an odd number of polarity inversion peaks in the blanking section and a positive and negative polarity inversion peaks corresponding to each horizontal pixel string in the frame. A timing controller for generating an image control signal including a signal; A gate driver which generates a gate signal for sequentially enabling the horizontal pixel array based on the frame control signal and scans and supplies the gate line to the gate line; A data driver for generating a data signal indicating a polarity state according to the polarity inversion signal and charging each of the enabled horizontal pixel columns based on the data and image control signal and supplying the data signal to the data line; Liquid crystal display comprising a. The method of claim 1, And the horizontal pixel column is divided into a first horizontal pixel column in which the data signal is initially charged and a second or less horizontal pixel column in which the data signal is subsequently charged. 3. The method of claim 2, And all horizontal pixel columns including the first horizontal pixel column are charged with opposite polarities to each adjacent horizontal pixel column. The method of claim 3, The image control signal, And an odd number of data latch signals in the blanking section for synchronizing an odd number of polarity inversion peaks in the blanking section. The method of claim 1, The liquid crystal panel is a thin film transistor having a semiconductor layer made of amorphous silicon and provided at the intersection of the gate line and the data line. Liquid crystal display further comprising. 6. The method of claim 5, And the gate driver is mounted in the liquid crystal panel. The method according to claim 6, And a plurality of gate signals that are scanned and transferred to the gate lines. An image realization method of a liquid crystal display device comprising a liquid crystal panel in which horizontal and vertical pixel columns are defined in a matrix so as to display an image in units of frames subsequent to a blanking period. Generating a polarity inversion signal alternately representing positive and negative polarity inversion peaks for polarity inversion in the frame including an odd number of polarity inversion peaks in the blanking period; Each horizontal pixel sequence is sequentially enabled in the frame, and each enabled horizontal pixel sequence is charged according to the polarity inversion state of the polarity inversion signal Image realization method of the liquid crystal display comprising a. 9. The method of claim 8, The horizontal pixel column is divided into a first horizontal pixel column in which a data signal is first charged and a second or less horizontal pixel column in a subsequent charging, And all horizontal pixel columns including the first horizontal pixel column are charged with opposite polarities to each adjacent horizontal pixel column.

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