KR101238007B1 - Liquid crystal display and driving method thereof - Google Patents

Abstract

The present invention is to reduce power consumption by reducing the alternating frequency of the common voltage in the implementation of the line inversion, and at the same time to obtain a precharging effect, by separating the even frame portion and the odd frame portion of the liquid crystal panel, the liquid crystal panel to separate the scan signal Provided is a liquid crystal display including a gate driver to supply, a source driver to control the polarity of even and odd frame parts of the liquid crystal panel to be opposite to each other, a timing controller to control the driving timing of the gate driver and the source driver, and a driving method thereof. do.

Liquid Crystal Display, Line Inversion, Scan Signal

Description

Liquid crystal display and driving method thereof

1 is a view for explaining the line inversion in the conventional liquid crystal panel.

FIG. 2 is a waveform diagram of a common voltage and a data voltage applied to FIG. 1.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4A and 4B are diagrams for describing outputs of a gate line and a data line in the liquid crystal panel of FIG. 3.

5 is a waveform diagram illustrating a common voltage and a data voltage in the liquid crystal panel of FIG. 3.

6 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS (S)

100: liquid crystal panel 110: gate driver

120: source driver 130: timing controller

GL: gate line DL: data line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display device using an inversion drive and a driving method thereof.

The liquid crystal display device forms a liquid crystal layer having anisotropic dielectric constant between upper and lower substrates, which are transparent insulating substrates, and then adjusts the intensity of an electric field formed in the liquid crystal layer to change the molecular arrangement of the liquid crystal material, thereby The display device expresses a desired image by adjusting the amount of light transmitted through the upper substrate. As a liquid crystal display device, a thin film transistor liquid crystal display device (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

In general, the liquid crystal display device includes a liquid crystal panel in which an image is displayed and a driving unit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines forming a row and the data lines forming a column and intersecting the gate lines are arranged in a matrix type, and regions are divided by gate lines and data lines crossing each other. The plurality of pixels constitute one frame. When scan signals are sequentially applied to the gate lines, one frame is displayed on the liquid crystal panel while data voltages are applied to the data lines in response to the scan signals.

Each pixel includes a thin film transistor, a pixel electrode, and the like, and the thin film transistor applies a data voltage supplied from the data line to the pixel electrode in response to a scan signal supplied from the gate line.

In order to drive such a liquid crystal panel, an inversion driving method of inverting the polarity by a predetermined unit is generally used to prevent deterioration of the internal liquid crystal and to improve display quality of an image. Inversion driving methods are classified into a frame inversion method, a line inversion method, and a dot inversion method according to a unit in which polarities are inverted.

The driver includes a gate driver and a source driver for driving the gate line and the data line of the liquid crystal panel, respectively, and a timing controller part for controlling the driving timing thereof.

FIG. 1 is a diagram illustrating a line inversion in a conventional liquid crystal panel, and FIG. 2 is a waveform diagram of a common voltage and a data voltage applied to FIG. 1.

N gate lines GL1, GL2, GL3, ..., GLn are disposed on the liquid crystal panel, and when driving the liquid crystal panel, the gate lines GL1, GL2, GL3, ..., GLn are unidirectional DS. Scan signal is applied to each of the gate lines GL1, GL2, GL3, ..., GLn.

The scan signal is a signal obtained by sequentially shifting the gate shift pulse GSP for every one horizontal period 1H, and the one horizontal period 1H corresponds to one frame period for driving one frame for the gate lines GL1, GL2, GL3, ..., it is fixed to the value distributed according to the number of GLn).

Then, a data voltage of one line is applied to each gate line GL1, GL2, GL3, ..., GLn selected by the scan signal.

The conventional one-line inversion driving method is a method of sequentially applying pixel data stored in the graphic RAM in the driving unit to the liquid crystal panel while changing polarity for each line, as shown in FIG. The common voltage Vcom and the data voltage Vdata corresponding to the pixel data are alternated.

When the line inversion method is applied, the power supply of the source driver controlling the inversion can be lowered to about 5V, so that power consumption can be reduced compared to the dot inversion method. have.

However, each time the gate lines GL1, GL2, GL3, ..., GLn are sequentially selected one by one through the scanning operation, the common electrode needs to be alternated once, thereby increasing the parasitic capacitance of the common electrode to which the common voltage is applied. Compared to the case where the common voltage is alternated in units of frames, the number of alternating times of the common voltage increases, thereby increasing power consumption.

Accordingly, an object of the present invention is to provide a liquid crystal display device that can reduce power consumption and at the same time obtain a precharging effect in implementing line inversion.

Another object of the present invention is to provide a method of driving a liquid crystal display device capable of efficiently driving the aforementioned liquid crystal display device.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not intended to limit the invention to the precise forms disclosed. Other objects, which will be apparent to those skilled in the art, It will be possible.

In accordance with an aspect of the present invention, a plurality of pixels separated by gate lines and data lines intersecting each other form one frame, and one frame includes an even frame portion and an odd frame portion. A liquid crystal panel, a gate driver configured to separate gate lines of the even frame portion and gate lines of the odd frame portion to supply a first scan signal and a second scan signal, and data lines of the even frame portion in response to the first scan signal A source driver for supplying a data voltage to the data frame, supplying a data voltage to data lines of the odd frame part in response to the second scan signal, and controlling the polarity of the even frame part and the odd frame part to be opposite to each other; To control the driving timing of the driver and the source driver. It comprises parts of the timing controller.

A method of driving a liquid crystal display according to the present invention includes a) generating a first gate control signal and a first data control signal, and b) a first scan signal sequentially in an even frame portion in response to the first gate control signal. C) generating and outputting a data voltage of the even frame part in response to the first data control signal, and controlling the even frame part to have a constant polarity; d) a second gate control signal and a second; Generating a data control signal, e) sequentially supplying a second scan signal to the gate lines of the odd frame part in response to the second gate control signal, and f) the odd number in response to the second data control signal Generates and outputs a data voltage of a frame portion, and controls the odd frame portion to have a polarity opposite to that of the even frame portion It includes.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, a liquid crystal display according to an exemplary embodiment and a driving method thereof will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a gate driver for driving the liquid crystal panel 100 and the gate lines GL1, GL2, GL3,..., GLn of the liquid crystal panel 100. The driving timing of the source driver 120, the gate driver 110, and the source driver 120 for driving the data lines DL1, DL2, DL3,..., DLm of the liquid crystal panel 100 is controlled. And a timing controller 130 for the purpose of doing so.

For convenience, hereinafter, the gate lines GL1, GL2, GL3, GL3, GL4,..., GLn are referred to as the gate line GL, and the data lines DL1, DL2, DL3,. DLm) is referred to as data line DL, respectively.

The liquid crystal panel 100 includes a plurality of pixels arranged in a matrix form, and the gate lines GL and the data lines DL are alternately disposed in the horizontal and vertical directions to define each pixel. These pixels gather to form a frame, and one frame of the liquid crystal panel 100 includes gate lines GL2, GL4, GL6,..., GLn constituting the even frame portion and gate lines GL1 constituting the odd frame portion. , GL3, GL5,…, GLn-1).

Each pixel is connected to the first scan signal supplied through the gate lines GL2, GL4, GL6, ..., GLn of the even frame part and the gate lines GL1, GL3, GL5, ..., GLn-1 of the odd frame part. The image is scanned by the supplied second scan signal and displayed according to the data voltage supplied through the data lines DL during the scan operation.

The gate driver 110 supplies a scan signal sequentially shifted to the gate lines GL of the liquid crystal panel 100 in response to the gate control signal GCS supplied from the timing controller 130.

Here, the gate driver 110 separates the gate lines GL2, GL4, GL6,..., GLn from the even frame part and the gate lines GL1, GL3, GL5,..., GLn-1 from the odd frame part. The scan signal and the second scan signal are supplied. For example, the first scan signal is sequentially supplied to the gate lines GL2, GL4, GL6,..., GLn of the even frame portion of the liquid crystal panel 100 during one frame period, and then the liquid crystal panel ( The second scan signal is sequentially supplied again to the gate lines GL1, GL3, GL5,..., GLn-1 of the odd frame part of 100.

The source driver 120 converts the red, green, and blue pixel data transmitted from the timing controller 130 into a data voltage using gamma voltages, and applies the data control signal DCS supplied from the timing controller 130. In response, the data voltage is supplied to the data lines DL.

The source driver 120 supplies data voltages for each line to the gate lines GL2, GL4, GL6,..., GLn of the even frame part selected by the first scan signal, and then supplies the data voltage by the second scan signal. The data voltages for each line are supplied to the selected gate lines GL1, GL3, GL5, ..., GLn-1, and the polarity of the even frame portion and the odd frame portion is reversed.

Here, the data control signal DCS includes a polarity control signal POL for controlling the polarity of the data voltage to be positive (+) (−), and according to the polarity control signal POL, polarities of even and odd frame parts are determined. These are driven opposite to each other.

The timing controller 130 receives red, green, and blue pixel data from an external system, performs a rearrangement process, and then transfers the data to the source driver 120.

The gate control signal GCS and the data control signal DCS are generated according to the control of various clock signals such as the vertical and horizontal synchronization signals H and V, the main clock CLK, and the data enable signal DE. The driving timing of the gate driver 110 and the source driver 120 is controlled.

4A and 4B are diagrams for describing outputs of gate lines and data lines in the liquid crystal panel of FIG. 3, and FIG. 5 is a waveform diagram illustrating common voltages and data voltages in the liquid crystal panel of FIG. 3.

The pixel data corresponding to one frame is divided into an even frame to be applied to the even frame part and an odd frame to be applied to the odd frame part.

As shown in FIG. 4A, the gate driver 110 first shifts sequentially along the one direction DS in the even frame portion of the liquid crystal panel 100 during one frame period for supplying an even frame. A signal is applied to drive the gate lines GL2, GL4, GL6,..., GLn of the even frame part, and the source driver 120 receives the data voltage of the even frame by one line for each data line DL. To supply.

The gate lines GL2, GL4, GL6, ..., GLn of the even frame are driven in the order of the second, fourth, and sixth gate lines GL2, GL4, GL6, and the like. Data for each line corresponding to GL4, GL6, ..., GLn is supplied to the data lines DL.

As shown in FIG. 4B, the second scan signal sequentially shifted along one direction DS is applied to the odd frame portion of the liquid crystal panel 100 during the one frame period for supplying the odd frame, and thus the odd number may be odd. The gate lines GL1, GL3, GL5,..., GLn-1 of the frame portion are driven so that the source driver 120 supplies the data voltage of an odd frame to the data lines DL by one line. do.

In an odd frame, the gate lines GL1, GL3, GL5, ..., GLn-1 are driven in the order of the first, third, fifth gate lines GL1, GL3, GL5, and the like, and each gate line. Data for each line corresponding to (GL1, GL3, GL5, ..., GLn-1) is supplied to the data lines DL.

Here, the polarity of the even frame and the odd frame is controlled to be opposite to each other.

For example, as illustrated in FIG. 5, the polarity of the common voltage Vcom may be inverted every one frame period, thereby controlling the polarity of the even frame and the odd frame to be opposite to each other.

That is, the source driver 120 alternates the common voltage Vcom every one frame period, divides the data voltage of one frame into even frames and odd frames, and changes polarities for each frame. It is applied to a liquid crystal panel.

As described above, when one frame is divided into even frames and odd frames, and the polarities of the even frames and the odd frames are inverted mutually, the polarities are in the horizontal line unit. Because of the inversion, one-line inversion can be efficiently implemented.

In addition, as shown in FIG. 5, when the polarities of the common voltage Vcom and the data voltage Vdata are controlled, the common voltage Vcom is alternated every frame period, so that the common voltage Vcom is alternated for each line. Compared to the case, the power consumption can be significantly reduced.

Further, the gate driver 110 sequentially scans the gate lines GL2, GL4, GL6,..., GLn of the even-frame portion, and the reference gate line (eg, GL2) and the next gate line (eg, The gate lines GL2, GL4, GL6, ..., GLn are driven to overlap the first scan signal of GL4.

Here, the first scan signal is generated by using the gate shift clock GSC and the gate shift pulse GSP supplied as the gate control signal GCS, and the gate shift pulse GSP according to the gate shift clock GSC. ) Is a signal shifted sequentially.

The pulse width of the gate shift pulse GSP is twice the reference horizontal period 1H divided by one frame period by the number of all the gate lines GL1, GL2, GL3,..., GLn configured in the liquid crystal panel 100 ( 2H) or higher.

Accordingly, since the first scan signal of the reference gate line (eg, GL2) and the next gate line (eg, GL4) is supplied to overlap, the pixels of the next gate line are scanned while the pixels of the reference gate line are scanned. Will perform precharging.

In the case of the second scan signal for driving the odd frame portion, the second scan signal is formed so as to overlap with the first scan signal.

As such, by varying the pulse width of the gate shift pulse GSP to increase the gate on time, the precharging function can be realized, thereby improving the response characteristics of the liquid crystal, thereby minimizing flicker. have.

6 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention, and is described with reference to the liquid crystal display of FIG. 3.

First, in step S100, the timing controller 130 generates a first gate control signal and a first data control signal.

Next, in step S110, the gate driver 110 sequentially orders the first gate lines GL2, GL4, GL6,..., GLn forming the even frame portion of the liquid crystal panel 100 in response to the first gate control signal. Supply the scan signal.

The first scan signal sequentially scans the gate lines GL2, GL4, GL6,... GLn of the even frame portion, and at the reference gate line (eg GL2) and the next gate line (eg GL4). Signals that overlap each other.

That is, while the gate driver 110 scans the gate lines GL2, GL4, GL6,..., GLn in the even frame portion in one direction DS, the reference gate line (eg, GL2) and the next gate line (eg, For example, the first scan signal is generated to overlap each other in GL4).

As a result, the pixels of the next gate line (eg GL4) perform precharging while the pixels of the reference gate line (eg GL2) are scanned.

Next, in step S120, the source driver 120 generates and outputs a data voltage corresponding to the pixel data of the even frame part in response to the first data control signal, and controls the even frame part to have a constant polarity.

Next, in step S130, the timing controller 130 generates the second gate control signal and the second data control signal.

Next, in step S140, the gate driver 110 sequentially processes the gate lines GL1, GL3, GL5,..., GLn-1 that form the odd frame part of the liquid crystal panel 100 in response to the second gate control signal. Supply a second scan signal.

The second scan signal sequentially scans the gate lines GL1, GL3, GL5, ..., GLn-1 of the odd frame portion, and the reference gate line (eg GL1) and the next gate line (eg GL3). ) Are signals that overlap each other.

Next, in step S150, the source driver 120 generates and outputs a data voltage corresponding to the pixel data of the odd frame part in response to the second data control signal, and controls the odd frame part to have a polarity opposite to that of the even frame part. do.

The timing controller 130 includes the polarity control signal POL in the first data control signal and the second data control signal to supply the source driver 120, and the source driver 120 is provided from the timing controller 130. The polarity control signal POL of controls the polarity of the even frame portion and the odd frame portion opposite to each other.

In steps S120 and S150, the source driver 120 may control the polarity of the even frame portion and the odd frame portion of the liquid crystal panel 100 to be opposite to each other by inverting the polarity of the common voltage Vcom every one frame period. .

As described above, one frame of the liquid crystal panel 100 is driven by dividing the frame into an even frame portion having a certain polarity and an odd frame portion having a polarity opposite to that of the even frame portion, thereby implementing a one-line inversion and a common voltage Vcom. The power consumption can be reduced by reducing the number of alternations.

In addition, the precharging function may be implemented by increasing the pulse width of the gate shift pulse GSP to overlap the scan signal of the reference gate line and the next data line.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood.

Therefore, it should be understood that the above-described embodiments are provided so that those skilled in the art can fully understand the scope of the present invention. Therefore, it should be understood that the embodiments are to be considered in all respects as illustrative and not restrictive, The invention is only defined by the scope of the claims.

According to the liquid crystal display and the driving method thereof according to the present invention as described above, the power consumption can be reduced by reducing the number of alternating times of the common voltage in implementing the line inversion, and at the same time, the precharging effect can be obtained. .

Claims (9)

A liquid crystal panel in which a plurality of pixels separated by gate lines and data lines crossing each other form one frame, and one frame includes an even frame portion and an odd frame portion; A gate driver configured to separate the gate lines of the even frame part and the gate lines of the odd frame part to supply a first scan signal and a second scan signal; Supplying a data voltage to data lines of the even frame part in response to the first scan signal, and supplying a data voltage to data lines of the odd frame part in response to the second scan signal, wherein the even frame part and the A source driver for controlling the odd frame parts to be opposite to each other; And And a timing controller to control driving timing of the gate driver and the source driver. The method of claim 1, Wherein the gate driver comprises: After sequentially scanning the gate lines of the even-frame portion and supplying the first scan signal of the reference gate line and the next gate line to overlap, And sequentially scanning the gate lines of the odd frame part so that the second scan signals of the reference gate line and the next gate line overlap each other. The method of claim 1, Wherein the gate driver comprises: And driving the gate lines of the even frame portion during one frame period for driving a reference frame, and then driving the gate lines of the odd frame portion for one frame period for driving a next frame. The method of claim 1, The first and second scan signal, A signal for sequentially shifting the gate shift pulse GSP according to the gate shift clock GSC. And a pulse width of the gate shift pulse GSP is equal to or greater than two times (2H) the reference horizontal period (1H) divided by one frame period by the number of the gate lines of the liquid crystal panel. The method of claim 1, And inverting the polarity of the common voltage every one frame period so that the polarity of the even frame portion and the odd frame portion is opposite to each other. a) generating a first gate control signal and a first data control signal; b) sequentially supplying a first scan signal to an even frame part in response to the first gate control signal; c) generating and outputting a data voltage of the even frame part in response to the first data control signal, and controlling the even frame part to have a constant polarity; d) generating a second gate control signal and a second data control signal; e) sequentially supplying a second scan signal to gate lines of an odd frame part in response to the second gate control signal; And f) generating and outputting a data voltage of the odd frame part in response to the second data control signal, and controlling the odd frame part to have a polarity opposite to that of the even frame part. The method of claim 6, In step c) and f), And controlling the polarity of the even frame portion and the odd frame portion to be opposite to each other by inverting the polarity of the common voltage every one frame period. The method of claim 6, In step b), And the first scan signal sequentially scans the gate lines of the even frame part and overlaps each other at a reference gate line and a next gate line. The method of claim 6, In step e), And the second scan signal sequentially scans the gate lines of the odd frame part and overlaps each other at a reference gate line and a next gate line.

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