KR101267079B1 - Liquid crystal display and driving method thereof - Google Patents

Abstract

The present invention is to improve pixel charging characteristics and to reduce power consumption in a data line sharing structure. A plurality of pixels are arranged in a horizontal direction to form a pixel line, and a pair of pixels connected to the pixels of the pixel line are alternately connected. A gate line is arranged above and below the pixel line, the liquid crystal panel in which two pixels share one data line, a gate driver and a source driver for supplying scan signals and data voltages to the liquid crystal, and a timing controller for controlling driving timing. If an Mth (M is a natural number) data line disposed between an adjacent pair of pixels is connected to one of the pair of pixels, the other pixel is connected to the M-1 or M + 1th data line. Provided are a liquid crystal display device and a driving method thereof, the pixels being connected and the direction of pixels connected to the Mth data line is changed for each pixel line. .

Liquid Crystal Display, Data Line Sharing, Column Inversion, Dot Inversion

Description

[0001] The present invention relates to a liquid crystal display and a driving method thereof,

1 is a schematic configuration diagram of a liquid crystal display according to the related art.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 3 is a detailed block diagram illustrating a part of the liquid crystal panel shown in FIG. 2.

FIG. 4 is a pixel charge distribution diagram when the liquid crystal panel of FIG. 3 is driven in a column inversion scheme.

FIG. 5 is a diagram illustrating a change in data voltage when the liquid crystal panel of FIG. 3 is driven in a column inversion scheme.

6 is a flowchart illustrating a method of driving a liquid crystal display according to an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS (S)

100: liquid crystal panel 110: gate driver

120: source driver 130: timing controller

GL: gate line DL: data line

PL: pixel line TFT: thin film transistor

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device having a data line sharing structure and a driving method thereof.

The liquid crystal display device forms a liquid crystal layer having anisotropic dielectric constant between upper and lower substrates, which are transparent insulating substrates, and then adjusts the intensity of an electric field formed in the liquid crystal layer to change the molecular arrangement of the liquid crystal material, thereby The display device expresses a desired image by adjusting the amount of light transmitted through the upper substrate. As a liquid crystal display device, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

Such a liquid crystal display includes a liquid crystal panel in which an image is displayed. When driving the liquid crystal panel, inversion driving is performed in which the polarity is inverted in a predetermined unit to prevent deterioration of the internal liquid crystal and to improve display quality of the image. It is common for the method to be used. The inversion driving method is classified into a frame inversion method, a column inversion method, and a dot inversion method according to the unit of polarity inversion.

FIG. 1 is a schematic configuration diagram of a liquid crystal display according to the related art, and illustrates red, green, and blue pixels R, G, and B constituting a liquid crystal display having a data line sharing structure.

Referring to FIG. 1, two gate lines GL1, GL2, GL3, GL4,... Are disposed above and below pixels forming one pixel line PL1, PL2,... DL1, DL2, DL3, ...) are shared by two adjacent pixels.

The liquid crystal display uses two gate lines GL1, GL2, GL3, GL4,... To independently drive even and odd pixels of each pixel line PL1, PL2,...

For example, even / odd pixels of the first pixel line PL1 are connected to the first and second gate lines GL1 and GL2, and the scan signal is applied to the first gate line GL1. Even pixels are driven, and then odd pixels of the same pixel line PL1 are driven by a scan signal applied to the second gate line GL2.

As described above, the conventional liquid crystal display device uses two gate lines GL1, GL2, GL3, GL4, ... to drive odd pixels and even pixels of each pixel line PL1, PL2, ....

However, the liquid crystal display having such a structure requires driving one pixel line PL1, PL2, ... by using two gate lines GL1, GL2, GL3, GL4, ..., thus doubling the amount of time during one frame period. The gate lines GL1, GL2, GL3, GL4, ... must all be driven. To this end, since one pixel charge time is reduced from one horizontal period 1H to one half horizontal period H / 2, there is a problem that it is difficult to secure sufficient pixel charging time and the image quality is degraded.

In addition, when the polarity of the data voltage applied to the data lines DL1, DL2, DL3, ... is inverted in units of pixels by applying the dot inversion method to improve the deterioration of image quality, the data lines DL1, DL2, DL3, There is a problem that the power consumption of the source driver for driving…) is excessively large.

Accordingly, an object of the present invention is to provide a liquid crystal display device having a data line sharing structure capable of improving pixel charging characteristics and reducing power consumption.

Another object of the present invention is to provide a method of driving a liquid crystal display device capable of efficiently driving the aforementioned liquid crystal display device.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not intended to limit the invention to the precise forms disclosed. Other objects, which will be apparent to those skilled in the art, It will be possible.

In the liquid crystal display according to the present invention for achieving the above technical problem, a plurality of pixels are arranged in a horizontal direction to form a pixel line, and a pair of gate lines connected to the pixels of the pixel line are connected up and down of the pixel line. A liquid crystal panel in which two pixels share one data line, a gate driver for supplying a scan signal to gate lines of the liquid crystal panel, and a data voltage for supplying data voltages to data lines of the liquid crystal panel A timing controller for controlling driving timing of the source driver, the gate driver, and the source driver, wherein an M-th (M is a natural number) data line disposed between a pair of adjacent pixels includes one pixel of the pair of pixels; When connected to the other side pixel is connected to the M-1 or M + 1st data line, the pixel line Characterized in that the direction of the pixels coupled to the M th data line changes.

In addition, the driving method of the liquid crystal display according to the present invention comprises the steps of: a) generating a gate control signal and a data control signal for controlling the driving timing; b) sequentially supplying scan signals to gate lines in response to the gate control signal; c) generating a data voltage corresponding to the input pixel data, outputting the data voltage as data lines by inverting polarity in column units in response to the data control signal; d) charging the data voltage while inverting the polarity of the pixels in units of dots by a connection structure of the pixels forming the data lines and the pixel lines; e) displaying an image according to the scan signal and the data voltage, and in step d), the Mth (M is a natural number) data line disposed between a pair of adjacent pixels When one of the pixels is driven, the other pixel is driven by the M-1 or M + 1 th data line.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, a liquid crystal display according to an exemplary embodiment and a driving method thereof will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a liquid crystal display according to an exemplary embodiment may include a gate driver for driving the liquid crystal panel 100 and the gate lines GL1, GL2, GL3, GL4,... Of the liquid crystal panel 100. 110, for controlling driving timings of the source driver 120, the gate driver 110, and the source driver 120 for driving the data lines DL1, DL2, DL3,..., Of the liquid crystal panel 100. Timing controller 130, and the like.

For convenience, hereinafter, gate lines GL1, GL2, GL3, GL3, GL4,... Are used as gate lines GL, and data lines DL1, DL2, DL3,... As the line DL, the pixel lines PL1, PL, ... are described as the pixel line PL, respectively.

The liquid crystal panel 100 includes a plurality of pixels arranged in a matrix form, and the gate lines GL and the data lines DL are alternately disposed in the horizontal and vertical directions to define each pixel. Pixels arranged in a horizontal direction constitute one pixel line PL, and two gate lines GL are arranged above and below pixels constituting the pixel line PL.

Each pixel displays an image according to a scan signal supplied through the gate lines GL and a data voltage supplied through the data lines DL. A more detailed configuration of the liquid crystal panel 100 will be described in FIG. 3.

The gate driver 110 supplies a scan signal sequentially shifted to the gate lines GL of the liquid crystal panel 100 in response to the gate control signal GCS supplied from the timing controller 130.

The source driver 120 converts the red, green, and blue pixel data transmitted from the timing controller 130 into a data voltage using gamma voltages, and applies the data control signal DCS supplied from the timing controller 130. In response, the data voltage is supplied to the data lines DL.

At this time, the data control signal DCS includes a polarity control signal POL for controlling the polarity of the data voltage to be positive (+), and is output through the data lines DL according to the polarity control signal POL. The polarity of the data voltage is inverted for each unit such as a dot, a column, or a frame.

The timing controller 130 receives red, green, and blue pixel data from an external system, performs a rearrangement process, and then transfers the data to the source driver 120. The gate control signal GCS and the data control signal DCS are generated according to the control of various clock signals such as the vertical and horizontal synchronization signals H and V, the main clock CLK, and the data enable signal DE. The driving timing of the gate driver 110 and the source driver 120 is controlled.

FIG. 3 is a detailed block diagram illustrating a part of the liquid crystal panel shown in FIG. 2.

Referring to FIG. 3, in the liquid crystal panel 100, the gate lines GL in the horizontal direction and the data lines DL in the vertical direction are alternately arranged to distinguish regions of the pixels, and pixels arranged in the horizontal direction are arranged. The pixel line PL is formed. The pixels include red, green, and blue pixels R, G, and B.

Two gate lines GL are arranged above and below the pixels constituting the pixel line PL, and the pair of gate lines GL arranged above and below the pixel line PL may correspond to the pixel line (PL). The pixels constituting PL) are alternately connected.

In addition, the two pixels share one data line DL to share a data voltage transmitted to the data line DL, and the thin film transistor TFT shares one data line DL. The data voltage is alternately applied to the two pixels.

Here, the pair of pixels sharing one data line DL are not pixels arranged adjacent to each other in the horizontal direction, and the pixels of the data line DL and the pixel line PL are constant, as shown in FIG. 3. It is connected by the structure which has a characteristic.

Hereinafter, the connection structure will be described based on the first pixel line PL1.

First, two pixels on the left and right share one data line DL1, DL2, DL3. Here, one of the two pixels disposed on both left and right sides and sharing one data line DL1, DL2, DL3 is not a pixel directly adjacent to the data line DL1, DL2, DL3, but next to the pixel. It is the pixel located. For example, pixels P1 and P3 share a first data line DL1, pixels P4 and P6 share a second data line DL2, and pixels PL5 and PL7 share a third data line DL3, respectively.

Then, for example, when a scan signal is sequentially applied to the first gate line GL1 and the second gate line GL2, the red pixel P1 connected to the left side of the first data line DL1 and the blue pixel P3 connected to the right side are connected. It is charged sequentially.

That is, the red pixel P1 adjacent to the side of the first data line DL0 is charged instead of the green pixel P2 adjacent to the left side of the first data line DL1. In this manner, one of the two pixels located at the left and right of one data line DL1, DL2, DL3 is cross-connected with a pixel located at the side of another adjacent data line DL0, DL1, DL2, DL3. have.

Generalizing this, when the M-th (M is a natural number) data line DL disposed between an adjacent pair of pixels is connected to one of the pair of pixels, the other pixel is M-1 or M + 1. The direction of the pixel connected to the first data line DL and connected to the Mth data line DL is changed for each pixel line PL.

That is, when the M-th data line DL is connected to the left pixel in the K-th (K is a natural number) pixel line PL, the M-th data line DL is connected to the right pixel in the K + 1th pixel line PL.

In the K-th (K is a natural number) pixel line PL, when the M-th data line DL is connected with the right pixel and simultaneously with the pixel located to the left of the left pixel, the K + 1th pixel line PL The Mth data line DL is connected to the left pixel and simultaneously connected to the pixel located to the right of the right pixel.

For example, in the first pixel line PL1, when the first data line DL1 is connected to the right pixel P3, the left pixel P2 adjacent to the other side of the first data line DL1 is connected to the first data line DL0. . In the second pixel line PL2, the first data line DL1 is connected to the left pixel, and the right pixel is connected to the second data line DL2.

Each pixel is connected to the gate line GL and the data line DL through a thin film transistor TFT having a gate electrode, a source and a drain electrode. The thin film transistor TFT is disposed at the intersection of the gate line GL and the data line DL to be electrically connected to each pixel. The gate electrode of the thin film transistor TFT is connected to the gate line GL, and the source electrode is To the pixel electrode (not shown) of the pixel, the drain electrode is connected to the data line DL, respectively.

When the scan signal is input to the gate line GL connected to the pixel, the thin film transistor is turned on to apply the data voltage from the data line DL to the pixel.

The driver integrated circuits constituting the gate driver 110 may be separated from the left and right sides of the liquid crystal panel 100 so that the gate lines GL may be disposed above the pixel line PL and the gate lines GL may be disposed below. To drive them individually. In this case, the gate driver 110 may be configured to be mounted on the liquid crystal panel 100 in a gate in panel (GIP) structure.

When the data voltages are output to the data lines DL, scan signals are sequentially applied to the gate lines GL in the order of the first, second, third, and fourth gate lines GL1, GL2, GL3, GL4, and the like. As the scan signal is applied, the thin film transistors TFTs connected to the respective gate lines GL are turned on, and predetermined pixel data is written in the predetermined pixel.

When the timing controller 130 controls the output of the source driver 120 to be inverted in polarity for each data line DL through the polarity control signal POL for controlling the polarities to be opposite to each other in a column unit, adjacent source drivers ( Polarities opposite to each other are output to the data lines DL of 120.

For example, as illustrated in FIG. 3, a signal of positive polarity is output to the first data line DL1, and a signal of negative polarity is output to the second data line DL2.

Then, a positive polarity signal is charged to the pixels P1 and P3 connected to the first data line DL1, and a negative polarity signal is charged to the pixels connected to the second data line DL2. In addition, according to the connection structure between the first data line DL1 and the second data line DL2, pixels receiving the positive polarity signal are continuously changed in the left / right directions for each pixel line PL. Likewise, the polarity is reversed in dots.

As such, in the liquid crystal panel 100 having the data line sharing structure, pixels arranged alternately on the left and right sides of the data line DL may be driven in a column inversion method, and dot inversion may be implemented through a connection structure of the pixels. .

Since the column inversion driving of the source driver 120 is shown as a dot inversion driving according to the connection structure of the pixels and the data line DL, which is the output of the source driver 120, compared with the conventional dot inversion method. While significantly reducing power consumption, the polarity is reversed at one pixel intervals in the horizontal and vertical directions, thereby improving pixel charging characteristics, thereby improving image quality deterioration.

FIG. 4 is a pixel charge distribution diagram when the liquid crystal panel of FIG. 3 is driven in a column inversion scheme.

5 is a diagram illustrating a change in data voltage when the liquid crystal panel of FIG. 3 is driven in a column inversion scheme, and illustrates a change in data voltage according to column inversion.

In the case of the pixel structure of the liquid crystal panel 100 as illustrated in FIG. 3, the dot inversion scheme as illustrated in FIG. 4 may be implemented by applying data voltages to the data lines DL in the column inversion scheme.

In FIG. 4, pixels driven by the first data line DL1 are indicated by thick lines. When a data voltage having a positive polarity is applied to the first data line DL1, as indicated, +1, +2, +3, +4, +5,... The pixels are charged in the order of.

In addition, when frame inversion is applied, the polarity of the second frame is reversed from that of the first frame, so that -1, -2, -3, -4, -5,... The pixels are charged in the order of.

Thus, since the dot inversion can be implemented through the connection structure of the data line DL and the pixels and the column inversion driving, the power consumption of the source driver 120 can be minimized, and at the same time, the pixel charging characteristics are improved. In this case, a reduction in charging time due to data line sharing can be overcome.

6 is a flowchart illustrating a method of driving a liquid crystal display according to an exemplary embodiment of the present invention, and illustrates a driving method centering on the liquid crystal display of FIGS. 2 and 3.

First, in step S100, the timing controller 130 generates a gate control signal GCS and a data control signal DCS for controlling the driving timing. Here, the data control signal DCS includes a polarity control signal POL for inverting the polarity of the signal output from the source driver 120 in a predetermined unit.

The polarity control signal POL is a signal for changing the polarity of the output signal of the source driver 120 in columns and also for changing the polarity in units of frames.

Next, in step S110, the gate driver 110 sequentially supplies scan signals to the gate lines GL in response to the gate control signal GCS.

Next, in step S120, the source driver 120 converts the red, green, and blue pixel data input through the timing controller 130 into data voltages using the gamma voltages. In this case, the source driver 120 is controlled to invert the polarity of the data voltage, which is an output signal in columns, by the data control signal DCS from the timing controller 130. The data voltage output from the source driver 120 is supplied to the data lines DL.

Next, in step S130, the data voltage supplied through the data lines DL is charged to each pixel while the polarities of the pixels are inverted in units of dots by the connection structure of the pixels constituting the liquid crystal panel 100.

The connection structure of the pixels is as described in FIG. 3.

More specifically, when the M-th (M is a natural number) data line disposed between an adjacent pair of pixels drives one of the left and right pixels, the other pixel is the M-1 or M + 1th data. Driven by lines.

In this case, when the M-th data line drives the left pixel in the K-th (K is a natural number) pixel line, the M-th data line drives the right pixel in the K + 1th pixel line.

In addition, the M-th data line drives the right pixel in the K-th (K is a natural number) pixel line and simultaneously drives the pixel located to the left of the left pixel, or drives the left pixel in the K + 1-th pixel line, and the right pixel. Can be configured to drive pixels located on the right side of the same time.

Next, in step S140, the alignment of the liquid crystal is adjusted according to the scan signal from the gate line GL and the data voltage from the data line DL, so that each pixel of the liquid crystal panel 100 displays an image.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand.

Therefore, it should be understood that the above-described embodiments are provided so that those skilled in the art can fully understand the scope of the present invention. Therefore, it should be understood that the embodiments are to be considered in all respects as illustrative and not restrictive, The invention is only defined by the scope of the claims.

The liquid crystal display and the driving method thereof according to the present invention made as described above have an effect of improving pixel charging characteristics and reducing power consumption in a data line sharing structure.

Claims (13)

A plurality of pixels are arranged in a horizontal direction to form a pixel line, and a pair of gate lines that are alternately connected to pixels of the pixel line are arranged above and below the pixel line, and two pixels share one data line. Liquid crystal panels; A gate driver for supplying scan signals to gate lines of the liquid crystal panel; A source driver for supplying a data voltage to data lines of the liquid crystal panel; And A timing controller configured to control driving timing of the gate driver and the source driver; When an Mth (M is a natural number) data line disposed between an adjacent pair of pixels is connected to one pixel of the pair of pixels, the other pixel is connected to an M-1 or M + 1th data line. And a direction of a pixel connected to the Mth data line is changed for each pixel line. The method of claim 1, The Mth data line is, And a left pixel in the K-th (K is a natural number) pixel line, and a right pixel in the K + 1th pixel line. The method of claim 1, And wherein the Mth data line is connected to the right pixel and simultaneously connected to the pixel located to the left of the left pixel in the Kth (K is a natural number) pixel line. The method of claim 3, And the M-th data line of the K + 1th pixel line is connected to the left pixel and simultaneously connected to the pixel located on the right side of the right pixel. The method of claim 1, And each of the plurality of pixels is turned on by the scan signal and connected to each of the data lines through a thin film transistor for applying a data voltage to each pixel. The method of claim 1, Wherein the gate driver comprises: A liquid crystal display device mounted on the liquid crystal panel in a gate in panel (GIP) structure. a) generating a gate control signal and a data control signal for controlling drive timing; b) sequentially supplying scan signals to gate lines in response to the gate control signal; c) generating a data voltage corresponding to the input pixel data, outputting the data voltage as data lines by inverting polarity in column units in response to the data control signal; d) charging the data voltage while inverting the polarity of the pixels in units of dots by a connection structure of the pixels forming the data lines and the pixel lines; e) displaying an image according to the scan signal and the data voltage, In step d), If an Mth (M is a natural number) data line disposed between an adjacent pair of pixels drives one pixel of the pair of pixels, the other pixel is driven by an M-1 or M + 1th data line. The driving method of the liquid crystal display device characterized by the above-mentioned. The method of claim 7, wherein The data control signal of step a), And a polarity control signal (POL) for changing polarity on a column basis. The method of claim 7, wherein The data control signal of step a), And a polarity control signal (POL) for changing the polarity in units of frames. delete The method of claim 7, wherein In step d), And the Mth data line drives a left pixel in a Kth pixel (K is a natural number) and a right pixel in a K + 1th pixel line. The method of claim 7, wherein In step d), And the Mth data line drives a right pixel in a Kth (K is a natural number) pixel line, and simultaneously drives a pixel located to the left of the left pixel. The method of claim 12, In step d), And the Mth data line drives a left pixel in a K + 1th pixel line, and simultaneously drives a pixel located on a right side of a right pixel.

Images