KR101529554B1 - Liquid crystal display device - Google Patents

Abstract

A liquid crystal panel including a plurality of gate lines, a plurality of data lines, and thin film transistors, and a liquid crystal panel including a plurality of gate lines, A timing controller for receiving a signal and generating a control signal, a gate driver for outputting a gate signal to a gate line of the liquid crystal panel in accordance with a control signal from the timing controller, And a data driver for outputting a data signal to the line, wherein the control signal includes a high signal corresponding to an interval before the valid data signal is input to the liquid crystal panel so as to mask the data signal before the valid data signal is input And a masking signal.

Liquid crystal display device, effective data signal, masking, SOE

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof that can generate an SOE masking signal (Source Output Enable Masking Signal) And a method of driving the liquid crystal display device.

2. Description of the Related Art In recent years, as portable information devices have become widespread, research and commercialization of a light-weight flat panel display (FPD) replacing a conventional CRT (cathode ray tube) .

Particularly, among such flat panel display devices, a liquid crystal display device is an apparatus which expresses an image using optical anisotropy of a liquid crystal, and has excellent resolution, color display and image quality and is actively applied to a monitor or a television of a notebook computer or a desktop computer .

In general, a liquid crystal display device includes a liquid crystal panel 2 in which a plurality of liquid crystal cells defined by a plurality of gate lines GL1-GLn and data lines DL1-DLm are arranged in a matrix form, A gate driver 4 for applying a gate scan signal to the gate lines GL1 to GLn of the liquid crystal panel 2 and a data driver 6 for applying a pixel signal to the data lines DL1 to DLm of the liquid crystal panel 2, The gate driver 4, and the data driver 6, as shown in FIG.

The liquid crystal panel 2 includes a plurality of liquid crystal cells defined by a plurality of gate lines GL1 to GLn and data lines DL1 to DLm and a plurality of gate lines GL1 to GLn, And a thin film transistor (TFT) connected to the data lines D11-DLm.

The TFT is turned on when a scan signal from the gate lines GL1 to GL, that is, a gate high voltage (Vgh), is supplied, and a pixel signal, which is applied from the data lines DL1 to DLm, Whereas when the gate-low voltage Vgl is supplied from the gate lines GL1 to GLn, the pixel signal is turned off to hold the pixel signal charged in the liquid crystal cell.

Usually, the liquid crystal cell has a pixel electrode connected to the TFT to receive a pixel signal, and a common electrode facing the pixel electrode, thereby forming a liquid crystal capacitance capacitor Clc. A storage capacitor Cst is formed in the liquid crystal cell in order to stably maintain the pixel signal until one pixel signal is charged and the next pixel signal is charged. In the liquid crystal display device constructed as described above, the alignment state of liquid crystal molecules having dielectric anisotropy changes according to a pixel signal inputted through the TFT, and the light transmittance is adjusted according to the alignment state of the liquid crystal molecules to realize a gray level.

The gate driver 4 is supplied with gate control signals GSP, GSC and GOE from the timing controller 10 and sequentially outputs the control signals GSP, GSC and GOE to the gate lines GL1 to GLn And outputs the gate high voltage Vgh to drive the respective TFTs connected to the gate lines GL1 to GLn.

The data driver 6 outputs the pixel signals to the data lines DL1 to DLm as the data control signals SSP, SSC, SOE and POL are input from the timing controller 10. [

The data driver 6 converts the digital signals of red (R), green (G), and blue (B) received from the timing controller 10 into analog pixel signals and supplies them to the data lines DL1 to Dlm Supply.

However, the following problems arise in driving the above-described liquid crystal display device.

Since the gate high voltage (Vgh) input to the TFT of the liquid crystal display device is generally a square wave having a set width, the TFT is turned on for a set period as the gate high voltage (Vgh) is applied. As described above, in the state that the TFT is turned on, the pixel driver 6 applies the pixel signal to the data lines DL1-Dlm through the TFT. However, the gate high voltage (Vgh) input to the TFT at the time of initial driving of the liquid crystal display device is not a usual square wave but a waveform having a tail at a constant interval. Therefore, when the liquid crystal display device is initially driven, the TFT is not turned on for a set time but turned on even at an undesired time. Accordingly, when the liquid crystal display device is initially driven, that is, when the screen of the display device is turned on, pixel signals are applied to the liquid crystal cell, so that an image is implemented on the screen.

When the black signal or the white signal is applied to the liquid crystal cell through the TFT during the initial driving of the liquid crystal display device as described above, no problem occurs in the image quality. However, when the image signal of the gray-scale voltage is applied, The image quality degradation phenomenon such as the occurrence of the stripes momentarily occurs.

An object of the present invention is to provide a liquid crystal display device capable of generating an SOE masking signal and preventing stripe or the like from being generated on a screen due to application of a gray-scale voltage when the liquid crystal display device is initially driven, and a driving method thereof.

According to an aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel including a plurality of gate lines, a data line, and a thin film transistor, A gate driver for outputting a gate signal to a gate line of the liquid crystal panel in accordance with a control signal from the timing controller; a data driver for outputting a data signal to a data line of the liquid crystal panel in accordance with a control signal of the timing controller; Wherein the control signal includes a high signal corresponding to an interval before the valid data signal is inputted to the liquid crystal panel and includes a masking signal for masking the data signal before the valid data signal is inputted .

According to another aspect of the present invention, there is provided a method for driving a liquid crystal display device, comprising: generating a control signal by receiving data and a vertical / horizontal synchronizing signal from outside; and sequentially generating a gate high voltage A step of receiving the SOE masking signal to prevent arbitrary data from being output in synchronization with a masking period during an initial operation; and a step of receiving an image according to the gate and SOE masking signals and implementing the image, .

In the present invention, since an SOE masking signal is generated and applied, an image signal is not inputted to the liquid crystal panel during initial driving of the liquid crystal display device. Accordingly, it is possible to prevent a certain gradation voltage from being applied to the data line from the data drive when the liquid crystal display device is initially driven, so that a vertical line or the like is generated on the screen to prevent the image quality from deteriorating.

Hereinafter, a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings. 2 is a view showing a structure of a driving unit of a liquid crystal display device according to the present invention.

2, the liquid crystal display according to the present invention includes a timing controller 110, a gate driver 112 for receiving a signal from the timing controller 110 and outputting a gate signal and a pixel signal, And a liquid crystal panel 116 to which the signals output from the gate driver 112 and the data driver 114 are applied.

In the liquid crystal panel 116, a plurality of liquid crystal cells defined by a plurality of gate lines GL1-GLn and data lines DL1-DLm are arranged in a matrix, and TFTs are formed in each of the liquid crystal cells .

The timing controller 110 includes a data sorting unit 110a for sorting video data input through a graphics card in a system driving unit not shown in the figure, a gate driver 112 and data A control signal generation unit 110b for generating a control signal such as a timing signal for controlling the timing of the driver 114 and an SOE generating unit 110b for generating an SOE masking signal using the SOE signal provided from the control signal generation unit 110b, And a masking signal generator 110c.

The graphics card in the system driver converts input video data to a resolution of a liquid crystal display device and outputs the converted video data to a liquid crystal display device. At this time, the video data is composed of red, green, and blue data. In addition, the graphics card generates control signals such as a clock signal DCLK, a horizontal synchronization signal Hsync, and a vertical synchronization signal.

The timing controller 110 arranges the video data Data converted from the graphics card in the data arrangement unit 110a and supplies the video data to the data driver 114. In the control signal generation unit 110b, A gate shift clock (GSC), a gate output enable (GOE), a gate start pulse (Gate Start Pulse) to control the timing of the gate driver 112 and the data driver 114, (SSP), Source Start Pulse (SSP), and Polarity Reverse (SSP), as well as a gate control signal, such as a source clock, POL, a data polarity selection (REV), an odd / even pixel data (Odd / Even data) signal, and the like.

In this case, the GSC is a signal for determining the on / off time of the gate of the TFT, GOE is a signal for controlling the output of the gate driver 112, and the GSP is a signal It is a signal that signals the first drive line. The SSC is used as a sampling clock for latching data in the data driver 114, and determines the driving frequency of the data drive IC. The SOE causes data corresponding to one horizontal line latched by the SSC to be simultaneously transmitted to the liquid crystal panel, and the SSP is a signal for notifying the start of data latching or sampling during one horizontal synchronization period. The POL is a polarity signal for driving the liquid crystal in the positive or negative polarity for driving the inversion of the liquid crystal. REV is a signal for selecting the polarity of the data to be transmitted. The odd / And represents the odd data of even-numbered pixels.

The SOE masking signal generator 110c receives the SOE signal from the control signal generator 110b to generate an SOE masking signal. The SOE masking signal is an SOE signal having a masking period for a predetermined period of time when the liquid crystal display device is initially driven. The masking period is a period during which the data of the gray scale voltage is supplied from the data driver 114 to the liquid crystal panel 116, The SOE masking signal generating unit 110 is formed integrally with the data aligning unit 110a and the control signal generating unit 110b in the timing controller 110. However, The SOE masking signal generating unit 110 may be formed outside the timing controller 110 separately from the data aligning unit 110a and the control signal generating unit 110b.

On the other hand, the gate driver 112 turns on / off the gate terminals of the thin film transistors arranged on the liquid crystal panel 116 by one line corresponding to the control signals inputted from the timing controller 110, 114 to the corresponding liquid crystal cell through the thin film transistor.

The data driver 114 samples the video data (R, G, B) input from the timing controller 110 and latches the sampled data and then converts the data stored in the latch into a gray scale voltage, 116).

Although not shown in the figure, the data driver 114 includes a data register in which data (RGB) is input from the timing controller 110, a shift register that generates a sampling clock, a shift register that shifts the shift register and m data lines A first latch and a second latch connected between the first and second latches DL1 to DLm, a gamma-gradation voltage circuit for dividing the gamma reference voltages and supplying the voltage to a digital-to-analog converter (DAC) An output unit and an output control unit 114a.

The data register temporarily stores data (RGB) input from the timing controller 110 and then supplies the stored data (RGB) to the first latch. The shift register receives a source start pulse SSP) according to the source sampling clock SSC to generate a sampling signal. In addition, the shift register shifts the source start pulse SSP and transfers the carry signal CAR to the next shift register. The first latch samples the digital video data RGB input from the data register in response to the sampling signal sequentially input from the shift register, and latches the sampled digital video data RGB one line at a time. The second latch latches the digital data RGB input from the first latch and then outputs the latched digital video data RGB to the data line in response to the SOE masking signal input from the timing controller 110 . The gamma gradation voltage circuit divides the gamma reference voltages divided in the reference voltage generator by the voltage input from the external power supply voltage generator to generate gamma gradation voltages corresponding to the respective gradations.

The DAC selects and outputs the gradation voltage of the corresponding level supplied from the gamma gradation voltage circuit corresponding to the video data (RGB) input from the second latch. At this time, the gradation voltage is output as a positive or negative voltage according to the polarity control signal output from the timing controller.

The output circuit temporarily stores the R, G, and B pixel voltages of the analog type selected and output from the DAC in an internal buffer. The output control unit 114a is formed of a switch interlocked with the buffer of the output circuit. When the SOE masking signal applied to the second latch is applied to control the switch, So that it can be prevented from being output to the panel 116.

Hereinafter, the configuration and operation principle of the SOE masking signal generator 110c in the timing controller 110 according to the present invention will be described in more detail with reference to FIG. 3 and FIG. 3, the SOE masking signal generation unit 110c includes a masking signal generation unit 210 and an operation unit 220 including an OR gate. The masking signal generator 210 includes an oscillator 211 for generating a clock having a periodicity at predetermined intervals, a counter 210 for counting the clock generated by the oscillator 211 and periodically inverting the clock signal at predetermined intervals And outputs a masking signal in a high state to the arithmetic operation unit 220. When the counting signal is lower than the reference value of the counting signal in response to the counting signal input from the counter 213, And a comparator 215 for generating a masking signal in a low state and outputting the masking signal to the arithmetic operation unit 220. [

The generation of the SOE masking signal in the SOE masking signal generator 110c will be described with reference to the waveform diagram shown in FIG. In the following description, the generation of the SOE masking signal will be described by way of example with reference to a specific frequency or a signal section, but this is merely for convenience of explanation, and the present invention is not limited to this particular frequency or signal section.

4, when an oscillation signal of 100 kHz is generated in the oscillation unit 211, the counter 213 synchronizes with the initial setup of the liquid crystal display device and outputs a clock (n = 500). The comparison unit 215 sets a reference value corresponding to 5 ms, and generates a masking signal maintaining a high state before the first reference value and maintaining a low state after the reference value. That is, the counter 213 counts the clock, outputs the high-level signal at the comparator 215 before the reference clock, and outputs the low-level signal at the comparator 215 after the reference clock. As described above, the counter 213 may output a masking signal in a high state at the time of initial driving of the liquid crystal display device, but may output a masking signal in a low state. And outputs a low signal when the clocked clock is earlier than the reference clock and outputs a high signal after the reference clock. The operation unit 220 includes an OR gate, and the timing controller 110 And a masking signal input from the masking signal generator 210. The SOE masking signal is generated by a logical operation of the SOE signal input from the control signal generator 110b and the masking signal input from the masking signal generator 210. [

The SOE masking signal is input to the data driver 116. 5A, the data driver 114 includes an output control unit 114a, a buffer unit 114b, and a switching signal generation unit 114c. The output controller 114a includes a first switch SW1 and a second switch SW2. The SOE masking signal output from the operation unit 220 is applied to the output control unit 114a through the buffer unit 114b of the data driver 114. [ 5B, when the SOE masking signal is input, the switching signal generator 114c generates a switching signal for controlling the first switch SW1 and the second switch SW2 of the output controller 114a Output.

The switching signal generator 114c may be formed in the data driver 114 together with the buffer 114b and the output controller 114a as described above but may be formed separately from the data driver 114, It might be.

 When the liquid crystal display device is initially driven, an image signal including the effective image voltage is input to the pixels of the liquid crystal display device. At this time, the effective image voltage means a voltage for an actually desired image. That is, the effective image voltage means an actual image signal which excludes an initial image signal and realizes a desired image.

As shown in FIG. 5B, the first switching signal and the second switching signal are input to the first switch SW1 and the second switch SW2, respectively, in the initial operation. As shown in FIG. 5B, the second switching signal maintains a low state at the initial driving of the liquid crystal display device. Therefore, the second switch SW2 is maintained in the off state, and the pixel signal is not inputted to the data line through the second switch SW2. At this time, a first switching signal in a low state applied to the first switch SW1 is inputted, and the first switch SW1 is turned off.

As described above, since the second switch SW2 is turned off at the time of initial driving of the liquid crystal display device, the image signal is not inputted to the liquid crystal panel (the section in which the image signal is not input in this way is referred to as a masking section). Accordingly, it is possible to prevent a certain gradation voltage from being applied to the data line from the data drive when the liquid crystal display device is initially driven, so that a vertical line or the like is generated on the screen to prevent the image quality from deteriorating.

A low signal is applied to the first switch SW1 to turn off the first switch SW1 and the second switch Sw2 to apply a high signal to the second switch SW2, And a pixel signal of an effective image voltage is applied to the pixels of the liquid crystal panel to realize an image. When a high signal is input to the first switch SW1 so that the first switch SW1 is turned on and the low signal is inputted to the second switch SW2 so that the second switch SW2 is turned off, The output line of each buffer unit 114b and the adjacent line are short-circuited, thereby outputting the intermediate level of the bilamer voltage.

6 is a waveform diagram showing states of a gate signal voltage, a data signal, and an SOE masking signal at the time of initial driving of the liquid crystal display device according to the present invention. As shown in FIG. 6, when the gate voltage is turned off at the time of initial driving to become the gate-high voltage (Vgh) to the gate-low voltage (Vgl), the ideal gate voltage forms a square wave, Thereby forming a tail. In FIG. 6, the tail occurs at the tail section t. The tail of the gate voltage is not turned on only at the time when the TFT is set at the time of initial driving of the liquid crystal display element but is not turned on even at the time not set. The masking period is formed in the tail period. The switches constituting the output control unit of the data driver are momentarily turned off in synchronization with the rising edge of the masking period, thereby preventing any data output in the masking period And the normal pixel voltage is output from the data driver in synchronism with the SOE period.

As described above, in the present invention, since the SOE masking signal is generated and applied, the image signal is not inputted to the liquid crystal panel at the time of initial driving of the liquid crystal display device. Accordingly, it is possible to prevent a certain gradation voltage from being applied to the data line from the data drive when the liquid crystal display device is initially driven, so that a vertical line or the like is generated on the screen to prevent the image quality from deteriorating.

On the other hand, the present invention is not limited to the above description.

The present invention prevents the image quality from being degraded by turning on the TFT at a time when the TFT is not set at the time of initial driving of the liquid crystal display device due to a tail generated at the gate-high voltage. Therefore, any configuration can be used as long as it can prevent deterioration of image quality due to the tail of the gate-high voltage.

For example, as shown in FIG. 7, by delaying the driving time point of the gate voltage Vg by a predetermined period (?), It is possible to prevent the TFT from turning on in the tail of the data signal, . That is, by synchronizing the timing at which the tail of the gate voltage Vg ends with the timing at which the effective data signal is input, the image quality can be prevented from being lowered by being turned on at the time when the TFT is not set during the initial driving of the liquid crystal display element will be.

1 is a block diagram showing a driving system of a conventional liquid crystal display device.

2 is a block diagram showing a driving system of a liquid crystal display according to the present invention.

3 is a block diagram illustrating the structure of the SOE masking signal generator of FIG.

FIG. 4 is a diagram showing an operation waveform of a sub-block of the SOE masking signal generating unit shown in FIG. 3; FIG.

FIG. 5A is a view showing a coupling relationship between the data driver and the liquid crystal panel shown in FIG. 2; FIG.

5B is a waveform diagram showing a switching control signal applied to the data driver of FIG. 5A,

6 is a waveform diagram of a liquid crystal display device according to the present invention.

7 is another waveform diagram of a liquid crystal display device according to the present invention.

Claims (15)

A liquid crystal panel including a plurality of gate lines, a data line, and a thin film transistor; A timing controller which receives a data and a vertical / horizontal synchronizing signal from the outside and generates a control signal including an SOE masking signal for masking an image signal before the effective image signal is inputted to the liquid crystal panel; A gate driver for outputting a gate signal to the gate line according to the control signal; And And a plurality of switches for outputting an image signal to the data line in response to the control signal and for blocking the output of the image signal before the effective image signal is inputted by receiving the SOE masking signal, Lt; / RTI > The data driver includes: A shift register for shifting a source start pulse input from a timing controller according to a source sampling clock signal to generate a sampling signal; A data register for temporarily storing digital video data (RGB) input from the timing controller; A first latch for latching the digital video data from the data register one line at a time in response to a sampling signal sequentially input from the shift register; And A second latch for latching the digital data input from the first latch and simultaneously outputting the latched data in response to the SOE period of the SOE masking signal; And the liquid crystal display device. The apparatus of claim 1, wherein the timing controller Data sorting means for receiving and rearranging R, G and B data from outside; Control signal generating means for generating a control signal including a gate output enable (GOE) signal and an SOE signal by receiving a vertical / horizontal synchronizing signal from the outside; And And SOE masking signal generating means for receiving the SOE signal from the control signal generating means and combining the masking signal with the SOE signal to generate the SOE masking signal. The data driver according to claim 1, A gradation voltage generator for generating positive and negative gradation voltages by dividing the reference voltage from the outside; A DAC for selecting and outputting a gradation voltage corresponding to data latched in the second latch from a gradation voltage generator in accordance with a polarity control signal input from the timing controller; And An output unit for holding the gradation voltage from the DAC in a buffer; And the liquid crystal display device. The liquid crystal display device according to claim 1, wherein the time (T) for the section before the effective image signal is input from the power-on time is 0 < 2. The liquid crystal display of claim 1, wherein the SOE masking signal is initiated in a high state during initial operation. The apparatus as claimed in claim 2, wherein the SOE masking signal generating means An oscillator for generating a clock at a predetermined period; A counter for inverting the clock every predetermined number of times; A comparator for outputting a high when the clock counted by the counter is lower than or equal to a reference value and outputting a low if the clock is higher than a reference value; And And a calculator for calculating a signal output from the comparator with an SOE signal. The liquid crystal display of claim 6, wherein the operator is an OR gate. delete delete delete delete delete delete delete delete

Images