KR20100069900A - Apparatus and method for driving liquid crystal display device - Google Patents

Abstract

PURPOSE: A drive unit and a driving method of the liquid crystal display are provided to use the multiplexer for the driver circuit. The driving method for the low power mode is added in the driving method. The unnecessary power consumption is reduced. CONSTITUTION: A multiplexer(140) successively supplies the control signal provided from the output channel of data driver(130) to data lines. The timing control part(150) outputs the control signal of multiplexer to the control signal. The electricity mode conversion part(160) is input the video data from outside. Comparing presently inputted data with previously inputted data. The electricity mode is converted.

Description

Driving device for liquid crystal display and driving method thereof {APPARATUS AND METHOD FOR DRIVING LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a driving device of the liquid crystal display device and a driving method thereof to reduce power consumption.

In general, the liquid crystal display device displays an image corresponding to the video signal by adjusting the light transmittance of the liquid crystal according to the video signal. Such a liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix form, and driving circuits for driving the liquid crystal display panel.

On the active matrix type liquid crystal display panel, a plurality of data lines and a plurality of gate lines cross each other and are formed in a pixel driving thin film transistor (“TFT”) at an intersection thereof.

The driving circuit of the liquid crystal display includes a data driving circuit for supplying data to data lines of the liquid crystal display panel and a gate driving circuit for supplying scan pulses to the liquid crystal display panel.

1 is a view showing a driving device of a liquid crystal display according to the prior art.

As shown in FIG. 1, a driving apparatus of a liquid crystal display according to the related art includes m (where m is a positive integer) data lines DL1 to DLm and n (where n is a different amount from m). A liquid crystal display panel 17 in which a liquid crystal cell Clc is formed in a region defined by integer gate lines GL1 through GLn, and a data driver for supplying a video signal to the data lines DL1 through DLm. 13, a gate driver 14 for supplying scan pulses to the gate lines GL1 to GLn, and a timing controller 18 for controlling the data driver 13 and the gate driver 14. It is configured to include.

Liquid crystal is injected between the two substrates, and the liquid crystal display panel 17 is formed such that the data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to each other on the lower substrate. The thin film transistor TFT is formed. The thin film transistor TFT supplies a video signal on the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scan pulse supplied to the gate lines GL1 to GLn.

To this end, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc.

The timing controller 18 generates a gate control signal GCS and a data control signal DCS using synchronization signals supplied from a system (not shown).

In addition, the timing controller 18 rearranges the digital data input thereto and supplies the sorted data to the data driver 13.

The data driver 13 supplies one line of video signal to the data lines DL1 to DLm every horizontal period in response to the data control signal DCS supplied from the timing controller 18.

In particular, the data driver 13 converts digital data input from the timing controller 18 into an analog video signal using a gamma voltage and supplies the digital data to the data lines DL1 to DLm.

The gate driver 14 sequentially supplies scan pulses (gate high voltages) to the n gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 18.

Accordingly, the thin film transistors TFT connected to the gate lines GL1 to GLn are sequentially driven. In this case, the gate low voltage (eg, the ground GND voltage) is supplied to the non-driven gate lines GL.

The data driver 13 needs m output channels to drive the m data lines DL1 to DLm in the driving apparatus of the general liquid crystal display.

Therefore, in the driving apparatus of a general liquid crystal display device, when an output channel of each data driving circuit drives one data line DL, a plurality of data integrated circuits must be installed corresponding to the number of data lines DL, thereby manufacturing costs. This rising problem occurs.

In particular, as the liquid crystal display panel becomes larger and higher in resolution, such problems become more serious.

Therefore, in the conventional LCD driving apparatus, a multiplexer is disposed between the data driving circuit and the data lines to distribute one output of the data driving circuit to the multiple data lines, thereby reducing the number of data integrated circuits. It is reducing manufacturing costs.

That is, since the output number of the data driving circuit is reduced by the multiplexer, the data driver can be simplified and the number of data input terminals of the liquid crystal display panel is reduced.

However, the driving device of the liquid crystal display device according to the related art is fixed to an LCM product, and thus the operation of the liquid crystal display device may be performed in the same driving method even when a color such as a notebook or simple document processing is not necessary. Therefore, unnecessary power loss cannot be avoided.

That is, the driving device of the liquid crystal display device according to the related art uses each multiplexer control signal unconditionally regardless of image data, so that primary power loss occurs due to unnecessary swinging of the multiplexer, and the output of the source output is reduced. There is additional power loss in the version.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and a liquid crystal display device driving apparatus for reducing unnecessary power consumption by using a multiplexer in a driving circuit and adding a low power mode driving method to a driving method of an LCM product. The purpose is to provide a driving method.

The driving device of the liquid crystal display according to the present invention for achieving the above object is m (where m is a positive integer) and n (where n is a positive integer different from m) A liquid crystal display panel in which a liquid crystal cell is formed in an area defined by the display, a data driver for supplying a video signal to the data lines, a gate driver for outputting a scan pulse for driving the gate lines, and the liquid crystal display. A multiplexer unit formed in a panel to drive a plurality of source outputs supplied from an output channel of the data driver unit, a timing controller for controlling the data driver unit and the gate driver unit and controlling the multiplexer unit; It operates in accordance with the timing control signal output from the multiplexer section and a plurality of data lines of the data driver section. Tie driving compared and determines the switching unit, and a video data input from the external power mode switch for outputting an on-off signal to the signal controller which is characterized in that made in comprising: a.

In addition, the driving method of the liquid crystal display according to the present invention for achieving the above object is m (where m is a positive integer) and n (where n is a positive integer different from m) A driving method of a liquid crystal display device comprising a liquid crystal display panel having a liquid crystal cell in a region defined by gate lines, the method comprising: supplying a video signal to the data lines; Outputting a scan pulse for driving the gate lines; And outputting a plurality of timing control signals formed on the liquid crystal display panel to drive a plurality of source outputs of the data lines together, wherein the timing control signals correspond to current image data among image data input from the outside. Comparing and determining previous image data to output an on / off signal, and receiving an on signal among the on / off signals to bundle a plurality of output lines among the data lines to output the same waveform.

The driving apparatus and driving method thereof of the liquid crystal display according to the present invention have the following effects.

First, it can reduce the power consumption of LCM products with multiplexer by switching to low power mode when working with simple documents or when color is not necessary.

Second, LCM products using low power consumption through power mode can be applied to portable applications.

Third, power consumption can be reduced without changing the TFT by changing the mode based on the image data.

Hereinafter, a driving apparatus and a driving method thereof of a liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

2 is a configuration diagram schematically showing a driving device of a liquid crystal display according to the present invention.

In the driving apparatus of the liquid crystal display according to the present invention, as illustrated in FIG. 2, m data lines DL1 to DLm and n gate lines GL1 to GLn cross each other, and a pixel driving part is disposed at an intersection thereof. A liquid crystal display panel 110 having a TFT (not shown), a gate driver 120 for sequentially supplying scan pulses to gate lines GL1 to GLn of the liquid crystal display panel 110, and the liquid crystal A data driver 130 for supplying digital video data to the data lines DL1 to DLm of the display panel 110 and the liquid crystal display panel 110 and provided to the data lines GL in three units. Controlling the multiplexer 140 for sequentially supplying control signals supplied from the output channels DL1 to DLm / 3 of the data driver 130, and controlling the data driver 130 and the gate driver 120. In addition, the control signal of the multiplexer 140 receives various The timing controller 150 for outputting a control signal and the image data input from the outside to compare the current input data and the previously input data to switch the power mode to supply the power to the multiplexer 140 It is configured to include a mode switching unit 160.

Here, the liquid crystal display panel 110 is a liquid crystal is injected between the two substrates, the data lines (DL1 to DLm) and the gate lines (GL1 to GLn) are formed to be orthogonal to each other on the lower substrate, The thin film transistor is formed in the cross region.

The thin film transistor supplies a video signal on the data lines DL1 to DLm to the liquid crystal cell in response to a scan pulse supplied to the gate lines GL1 to GLn. To this end, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell.

In addition, a storage capacitor is formed in the liquid crystal cell of the liquid crystal display panel 110. The storage capacitor is formed between the pixel electrode of the liquid crystal cell and the front gate line GL or between the pixel electrode of the liquid crystal cell and the common electrode. It is formed in the to keep the voltage of the liquid crystal cell constant.

The timing controller 150 generates a gate control signal and a data control signal using synchronization signals supplied from a system (not shown). Here, the gate control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like.

The data control signal DCS includes a source start pulse SSP, a source shift clock SSC, a source output enable SOC, and a polarity POL. And the like.

In addition, the timing controller 150 rearranges the digital data input thereto and supplies the sorted data to the data driver 130. In addition, the timing controller 150 generates a control signal to the multiplexer 140 based on the information input from the power mode switch 160.

The multiplexer unit 140 generates the first to third switching control signals MUX1, MUX2, and MUX3 according to a control signal input from the timing controller 150, so that the number of source output channels of the data driver 130 is increased. Reduce That is, the number of output channels of the data driver 130 is reduced to m / 3.

The data driver 130 includes a plurality of data integrated circuits (not shown). Each data integrated circuit supplies one line of video signal to the data lines DL1 to DLm every horizontal period in response to a data control signal supplied from the timing controller 150.

In particular, the data driver 130 converts the digital data input from the timing controller 150 into an analog video signal using a gamma voltage and supplies the digital data to the data lines DL1 to DLm.

Specifically, the data driver 130 shifts the source start pulse SSP according to the source shift clock SSC to generate a sampling signal. Subsequently, in response to the sampling signal, digital data is sequentially input and latched in predetermined units.

Here, the switching unit 170 is configured to operate by receiving timing control signals MUX1, MUX2, and MUX3 output from the multiplexer unit 140. That is, the switching unit 170 is intended to reduce the number of outputs by tying and driving a plurality of output lines output from the data driver 130.

The switching unit 170 is composed of three PMOS transistors according to an exemplary embodiment of the present invention. The three output lines adjacent among the output lines of the data line are sequentially output by the timing control signals sequentially output from the multiplexer unit 140. Drive the bundle.

That is, since the switching unit 170 is made of a PMOS transistor, when the timing control signal output from the multiplexer unit 140 is at a low voltage, the switching unit 170 turns on the image data stored in the data driver 130. 110 can be supplied.

The data driver 130 converts the latched one-line digital data into a video signal, which is an analog signal, and supplies the data data to the data lines DL1 through DLm in an enable period of the source output signal SOE.

Here, the data driver 130 converts the video signal into a positive polarity or a negative polarity in response to the polarity signal.

The gate driver 120 sequentially generates n scan pulses (gate high voltages) in response to the gate control signal from the timing controller 150.

At this time, a gate low voltage (eg, a ground GND voltage) is supplied to the output channels GL1 to GLn that are not driven. To this end, the gate driver 120 and the data driver 130 are composed of a plurality of gate integrated circuits and data integrated circuits (not shown). Each gate integrated circuit includes a shift register that sequentially generates scan pulses, that is, gate high pulses, in response to a gate start pulse GSP and a gate shift clock supplied from the timing controller 150, and a scan pulse voltage of the liquid crystal cell. And a level shifter for shifting to a level suitable for driving.

On the other hand, in the embodiment of the present invention has been described for controlling the three channels of the data driver 130, but is not limited to this can be configured to control the number of channels i (where i is an integer).

The multiplexer unit 140 sequentially supplies scan pulses from an output channel of the data integrated circuit to i data lines DL according to a control signal supplied from the timing controller 150.

3 is a diagram schematically illustrating a configuration of a power mode switching unit of FIG. 2.

As shown in FIG. 3, the power mode switching unit 160 includes a frame memory 161 for receiving and storing image data supplied to a system (not shown), image data stored in the frame memory 161, and a current. And a comparator 162 for comparing the input image data and outputting an on-off signal.

The power mode switching unit 160 configured as described above is normally supplied with normal operation, that is, image data is normally supplied together with the timing controller 150 of FIG. 2. The signal is applied to the timing controller 150.

When the ON signal of the comparator 162 is applied, the timing controller 150 turns on the multiplexer 140, and outputs data such that the output of the source output terminal is mono in color. Control to output only once for 1H time.

Meanwhile, the comparison unit 162 receives the current image data and the previous image data among the input image data, compares an offset, and switches to the low power mode when the current image data and the previous image data are the same.

That is, FIG. 4 is a diagram illustrating a relationship between the timing control signals MUX 1, MUX 2, and MUX 3 of the multiplexer unit and the scan pulse Sn.

As shown in FIG. 4, the scan signal Gate n applied to the gate lines is generated as a gate low voltage for approximately one horizontal period H, and maintains the gate high voltage Vgl for other periods. The duty ratio of this scan signal is approximately one hundredth as one frame period includes several hundred horizontal periods (H).

Each of the timing control signals MUX 1, MUX 2, and MUX 3 of the multiplexer unit 140 is generated with a gate low voltage for approximately one third horizontal period every horizontal period. Since the duty ratio of each of the timing control signals MUX 1, MUX 2, and MUX 3 of the multiplexer unit 140 is generated every horizontal period, the duty ratio is approximately 1/2 to one minute.

Here, when the timing control signal duty ratio of the demultiplexer 14 is 1/3, it is a case where only three MUX TFTs are included in one multiplexer.

The MUX TFTs MT1, MT2, MT3 and the pixel driving TFT, which are turned on and off by receiving the timing control signal of the multiplier unit 140, are directly formed on the glass substrate of the liquid crystal display panel 110 and have a swing width of the gate. It is the same between the high voltage and the gate low voltage.

However, the MUX TFTs MT1, MT2, and MT3 of the multiplexer 140 time-division data input through one source line in response to different timing control signals MUX 1, MUX 2, and MUX 3. Supplies to four data lines.

As such, the source outputs Sn and Sn + 1 of the data driver 130 are connected through the plurality of data lines and the multiplexer unit 140, and the plurality of data lines are charged during one line. The number of source output channels of 130 is reduced.

Meanwhile, when the on signal is applied to the timing controller as shown in FIG. 3, the multiplexer outputs the same timing control signal as shown in FIG. 5.

That is, FIG. 5 is a diagram illustrating a relationship between the timing control signal of the multiplexer unit and the scan pulse Sn.

As shown in FIG. 5, in the timing controller 150 receiving the ON signal from the power mode switching unit 160, the timing control signals MUX 1, MUX 2, and MUX 3 output from the multiplexer 140 are uniform. The control signal is applied to make the same low voltage signal.

That is, power consumption generated when switching the multiplexer unit 140 by applying an ON signal from the power mode switching unit 160 to the timing controller 150 during a document operation or a job requiring no color. The source output can drive low power because the inversion frequency is reduced to 1 / mux.

Experimental results of applying the driving apparatus and driving method thereof according to the present invention are as follows.

That is, the power consumption of the LCD panel was about 11.42mW as a result of 3MUX application, mux on time 9us, period 45us, frequency 22.2kHz, mux voltage -8.0V ~ 10V.

On the other hand, when the power mode is switched to the low power mode, the power consumption of the liquid crystal display panel is about 9.84 mW under the same conditions as described above, which can reduce power consumption by about 13%.

On the other hand, the embodiment of the present invention has been described using the power mode switching unit to reduce power consumption by switching to the power mode when performing a document operation that uses a low power or a job that does not require color images, but is not limited thereto. Can also reduce power consumption by switching modes with manual offset input.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

1 is a view showing a driving device of a liquid crystal display according to the prior art;

2 is a configuration diagram schematically showing a driving device of a liquid crystal display according to the present invention.

3 is a view schematically showing the configuration of the power mode switching unit of FIG.

4 is a diagram illustrating a relationship between timing control signals MUX 1, MUX 2, and MUX 3 and a scan pulse Sn in the multiplexer unit.

5 is a diagram illustrating a relationship between a timing control signal of a multiplexer unit and a scan pulse Sn;

Explanation of symbols for the main parts of the drawings

110: liquid crystal display panel 120: gate driver

130: data driver 140: multiplexer

150: timing controller 160: power mode switching unit

170: switching unit

Claims (4)

a liquid crystal display panel in which a liquid crystal cell is formed in an area defined by m (where m is a positive integer) data lines and n (where n is a positive integer different from m); A data driver for supplying a video signal to the data lines; A gate driver for outputting a scan pulse for driving the gate lines; A multiplexer unit formed on the liquid crystal display panel to drive a plurality of source outputs supplied from an output channel of the data driver unit; A timing controller for controlling the data driver and the gate driver and controlling the multiplexer; A switching unit which operates according to a timing control signal output from the multiplexer unit and drives a plurality of data lines of the data driver unit; And a power mode switching unit configured to compare and determine image data input from an external device and output an on / off signal to the timing controller. The method of claim 1, wherein the timing controller receives the ON signal of the power mode switching unit and applies the same timing control signal through the multiplexer unit to drive a plurality of source output terminals output from the data driver. Driving device of liquid crystal display device. The apparatus of claim 1, wherein the power mode switching unit comprises a frame memory configured to receive and store image data supplied to the system, and a comparison unit configured to compare an image data stored in the frame memory with image data currently input and output an on / off signal. The driving device of the liquid crystal display device comprising a. Liquid crystal display panel comprising a liquid crystal display panel in which a liquid crystal cell is formed in an area defined by m (where m is a positive integer) data lines and n (where n is a positive integer different from m). In the driving method of the display device, Supplying a video signal to the data lines; Outputting a scan pulse for driving the gate lines; Outputting a plurality of timing control signals formed on the liquid crystal display panel to drive a plurality of source outputs of the data lines together; The timing control signal outputs an on / off signal by comparing and determining current image data and previous image data among image data input from the outside, and receives an on signal among the on / off signals to output an output line of the data line. A method of driving a liquid crystal display device, characterized in that a plurality of outputted to have the same waveform.

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