KR20150067840A - Driving circuit of display device - Google Patents

Abstract

The present invention relates to a driving circuit for a display device capable of sufficiently securing the charging time of pixels. It includes a data driver of outputting image data; and a multiplexer which time-shares the image data from the data driver according to control pulse signals which are successively from the outside, and output it. The pulse maintaining hours of control pulse signals outputted in an adjacent period are partly overlapped.

Description

[0001] DRIVING CIRCUIT OF DISPLAY DEVICE [0002]

The present invention relates to a driving circuit for a display device, and more particularly to a driving circuit for a display device capable of sufficiently securing the charging time of a pixel.

As the display device becomes larger, more pixels must be driven within a limited time, which results in a reduction in the charging time of the pixel. If the charging time of the pixel is insufficient, the charged amount of the pixel is reduced and the image quality is deteriorated. Particularly, this problem is more serious in a time division driving type display device using a multiplexer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device capable of increasing a charging time of a pixel by partially overlapping pulse holding times of control pulse signals supplied to a multiplexer, The present invention has been made to solve the above problems.

According to an aspect of the present invention, there is provided a driving circuit for a display device, including: a data driver for outputting image data; And a multiplexer for time-dividing and outputting image data from the data driver in accordance with control pulse signals sequentially supplied from the outside; And the pulse holding times of the control pulse signals output in the adjacent period are partially overlapped.

The active point of the control pulse signal output relatively late among the control pulse signals output in the adjacent period is faster than the active point of the control pulse signal output relatively earlier.

The control pulse outputted relatively late among the control pulse signals output in the adjacent period transitions to the inactive voltage within the effective period of the current image data corresponding to the control pulse signal and outputs the previous image data To an active voltage within a valid period of the voltage.

And the control pulse signals all have the same pulse duration.

The control pulse signals may include a first control pulse signal for controlling the output of the red image data among the image data, a second control pulse signal for controlling the output of the green image data among the image data, And a third control pulse signal for controlling the output of the blue image data among the data.

Wherein the multiplexer comprises: a first switching device for supplying red image data from the data driver to a red pixel according to the first control pulse signal; A second switching element for supplying green image data from the data driver to the green pixel according to the second control pulse signal; And a third switching element for supplying the blue image data from the data driver to the blue pixel according to the third control pulse signal.

The driving circuit for a display device according to the present invention has the following effects.

In the present invention, the pulse retention times of the control pulse signals supplied to the multiplexer may be partially overlapped to increase the pulse retention time relatively. Therefore, the charging time of the pixel is increased, and thus a high quality picture display can be assured even in a display device of high resolution.

1 is a view showing a display device according to an embodiment of the present invention;
2 shows a detailed configuration of the multiplexer of FIG. 1; FIG.
3 is a timing chart of image data, gate signals, and first through third control pulse signals

FIG. 1 is a diagram illustrating a display apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram showing a detailed configuration of the multiplexer of FIG.

1, a display device including a display panel (DSP), a data driver (DD), a gate driver (GD), a multiplexer (MUX), and a display driver Wherein the data driver DD, the gate driver GD, the multiplexer MUX and the timing controller TC are connected to the display panel DSP so that an image is displayed on the display portion of the display panel DSP. DSP) for driving the display device.

The display panel DSP includes i * j pixels (PXLs) for displaying an image and i (i is a natural number) gate lines GL1 to GLi connected to these pixels PXL and j Lt; / RTI > data lines DL1 to DLj. J pixels (PXL) arranged along one horizontal line are commonly connected to one gate line, and i pixels (PXL) arranged along one vertical line are connected in common to one data line. The i * j pixels PXL include a plurality of red pixels R for displaying a red image, a plurality of green pixels G for displaying a green image, and a plurality of red pixels R for displaying a red image, And blue pixels (B). The red pixels R, the green pixels G and the blue pixels B are arranged in a matrix form on the display portion of the display panel DSP.

Each of the red, green and blue pixels R, G and B includes a thin film transistor and a pixel electrode. The gate electrode of the thin film transistor is connected to the corresponding gate line. The drain electrode is connected to the corresponding data line, And the source electrode is connected to the pixel electrode. Wherein one side of each of the pixel electrodes is commonly connected to a common line. A liquid crystal is formed between the pixel electrode and the common electrode. The liquid crystal, the pixel electrode, and the common electrode form a liquid crystal capacitance capacitor. Each of the pixels further includes a storage capacitor, which is formed at a portion of the pixel electrode provided in the pixel and a gate line (a front gate line) preceding the gate line to which the pixel is connected .

The data driver DD supplies j pieces of image data to j data lines DL1 to DLj via a multiplexer (MUX). The data driver DD converts the red, green, and blue image data supplied from the timing controller TC into an analog signal and supplies the analog red, green, and blue image data to the j data lines via the multiplexer (MUX) (DL1 to DLj). That is, the data driver DD converts the red, green, and blue image data corresponding to the pixels (j pixels) of one horizontal line driven by the gate driver GD into an analog signal, (P is a natural number smaller than j) output channels (OC1 to OCp) composed of a smaller number of j pieces of image data of one horizontal line. At this time, the data driver DD sequentially outputs j image data divided into three for one horizontal period (one horizontal period). For example, the data driver DD simultaneously outputs the red image data among the j image data through the p output channels OC1 to OCp during the first period of the horizontal period, Green image data among the plurality of image data is simultaneously output through the p output channels OC1 to OCp during the second period of the horizontal period and then blue image data among the j image data is output to the horizontal period (OC1 through OCp) for the third period of the second period.

The multiplexer MUX time-divides and outputs j pieces of image data from the data driver DD in accordance with the control pulse signals CPS1 to CPS3 provided from the timing controller TC, and outputs the time- To the data lines DL1 to DLj sequentially. To this end, the multiplexer MUX includes switching elements SW1 to SW3 which are sequentially turned on according to the first to third control pulse signals CPS1 to CPS3, as shown in Fig. 2 .

The first switching device SW1 supplies red image data from the data driver DD to the red pixel R in accordance with the first control pulse signal CPS1 and the second switching device SW2 supplies the red image data from the data driver DD to the red pixel R, And supplies the green image data from the data driver DD to the green pixel G according to the signal CPS2 and the third switching element SW3 supplies the green image data from the data driver DD according to the third control pulse signal CPS3. To the blue pixel (B).

To this end, the gate electrode of the first switching device SW1 is connected to the first control line CL1 to which the first control pulse signal CPS1 is applied, and the drain electrode (or source electrode) thereof is connected to the first output channel OC1, and its source electrode (or drain electrode) is connected to the first data line DL1.

The gate electrode of the second switching element SW2 is connected to the second control line CL2 to which the second control pulse signal CPS2 is applied and its drain electrode (or source electrode) is connected to the first output channel OC1 , And its source electrode (or drain electrode) is connected to the second data line DL2.

The gate electrode of the third switching device SW3 is connected to the third control line CL3 to which the third control pulse signal CPS3 is applied and its drain electrode (or source electrode) is connected to the first output channel OC1 , And its source electrode (or drain electrode) is connected to the third data line DL3.

 At this time, the turn-on period of the first switching device SW1 partially overlaps the turn-on period of the second switching device SW2, and the turn-on period of the second switching device SW2 and the turn- The turn-on period of the switch SW3 partially overlaps. This turns on the second switching device SW2 before the first switching device SW1 is turned off and also turns on the third switching device SW3 before the second switching device SW2 is turned off, On in advance. Accordingly, since the turn-on time of the second switching device SW2 and the third switching device SW3 can be longer than that of the prior art, it is possible to secure a sufficient charging time for the data lines in time division driving. To this end, the second control pulse signal CPS2 is activated so that the pulse holding time of the first control pulse signal CPS1 and the pulse holding time of the second control pulse signal CPS2, which are output in the adjacent period, The third control pulse signal CPS3 so that the pulse holding time of the second control pulse signal CPS2 and the pulse holding time of the third control pulse signal CPS3 that are output in the adjacent period are partially overlapped, ) Can be advanced.

On the other hand, in order for the turn-on time of the first switching device SW1 to have the same turn-on time as the above-described second switching device SW2 (or the third switching device SW3) The pulse holding time of the first control pulse signal CPS1 supplied to the first switch SW1 may also be the same as the second control pulse signal CPS2 (or the third control pulse signal CPS3).

On the other hand, in order to partially overlap the pulse holding time of the first control pulse signal CPS1 and the pulse holding time of the second control pulse signal CPS2 outputted in the adjacent period, The second control pulse signal (CPS2) is generated so as to partially overlap the pulse holding time of the second control pulse signal CPS2 and the pulse holding time of the third control pulse signal CPS3, It is also possible to extend the inactive timing of the CPS2 backward.

Here, the active time of a signal means a time point at which the signal transits from the inactive voltage to the active voltage, and the inactive timing of the signal means a time point at which the signal transits from the active voltage to the inactive voltage. At this time, if the active voltage is the high logic voltage and the inactive voltage corresponds to the low logic voltage, the active time becomes the rising edge of the signal, and the inactive time becomes the falling edge of the signal falling edge. On the other hand, when the active voltage is the low logic voltage and the inactive voltage corresponds to the high logic voltage, the active point becomes the polling edge point of the signal, and the inactive point becomes the rising edge point of the signal. The active period of the signal means a period in which the signal is maintained in the state of the active voltage.

2, in addition to the first to third switching elements SW3 connected to the first output channel OC1 described above, the multiplexer MUX is connected to each of the remaining output channels OC2 to OCp And the first to third switching elements are also connected to the first to third switching elements connected to the first output channel OC1. Are connected between the corresponding output channels and the corresponding data lines in the same manner as the switches SW1 to SW3. For example, another first through third switching elements are connected between the second output channel OC2 and the fourth through sixth data lines DL4 through DL6. In this case, The drain electrodes of the elements are connected in common to the second output channel OC2, and each of the source electrodes thereof is individually connected to each of the fourth to sixth data lines DL4 to DL6. On the other hand, all the first switching elements SW1 included in the multiplexer MUX are supplied with the first control pulse signal CPS1 in common regardless of the output channels to which they are connected, and all of the first switching elements SW1 included in the multiplexer 2 switching elements SW2 are all supplied with the second control pulse signal CPS2 in common regardless of the output channels to which they are connected and all the third switching elements SW3 included in the multiplexer MUX are connected to the output The third control pulse signal CPS3 is supplied in common regardless of the channel.

The characteristics of the first to third control pulse signals CPS1 to CPS3 described above with reference to FIG. 3 will now be described.

3 is a timing chart of the video data, the gate signals GS, and the first to third control pulse signals CPS1 to CPS3.

As shown in FIG. 3, the first to third control pulse signals CPS1 to CPS3 are sequentially output. For example, the first, second, and third control pulse signals CPS1, CPS2, and CPS3 are sequentially output during the first horizontal period Hn during which the gate signal GS is maintained at the active voltage. At this time, the active time point R1 of the first control pulse signal CPS1 is the most advanced, the active time point R3 of the third control pulse signal CPS3 is the latest, The time point R2 is located between the active time point R1 of the first control pulse signal CPS1 and the active time point R3 of the third control pulse signal CPS3.

At this time, the active point of the control pulse signal output relatively late among the control pulse signals output in the adjacent period is relatively fast, so that the pulse retention times of the two control pulse signals output in the adjacent period may partially overlap each other. Is faster than the active point of the output control pulse signal. For example, as shown in FIG. 3, the active time point R2 of the second control pulse signal CPS2 is faster than the inactive time point F1 of the first control pulse signal CPS1. Thereby, the second control pulse signal CPS2 is maintained in the active voltage state by a time length corresponding to the overlap period OV1 between the active time point R2 and the inactive point in time F1. Similarly, the third control pulse signal CPS3 is maintained in the active voltage state by a time length corresponding to the overlap period OV2 in which the second control pulse signal CPS2 and the third control pulse signal CPS3 overlap, .

In addition, the control pulses outputted relatively later among the control pulse signals output in the adjacent period, so that the image data Img_D of each color can be correctly supplied to the correct pixels, To the inactive voltage, and transitions to the active voltage within the effective period of the previous image data output before the current image data. For example, as shown in FIG. 3, the inactive point of time F2 of the second control pulse signal CPS2 is located within the valid period VP_B of the green image data G_Dn. Therefore, when the second control pulse signal CPS2 reaches the inactive point in time F2, the green video data G_Dn is kept charged in the corresponding data line (i.e., the data line connected to the green pixel). Likewise, when the third control pulse signal CPS3 reaches the inactive point in time F3, the blue data B_Dn is kept charged in the data line (i.e., the data line connected to the blue pixel). Also, when the first control pulse signal CPS1 reaches the inactive point F1, the red image data R_Dn is kept charged in the corresponding data line (i.e., the data line connected to the red pixel). The green data G_Dn-1, B_Dn-1, R_Dn + 1 and G_Dn + 1 shown in FIG. 3 are the green image data in the n-1th horizontal period Hn- -1), red image data in the (n + 1) -th horizontal period Hn + 1, and green image data in the (n + 1) -th horizontal period Hn + 1. Although not shown, the data output first in the (n-1) -th horizontal period Hn-1 is red image data, and the data output latest in the (n + 1) -th horizontal period Hn + Data.

The first control pulse signal CPS1 may have the same form as the second and third control pulse signals CPS2 and CPS3 described above. In such a case, as shown in FIG. 3, the first to third control pulse signals CPS1 to CPS3 all have pulse holding times of the same length.

3, the starting point of the valid period VP_R of the active time point R1 and the red video data R_Dn of the first control pulse signal CPS1 located in the nth horizontal period Hn is set to the nth It is possible to further secure the charging time of the red video data R_Dn by advancing further to the active point of the gate signal GS in the horizontal period Hn.

3, the inactive time F3 of the third control pulse signal CPS3 located in the n-th horizontal period Hn is set to the inactive time point of the gate signal GS in the n-th horizontal period Hn And the end time of the valid period VP_B of the blue image data B_Dn in the nth horizontal period Hn is set to the inactive period of the gate signal GS in the nth horizontal period Hn, It is possible to further secure the charging time of the blue image data B_Dn by extending to the point when it is completely held by the voltage (time later than the inactive point of time of the gate signal).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Img_D: Image data GS: Gate signal
R_Dn, R_Dn + 1: Red image data B_Dn-1, B_Dn: Blue image data
G_Dn-1, G_Dn, G_Dn + 1: green image data CPS #: # control pulse signal
H #: Horizontal Period OV #: Overlap Period
VP_R, VP_G, VP_B: Valid period R1-R3:
F1-F3: Inactive point

Claims (6)

A data driver for outputting image data; And
And a multiplexer for time-dividing and outputting image data from the data driver in accordance with control pulse signals sequentially supplied from the outside;
Wherein pulse holding times of control pulse signals output in an adjacent period are partially overlapped. The method according to claim 1,
Wherein the active point of the control pulse signal output relatively late among the control pulse signals output in the adjacent period is faster than the active point of the control pulse signal output relatively earlier. The method according to claim 1,
The control pulse outputted relatively late among the control pulse signals output in the adjacent period transitions to the inactive voltage within the effective period of the current image data corresponding to the control pulse signal and outputs the previous image data And a transition is made to an active voltage within a valid period of the display driving circuit. The method according to claim 1,
Wherein the control pulse signals have pulse holding times of the same length. The method according to claim 1,
The control pulse signals may include a first control pulse signal for controlling the output of the red image data among the image data, a second control pulse signal for controlling the output of the green image data among the image data, And a third control pulse signal for controlling the output of the blue image data among the data. 6. The method of claim 5,
The multiplexer comprising:
A first switching element for supplying red image data from the data driver to a red pixel according to the first control pulse signal;
A second switching element for supplying green image data from the data driver to a green pixel according to the second control pulse signal; And
And a third switching element for supplying the blue image data from the data driver to the blue pixel according to the third control pulse signal.

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