JP2002278519A - Active matrix liquid crystal display and drive method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce relatively large power consumption of the output buffer circuit in a signal line drive circuit separated from a display memory of the display device, used for a portable electronic equipment driven by small sized batteries, especially an active matrix system liquid crystal display. SOLUTION: The signal line output circuit is made into an analog multiplexer and is integrated with the display memory for reducing the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal having a structure in which a signal line driving circuit of a liquid crystal panel and a control circuit including a display memory are integrated, thereby enabling low power, low cost, and high image quality. It relates to a display device. Further, the present invention relates to an active matrix liquid crystal display device having a function of arbitrarily selecting the number of display colors and capable of further reducing power in a low display color mode.

[0002]

2. Description of the Related Art In a display device used for a small portable electronic device driven by a battery such as a mobile phone, the number of pixels and the number of display colors tend to increase year by year. In addition to this, the continuous use time of the mobile phone is required to be further prolonged, and it is necessary to further reduce the power of the display device. One of the display devices that can meet the demand is a liquid crystal display device.
Many mobile phones are equipped with a simple matrix type liquid crystal display device using N and an active matrix type liquid crystal display device having a thin film transistor (TFT) in a pixel.

FIG. 7 shows a conventional active matrix liquid crystal display device used for a small portable electronic device. 7
Reference numeral 01 denotes an active matrix liquid crystal panel, which includes a thin film transistor 702 at the intersection of the signal lines S1 to Sn and the scanning lines G1 to Gm. 703, a signal line driving circuit;
Reference numeral 04 denotes a scanning line driving circuit, and reference numeral 705 denotes a control circuit for controlling these driving circuits. These circuits are generally composed of separate semiconductor integrated circuits. This is because the control circuit 705 includes a display memory as described below, so that the circuit scale is large and a fine semiconductor process is used. On the other hand, the signal line driving circuit 703 and the scanning line driving circuit 704 have operating voltages of respectively. 3-5V, 25
This is because a high withstand voltage semiconductor process is used because it is as large as about 30 V. The operating voltage of the signal drive circuit is as high as about 8 to 10 V when the positive voltage and the negative voltage are not used in common.

[0006] The control circuit 705 includes a control unit 706 and a display memory unit 707.
The active matrix liquid crystal panel 701 has a capacity according to the number of pixels and the number of display colors. The control circuit 705
Receives a digital video signal and a control signal such as a synchronization signal from the outside, writes display data in a display memory unit 707, and receives a display signal stored in a display memory 707 without receiving a digital video signal from the outside in a still image display mode. Power is reduced by repeatedly transferring data to the signal line driver circuit 703.

The signal line driving circuit 703 includes a shift register 708, a sampling latch 709, and a hold latch 7
10, a D / A converter 711, and an output buffer 712. The operation of the shift register 708 is briefly described below. The shift register 708 sequentially brings the sampling latches 709 into a fetched state according to the horizontal control signal sent from the control unit 706, and sequentially stores the display data sent from the display memory 707. When the data for one line is stored in the sampling latch 709, the control unit 706 sets the hold latch 710 in a fetched state and transfers the data for one line all at once. Thereafter, the hold latch holds the captured data, is converted into an analog voltage by the D / A converter 711, charges and discharges the signal line capacitance by the output buffer 712, and reaches a desired analog voltage.

As described above, the signal line driving circuit 703 outputs an analog voltage to the signal line Si every horizontal scanning cycle. The scanning line driving circuit 704 is synchronized with this.
Sequentially selects the scanning lines Gj. The thin film transistor 702 connected to the selected scanning line is turned on, and the signal line voltage at that time is written to the liquid crystal.

FIG. 8 shows an example of a D / A converter. D
The / A converter includes a reference resistor section 801, a decoder section 802, and a switch section 803. In accordance with the display data from the hold latch 710, the decoder unit 802 turns on one of the switches 803, selects one of the voltages from the reference resistance unit 801, and outputs it to the output buffer 712.

FIG. 9 shows an example of the configuration of an output buffer.
Transistors MN1 and MN2 are differential input sections composed of Nch, MP1 and MP2 are current mirror sections, MN3 is a constant current source switch, 901 is an output section, VIN is an input terminal, VOUT is an output terminal, and VB is a bias terminal. It is.
FIG. 9 shows a configuration of a so-called voltage follower operational amplifier in which the output terminal VOUT and the inverting input terminal of the input operation unit are connected. Actually, the differential input unit is not only Nch but also Pch so that the output voltage range is rail-to-rail that can be widely taken from ground voltage to power supply voltage.
Often configured with. In order to operate the differential input section, the constant current source switch MN3 must be turned on, and at this time, a current constantly flows from the power supply voltage to the ground voltage. In order to reduce the power due to the static current, there is a method of shutting off the constant current source switch MN3 after the charging and discharging of the signal line capacitance connected to the output terminal VOUT is completed within a predetermined time as a low power mode. .

Further, in order to reduce the power by limiting the number of display colors, a low display color mode voltage level 1002 may be provided in parallel with the output buffer 1001 as shown in FIG. For example, in the case of the binary display mode, the output buffer 10
The static current 01 is turned off, and the output switch control circuit 1004 outputs a binary voltage (white or black) from the output selection switch 1003 according to the binary data read from the display memory. RGB for color panel
Are binary values, and an eight-color display is obtained.

[0010]

In the structure of the conventional active matrix liquid crystal display device, a display memory using a fine process for reducing the area and a process having a relatively high withstand voltage for driving the liquid crystal are used. The signal line driving circuit including the configured output buffer has been configured by different semiconductor integrated circuits. Therefore, a shift register as an interface circuit, a serial conversion circuit for sending output data from a display memory to a signal line driving circuit, or a circuit for generating a control signal for a shift register included in a control unit, and the like are provided. Was needed.
Therefore, there is a problem that the power consumed by these circuits is large and the circuit area is large. Furthermore, when the display memory and the signal line drive circuit are formed by different chips, the power loss due to the wiring capacitance existing between the two cannot be ignored. In addition, since a plurality of semiconductor integrated circuits need to be prepared, there is a problem that the cost increases.

Further, in the configuration of the conventional active matrix liquid crystal display device, since an output buffer, that is, an operational amplifier is provided for each signal line, static power loss occurs in addition to the charge / discharge power of the signal line capacitance. Was. For example, when the number of horizontal pixels is 160, the output buffer for driving all signal lines is 160 × 3 (RGB)
= 480, 10uA per unit at power supply voltage 3V
Assuming that a static current of 3 × (10
× 0.001) × 480 = 14.4 mW, which occupies most of the power of the signal line driving circuit. In addition, such an increase in the power of the liquid crystal display device has led to a reduction in the continuous use time of the portable electronic device mounted.

Further, in the configuration of the conventional active matrix liquid crystal display device, an output deviation occurs due to a variation in the operational amplifier, thereby deteriorating the display quality. Also,
In order to cover the entire liquid crystal drive voltage range from white display to black display, it is necessary to employ a so-called rail-to-rail operational amplifier configuration, which increases the circuit area and power consumption.

Further, in the configuration of the conventional active matrix liquid crystal display device, even if the number of display colors is set to be small, all the operational amplifiers must be turned on, and the power is as low as when the number of display colors is set to be large. It was big.
Further, a configuration is conceivable in which a low display color mode voltage level is provided in parallel with the operational amplifier, and when the number of display colors is set small, the voltage level is output to a signal line to stop the operational amplifier. However, there is a problem that the control circuit becomes complicated and the circuit area becomes very large.

[0014]

To solve the above-mentioned problems, the following means have been taken. That is, the present invention is the same as an active matrix liquid crystal panel having a plurality of signal lines and a plurality of scanning lines arranged orthogonally to each other and a thin film transistor near an intersection thereof, and a first semiconductor integrated circuit for driving the scanning lines. A power supply circuit that is formed on the semiconductor chip and outputs a plurality of voltage levels, a storage circuit that stores display data, and an analog multiplexer that outputs one of the voltage levels to the signal line according to the display data. And a second semiconductor integrated circuit.

Further, the analog multiplexer is arranged for each of the signal lines, and comprises an output switch of a number equal to the number of the voltage levels, and a decoder for turning on one of the output switches in accordance with the display data. A power supply circuit includes a plurality of resistors connected in series, a switch that cuts off a current flowing through the resistors, and a plurality of buffer circuits that current-amplifies a voltage level at a connection point of the resistors and outputs the resultant to the analog multiplexer. A switching function of the number of display colors, and a function of turning on and off the switch and the buffer circuit according to the setting of the number of display colors.

Further, according to the present invention, the reading of the display data from the storage circuit is performed in parallel in units of at least a plurality of pixels of one horizontal pixel.

Further, in the present invention, the analog multiplexer displays a halftone of the voltage level by outputting a combination of two adjacent ones of the voltage levels to the signal line in a plurality of frame periods.

[0018]

(Embodiment 1) FIG. 1 shows a first embodiment of the present invention. An active matrix liquid crystal panel 101 includes a thin film transistor 102 at an intersection between the signal lines S1 to Sn and the scanning lines G1 to Gm. 103 is a signal line driving circuit, and 104 is a scanning line driving circuit. The signal line driving circuit 103 includes a control circuit 105, a display memory 106, a power supply circuit 107, and an analog multiplexer 108, which are integrated on the same semiconductor chip. Reference numeral 109 denotes a latch for temporarily storing data output from the display memory 106;
Reference numeral 10 denotes a circuit for inverting data according to the polarity inversion driving of the liquid crystal. The analog multiplexer 108 is connected to the signal line Si.
And selects one of the constant voltage levels V0 to Vk-1 output from the power supply circuit 107 and outputs it to the signal line. FIG. 2A illustrates an example of a configuration of an analog multiplexer. K analog switches 201 corresponding to the outputs V0 to Vk-1 of the power supply circuit;
And a level shifter circuit 203 which raises a logic voltage output from the decoder to a voltage at which the analog switch 201 can be turned on / off. For example, the value of the output voltage S when the input data is 4 bits is shown in FIG.
It is shown in (B). The analog switch 201 is provided for each signal line of the liquid crystal panel. For example, the analog switch may be shared by a plurality of signal lines for each of a plurality of adjacent pixels or RGB.

The circuit operation of FIG. 1 will be described. The control circuit 105 outputs a read control signal to the display memory 106 in accordance with an internally generated synchronization signal or an externally input synchronization signal. The read control signal is a configuration of the display memory, that is, a single port where input and output are common in read / write, a dual port where input and output are independent, or a control signal and input / output data are synchronized with a clock. For example, in the case of an asynchronous dual-port memory, data is generally input / output by a read / write address signal and an enable signal, depending on whether the operation is performed asynchronously.

In the case of a still image display, the display data stored in the display memory is repeatedly read. At this time, writing from the external signal source, for example, the MPU to the display memory can be stopped, and power consumption can be reduced. Data for one horizontal pixel is read from the display memory and stored in the latch 109. At this time, there are a case where data for one horizontal pixel is transferred simultaneously and a case where data is transferred serially one pixel or several pixels at a time. Transferring as much data as possible at once requires fewer circuits for generating control signals to the display memory, and lowers the frequency of the control signals, thereby reducing power consumption. Actually, the peak current at the time of memory reading may be suppressed, or a control signal having a cycle shorter than one horizontal scanning period may be required in some cases.

A data inverting circuit 110 is provided downstream of the latch, and inverts input data in accordance with a polarity inversion cycle. This is because it is necessary to drive the liquid crystal by AC at regular intervals, so that one set of voltage groups is used for both the positive voltage and the negative voltage applied to the liquid crystal, and the number of voltage levels to be prepared by the power supply circuit is one. This is because only the polarity can be used. However, in order to share the positive voltage and the negative voltage with one set of voltage groups, k voltage levels V0 to Vk-1 need to be symmetric with respect to the center.

Next, the operation of the data inverting circuit will be described with reference to FIG. FIG. 3 shows an example in which all white display is performed with normally white liquid crystal in the opposed one-line inversion drive. Sixteen voltage levels V0 to V15 (V0> V15) are input to the analog multiplexer, and "1111" is input as 4-bit data. The polarity inversion circuit inverts the input data according to the polarity inversion signal INV,
Perform non-inversion. It is assumed that INV = “0” for positive polarity and INV = “1” for negative polarity. It is assumed that the polarity when a pixel on a certain line is selected is positive, and non-inverted data is output from the polarity inversion circuit. At this time, while the opposite voltage Vcom is at the L level, V15 is output as the signal line voltage Vs from the analog multiplexer, and white display is performed. A negative polarity is applied to the pixels on the next line, but data obtained by inverting the input data is output from the polarity inversion circuit. Since the counter voltage Vcom is inverted to the H level, V0 is output as the signal line voltage Vs from the analog multiplexer, and the white display is also performed. As described above, the same voltage group V0 to V15 can be used regardless of whether the polarity is positive or negative. In this embodiment, the opposing inversion drive has been described. However, a capacitive coupling drive (Japanese Patent No. 2730286) may be used in which the voltage of the positive polarity and the voltage of the negative polarity can be commonly used while the opposing voltage Vcom is fixed.

According to this embodiment, since an operational amplifier is not used in the signal line output circuit and an analog multiplexer is used, a steady current does not flow, so that power consumption can be reduced. Further, since the display memory and the analog multiplexer are integrated, data read from the display memory can be transferred to the signal line output circuit in parallel. For this reason, the transfer frequency can be reduced, and a shift register circuit and a circuit for generating a control signal for the shift register, which are conventionally required, are not required, so that power consumption can be reduced.
Further, the wiring capacitance existing between the display memory and the signal line output circuit can be made sufficiently small, so that power consumption can be reduced.

(Embodiment 2) FIG. 4 shows a second embodiment of the present invention. Those having the same functions as those in FIG. Reference numeral 401 denotes a signal line driving circuit, which includes a control circuit 402, a display memory 106, a power supply circuit 107, and an analog multiplexer 108, as in FIG. A generation circuit 404 and a gradation control circuit 405 are provided for each signal line. When the power supply circuit 107 outputs, for example, 16 voltage levels, a 4-bit gray scale can be expressed. The present invention enables display when the display color setting unit 403 sets a display color such as 5 bits or 6 bits which is larger than the number of voltage levels. In this case, the grayscale control signal generation circuit 404 sends a control signal to the grayscale control circuit 405 for each frame or for each horizontal scanning cycle, and the grayscale control circuit 405 uses a plurality of frames for one pixel. The voltage level is selected so that two adjacent gradations are displayed in combination. For example, FIG.
When the number of voltage levels is 16 and the display color to be set is 6 bits, the voltage levels V0 and V1 are applied to one pixel in the order of (V0, V1, V0, V1) using four frames. Output. At this time, the pixel is displayed as the middle gray level of the gray levels displayed by V0 and V1. That is, V
When the gray scale corresponding to 0 is “gray scale 0” and the gray scale corresponding to V1 is “gray scale 1”, it can be regarded that “gray scale 0.5” is output. Also, (V0, V1,
V1, V1), it becomes "gradation 0.75". In this way, by displaying a plurality of frames in combination with adjacent gray levels, 16 gray levels become 61 gray levels, and 6 bits (64 gray levels) can be realized.

By using this embodiment, an analog multiplexer can be used for the signal line output circuit to display more gradations with a limited number of voltage levels, and the circuit scale of the analog multiplexer and the power supply circuit can be reduced. There is.

(Embodiment 3) FIG. 6 shows a third embodiment of the present invention. Reference numeral 601 denotes a power supply circuit in the signal drive circuit, which is used, for example, as the power supply circuit 107 in FIG. The power supply circuit 601 has a voltage level V0 applied to the liquid crystal.
ＶVk−1, and outputs it to the subsequent analog multiplexer. 602 is a display color setting means, and 603 is a stop signal generation circuit. The power supply circuit 601 includes a reference resistor unit 604 in which a plurality of resistors are connected in series, an operational amplifier 605 that is connected to a connection point of each resistor and amplifies the voltage level of the connection point with a current, and a constant current switch inside the operational amplifier 605. A bias circuit 606 that supplies a voltage to operate the operational amplifier and a cutoff switch 607 that cuts off a current flowing through the reference resistance unit 604 are provided.

When the number of display colors is set smaller than the number of voltage levels by the display color setting means 602, the stop signal generation circuit 603 outputs a stop signal to the bias circuit 606 and the cutoff switch 607, and the reference resistor 607 and the operational amplifier 605. Is set to 0. For example, it is assumed that 16 voltage levels are output by the power supply voltage V0, the ground voltage V15, and the voltages V1 to V14 output by the operational amplifier 605. At this time, a 4-bit gradation can be expressed. However, when the display color is set to 1-bit, that is, binary display by the display color setting means 602, the stop signal generation circuit 603 turns off the cutoff switch 607, and the bias circuit 6
06 to turn off the unused operational amplifier 605. When 2 bits or 3 bits are set, the cutoff switch 607 is turned on, and the bias circuit 606 is controlled to turn off only the unused operational amplifier. As described above, power consumption can be reduced according to the display color.

According to this embodiment, the degree of freedom in setting display colors can be increased, and the power can be reduced as the number of display colors set is smaller. In the conventional configuration, since the operational amplifier is used for the signal line output, the power consumed by the operational amplifier is constant regardless of the number of display colors.
Since the analog multiplexer is used for the signal line output, the output of the power supply circuit can be partially stopped, so that the power consumption can be further reduced.

[0029]

According to the first embodiment of the present invention, since an operational amplifier is not used in the signal line output circuit and an analog multiplexer is used, a steady current does not flow, so that low power can be achieved. effective. In addition, since the display memory and the analog multiplexer are integrated, the data transfer frequency from the display memory to the signal line output circuit is reduced, and there is no need for a shift register circuit and a circuit for generating control signals for the shift register, which were required in the past. Therefore, there is an effect that power consumption can be reduced. Further, since the wiring capacitance existing between the display memory and the signal line output circuit can be made sufficiently small, there is an effect that power consumption can be reduced. Further, there is no need to configure the display memory and the signal line drive circuit with separate semiconductor integrated circuits, and there is an effect that the cost can be reduced.

According to the second embodiment of the present invention, the degree of freedom in setting display colors can be increased, and more gradations can be displayed with a limited number of voltage levels by using an analog multiplexer for signal line output. Thus, there is an effect that the circuit scale of the analog multiplexer and the power supply circuit can be reduced. Furthermore, since the same voltage level output from the power supply circuit is commonly used for all signal lines, there is an effect that an output deviation does not occur and good image quality can be provided.

According to the third embodiment of the present invention, the degree of freedom in setting display colors can be increased, and the lower the number of display colors to be set, the lower the power consumption. Further, since the analog multiplexer is used for the output of the signal line, the output of the power supply circuit can be partially stopped, and the power can be further reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an analog multiplexer according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an operation of a data inversion circuit.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between voltage selection and gradation in a second embodiment of the present invention.

FIG. 6 is a diagram showing a third embodiment of the present invention.

FIG. 7 is a diagram showing a conventional configuration.

FIG. 8 is a diagram showing an example of a conventional D / A converter.

FIG. 9 is a diagram showing an example of a conventional output buffer.

FIG. 10 is a diagram showing an example of a conventional low display color mode.

[Explanation of symbols]

101, 701 Active matrix liquid crystal panel 102, 702 Pixel transistor (TFT) 103, 401, 703 Signal line drive circuit 104, 704 Scan line drive circuit 105, 402, 705 Control circuit 106, 707 Display memory 107, 601 For signal line drive Power supply circuit 108 Analog multiplexer 109 Latch 110 Data inversion circuit 201 Analog switch 202 Decoder 203 Level shifter 403, 602 Display color setting means 404 Gradation control signal generation circuit 603 Stop signal generation circuit 604, 801 Reference resistance section 605 Operational amplifier 606 Bias circuit 607 Cutoff Switch 706 Control circuit control unit 708 Shift register 709 Sampling latch 710 Hold latch 711 D / A converter 12, 1001 Output buffer 802 D / A converter decoder 803 D / A converter switch 901 Output 1002 Voltage level for low display color mode 1003 Output selection switch 1004 Output switch control circuit S1 to Sn Signal lines G1 to Gm Scan line V0 To V15, V0 to Vk-1 Signal line driving voltage level Vs Signal line voltage Vcom Counter voltage VIN Input voltage VOUT Output voltage VB Bias voltage MN1, MN2 Differential input section N-channel transistor MN3 Constant current source switch MP1, MP2 Current Mirror P-channel transistor

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 611 G09G 3/20 611A 624 624B F-term (Reference) 2H093 NA16 NA51 NA61 NC03 NC13 NC21 NC34 ND39 ND54 5C006 AA02 AA11 AA21 AC21 AF01 AF41 BB16 BC11 BC16 BF24 BF25 BF42 FA47 FA52 FA56 5C080 AA10 BB05 CC03 DD26 DD27 FF11 GG01 JJ02 JJ03 KK07 KK47

Claims (12)

[Claims] 1. An active matrix liquid crystal panel having a plurality of signal lines and a plurality of scanning lines arranged orthogonal to each other and a thin film transistor near an intersection thereof, and a first semiconductor integrated circuit for driving the scanning lines. A power supply circuit that is formed on the semiconductor chip and outputs a plurality of voltage levels, a storage circuit that stores display data, and an analog multiplexer that outputs one of the voltage levels to the signal line according to the display data. An active matrix liquid crystal display device, comprising: a second semiconductor integrated circuit having the same. 2. The active matrix liquid crystal display device according to claim 1, wherein said analog multiplexer is arranged for each of said signal lines. 3. The analog multiplexer according to claim 1, further comprising a number of output switches equal to the number of the voltage levels, and a decoder for turning on one of the output switches in accordance with the display data. Active matrix liquid crystal display device. 4. The active matrix liquid crystal display device according to claim 1, wherein said voltage level takes a value symmetric with respect to a median value. 5. An active matrix liquid crystal panel having a plurality of signal lines and a plurality of scanning lines arranged orthogonal to each other and a thin film transistor near an intersection thereof, and a first semiconductor integrated circuit for driving the scanning lines. A power supply circuit that is formed on the semiconductor chip and outputs a plurality of voltage levels, a storage circuit that stores display data, and an analog multiplexer that outputs one of the voltage levels to the signal line according to the display data. A method for driving an active matrix liquid crystal display device comprising: a second semiconductor integrated circuit, wherein reading of display data from the storage circuit is performed in parallel in units of at least a plurality of pixels of one horizontal pixel. A method for driving an active matrix liquid crystal display device. 6. The method of driving an active matrix liquid crystal display device according to claim 5, wherein said pixel unit is equal to one horizontal pixel number. 7. An active matrix liquid crystal panel having a plurality of signal lines and a plurality of scanning lines arranged orthogonally to each other and a thin film transistor near an intersection thereof, and a first semiconductor integrated circuit for driving the scanning lines. A power supply circuit that is formed on the semiconductor chip and outputs a plurality of voltage levels, a storage circuit that stores display data, and an analog multiplexer that outputs one of the voltage levels to the signal line according to the display data. A driving method of an active matrix liquid crystal display device comprising: a second semiconductor integrated circuit provided by the analog multiplexer, wherein the analog multiplexer combines adjacent two of the voltage levels with respect to the signal line in a plurality of frame periods. Outputting an output signal to display a halftone of the voltage level. The driving method of the scan liquid crystal display device. 8. The driving method of an active matrix liquid crystal display device according to claim 7, further comprising a function of switching the number of display colors, wherein the halftone display is performed when the number of display colors is large. 9. An active matrix liquid crystal panel having a plurality of signal lines and a plurality of scanning lines arranged orthogonal to each other and a thin film transistor near an intersection thereof, and a first semiconductor integrated circuit for driving the scanning lines. A power supply circuit that is formed on the semiconductor chip and outputs a plurality of voltage levels, a storage circuit that stores display data, and an analog multiplexer that outputs one of the voltage levels to the signal line according to the display data. An active matrix liquid crystal display device comprising: a second semiconductor integrated circuit comprising: a plurality of resistors connected in series; a switch for interrupting a current flowing through the resistors; and a connection between the resistors. A plurality of buffer circuits for current-amplifying a voltage level at a point and outputting the amplified voltage level to the analog multiplexer. Active matrix liquid crystal display device that. 10. The active matrix liquid crystal display device according to claim 9, wherein said voltage level takes a value symmetric with respect to a median value. 11. The active matrix liquid crystal display device according to claim 9, wherein said buffer circuit includes a bias circuit which can be turned on or off independently. 12. An active matrix liquid crystal panel having a plurality of signal lines and a plurality of scanning lines arranged orthogonal to each other and a thin film transistor near an intersection thereof, and a first semiconductor integrated circuit for driving the scanning lines. A power supply circuit that is formed on the semiconductor chip and outputs a plurality of voltage levels, a storage circuit that stores display data, and an analog multiplexer that outputs one of the voltage levels to the signal line according to the display data. A driving method of an active matrix liquid crystal display device comprising: a second semiconductor integrated circuit comprising: a plurality of resistors connected in series; a switch configured to cut off a current flowing through the resistors; A plurality of buffer circuits that current-amplify the voltage level at the connection point of the resistor and output the amplified voltage to the analog multiplexer, It has 示色 number of switching function, a driving method of the active matrix liquid crystal display device characterized by having the ability to turn on or off the buffer circuit and the switch in response to the color depth setting.