JP2005275382A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further reduce power consumption in a display device having an SRAM. <P>SOLUTION: A memory cell in a driving circuit comprises a first inverter I1 where an input terminal and an output terminal are connected to a first node and a second node respectively; a second inverter I2 where an output terminal and an input terminal are connected to the first node and the second node, respectively; a first conductive type first transistor M1 which is connected between a first data line DT and the first node, and has a control terminal connected to a first word line W2; a third inverter I3 where the input terminal is connected to the first word line W2; a second conductive type second transistor M3, which is connected between the first data line DT and the first node and has a control terminal connected to the output terminal of the third inverter I3; a first conductive type third transistor M2, which is connected between a second data line DB and the second node and has a control terminal connected to a second word line W1; and a second conductive type fourth transistor M4, which is connected between the second data line W1 and the second node and has a control terminal connected to a third word line W1B. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device, and more particularly to a technique that is effective when applied to a drive circuit of a liquid crystal display device used in a mobile phone or the like.

A TFT (Thin Film Transistor) type liquid crystal display module having a small liquid crystal panel with a sub-pixel number of about 240 × 320 × 3 in color display is widely used as a display unit of a portable device such as a mobile phone.
Some liquid crystal display modules used as a display unit of a cellular phone or the like include a semiconductor memory (Static Random Access Memory; hereinafter referred to as SRAM) in order to reduce power consumption.
FIG. 27 is a circuit diagram showing one memory cell of a conventional SRAM.
As shown in the figure, one memory cell of a conventional SRAM has a word line (W), a data line (DT, DB), and an N-type MOS transistor (hereinafter simply referred to as NMOS) that constitutes a transfer switch element ( M1, M2) and inverters (I1, I2).
In FIG. 27, node1 and node2 represent internal nodes.
Further, the size of each NMOS (M1, M2) is determined by the level values of the data line DT and the internal node (node1) connected by the MOS (M1, M2), and the data line DB and the internal node (node2), respectively. If they are different, the size of each MOS (M1, M2) is adjusted so that the node on the High level (hereinafter referred to as H level) side always changes to the Low level (hereinafter referred to as L level).
That is, since writing / reading is possible only at the L level, the operation of the SRAM cell of FIG. 27 is as follows.

(1) Write Operation Before the word line W is set to H level, the data lines (DT, DB) are once precharged to the power supply voltage Vcc.
Next, the word line W is set to H level and the NMOSs (M1, M2) are turned on. At this time, since the data lines (DT, DB) are both at the H level, the value of the internal node does not change and the data in the RAM is retained.
Next, only the data line of the SRAM to be written is changed. For example, when “0” is written, if the data line (DT) is set to L level, the internal node (node1) is always set to L level, and “0” is written.
Conversely, when “1” is written, only the data line (DB) is set to L level after precharging. Then, the internal node (node2) always becomes L level, and the internal node (node1) becomes H level by the inverter (I2). As a result, “1” is written in the SRAM.
(2) Read operation Before the word line W is set to the H level, the data lines (DT, DB) are once precharged up to the power supply voltage Vcc.
Next, the word line W is set to the H level, and the NMOSs (M1, M2) are turned on. Then, when the data stored in the memory cell is “0”, only the data line (DT) changes to the L level because the internal node (node1) is at the L level.
On the other hand, when the data stored in the memory cell is “1”, only the data line (DB) changes to the L level because the internal node (node2) is at the L level. As a result, the data read operation of the SRAM can be performed.
Of course, it goes without saying that the transistor size in each inverter is adjusted in order to realize the above-described operation.

As prior art documents related to the invention of the present application, there are the following.
JP 2002-341842 A JP 2002-297105 A JP 2002-318866 A JP 2003-84722 A Japanese Patent Laid-Open No. 11-134866

In the SRAM memory cell described above, when the word line is at the H level and the NMOS (M1, M2) is turned on and the values of the data (DT, DB) are both at the L level, the internal inverter ( The value of I1, I2) is not fixed, and there is a possibility that a through current flows.
Therefore, when performing a write / read operation, it is necessary to precharge the data lines (DT, DB) to the power supply voltage Vcc.
Therefore, extra power for precharging is required, which is a factor that hinders further reduction in power consumption of the liquid crystal display module having the above-described conventional SRAM. In particular, when a portable device including a liquid crystal display module is battery-driven, it is a big problem in extending the usage time.
Here, in order to eliminate the need for precharge, it is necessary to have a configuration capable of writing / reading at H level / L level.
However, H level / L level writing is possible when the NMOS (M1, M2) is turned on, the internal node always follows and changes the value of the data line. The fact that level / L level reading is possible means that when the NMOS (M1, M2) is turned on, the data line always follows the value of the internal node and changes.
For this reason, writing / reading at H level / L level cannot be performed on both the data line DT side and the data DB side.
The present invention has been made in order to solve the above-described problems of the prior art, and an object of the present invention is to provide a technique capable of further reducing power consumption in a display device having an SRAM. There is to do.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

According to an embodiment of the present invention, a driving circuit to which video data is supplied from the outside, a video line to which a video signal output from the driving circuit is supplied, and the video signal is supplied through the video line. A display device having a pixel,
The drive circuit has a memory for storing the video data in a memory cell;
The memory cell of the memory includes a first inverter having an input terminal connected to the first node and an output terminal connected to the second node;
A second inverter having an output terminal connected to the first node and an input terminal connected to the second node;
A first conductivity type first transistor connected between a first data line and the first node and having a control terminal connected to the first word line;
A second transistor of a second conductivity type connected between the first data line and the first node and having a control terminal connected to a third word line;
A third transistor of a first conductivity type connected between a second data line and the second node and having a control terminal connected to the second word line;
A fourth transistor of a second conductivity type is connected between the second data line and the second node, and a control terminal is connected to the fourth word line.
An example of the circuit configuration showing this embodiment is shown in FIG.
According to another embodiment of the present invention, a driving circuit to which video data is supplied from the outside, a video line to which a video signal output from the driving circuit is supplied, and the video signal to be supplied through the video line A display device comprising:
The drive circuit includes a memory for storing the video data in a memory cell;
A DA conversion circuit provided between the memory and the video line;
The memory cell of the memory includes a first inverter having an input terminal connected to the first node and an output terminal connected to the second node;
A second inverter having an output terminal connected to the first node and an input terminal connected to the second node;
A first conductivity type first transistor and a second conductivity type second transistor connected between a first data line and the first node;
A first conductivity type third transistor and a second conductivity type fourth transistor connected between a second data line and the second node;
The first and second transistors are turned on when the video data is written, and turned off when the video data is read.
The third transistor and the fourth transistor are turned off when the video data is written and turned on when the video data is read.
According to still another embodiment of the present invention, a drive circuit to which video data is supplied from the outside, a video line to which a video signal output from the drive circuit is supplied, and the video signal through the video line A display device having supplied pixels,
The drive circuit has a memory for storing the video data in a memory cell;
The memory cell of the memory includes a first inverter having an input terminal connected to the first node and an output terminal connected to the second node;
A second inverter having an output terminal connected to the first node and an input terminal connected to the second node;
A first conductivity type first transistor connected between a first data line and the first node and having a control terminal connected to the first word line;
A third inverter having an input terminal connected to the first word line;
A second conductivity type second transistor connected between the first data line and the first node and having a control terminal connected to an output terminal of the third inverter;
A third transistor of a first conductivity type connected between a second data line and the second node and having a control terminal connected to the second word line;
A fourth inverter whose input terminal is connected to the second word line;
A fourth transistor of a second conductivity type connected between the second data line and the second node and having a control terminal connected to an output terminal of the fourth inverter; is there.
An example of the circuit configuration showing this embodiment is shown in FIG.
According to still another embodiment of the present invention, a driving circuit to which video data is supplied from the outside,
A display device having a video line to which a video signal output from the driving circuit is supplied, and a pixel to which the video signal is supplied via the video line;
The drive circuit has a memory for storing the video data in a memory cell;
The memory cell of the memory includes a first inverter having an input terminal connected to the first node and an output terminal connected to the second node;
A second inverter having an output terminal connected to the first node and an input terminal connected to the second node;
A first conductivity type first transistor connected between a first data line and the first node and having a control terminal connected to the first word line;
A second transistor of a second conductivity type connected between the first data line and the first node and having a control terminal connected to a third word line;
A third transistor of a first conductivity type connected between a second data line and the second node and having a control terminal connected to the second word line;
A third inverter having an input terminal connected to the second word line;
A fourth transistor of a second conductivity type connected between the second data line and the second node and having a control terminal connected to an output terminal of the third inverter; is there.
An example of the circuit configuration showing this embodiment is shown in FIG.
According to still another embodiment of the present invention, a drive circuit to which video data is supplied from the outside, a video line to which a video signal output from the drive circuit is supplied, and the video signal through the video line A display device having supplied pixels,
The drive circuit has a memory for storing the video data in a memory cell;
The memory cell of the memory includes a first inverter having an input terminal connected to the first node and an output terminal connected to the second node;
A second inverter having an output terminal connected to the first node and an input terminal connected to the second node;
A first conductivity type first transistor connected between a first data line and the first node and having a control terminal connected to the first word line;
A third inverter having an input terminal connected to the first word line;
A second conductivity type second transistor connected between the first data line and the first node and having a control terminal connected to an output terminal of the third inverter;
A third transistor of a first conductivity type connected between a second data line and the second node and having a control terminal connected to the second word line;
A fourth transistor of the second conductivity type is connected between the second data line and the second node, and a control terminal is connected to a third word line.
An example circuit configuration showing this embodiment is shown in FIG.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, it is possible to further reduce power consumption in a display device having an SRAM.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
[Example 1]
FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display module according to Embodiment 1 of the present invention.
The liquid crystal panel (PNL) is provided with a plurality of scanning lines (or gate lines) (G1 to G320) and video lines (or drain lines) (S1 to S720) in parallel.
A pixel portion is provided corresponding to a portion where the scanning line (G) and the video line (S) intersect. The plurality of pixel portions are arranged in a matrix, and each pixel portion is provided with a pixel electrode (ITO1) and a thin film transistor (TFT). In FIG. 1, the number of subpixels of the liquid crystal panel (PNL) is 240 × 320 × 3.
A common electrode (also referred to as a counter electrode or a common electrode) (ITO2) is provided so as to face each pixel electrode (ITO1) with the liquid crystal interposed therebetween. Therefore, a liquid crystal capacitor (LC) is formed between each pixel electrode (ITO1) and the common electrode (ITO2).
A liquid crystal panel (PNL) has a predetermined gap between a glass substrate (GLASS) provided with a pixel electrode (ITO1), a thin film transistor (TFT), and a glass substrate (not shown) on which a color filter or the like is formed. The two substrates are bonded together by a seal material provided in a frame shape in the vicinity of the peripheral edge between the two substrates, and the inside of the seal material between the two substrates from the liquid crystal sealing port provided in a part of the seal material. The liquid crystal is sealed and sealed, and a polarizing plate is attached to the outside of both substrates.
Since the present invention is not related to the internal structure of the liquid crystal panel, a detailed description of the internal structure of the liquid crystal panel is omitted. Furthermore, the present invention can be applied to a liquid crystal panel having any structure.

In this embodiment, a drive circuit (DRV) is mounted on a glass substrate (GLASS).
The driving circuit (DRV) includes a controller circuit 100, a source driver 130 for driving the video line (S) of the liquid crystal panel (PNL), a gate driver 140 for driving the scanning line (G) of the liquid crystal panel (PNL), A liquid crystal driving power generation circuit 120 that generates a power supply voltage (for example, a common voltage (Vcom) supplied to the common electrode (IT2) of the liquid crystal panel (PNL)) necessary for displaying an image on the liquid crystal panel (PNL); And a memory circuit (hereinafter referred to as RAM) 150. In FIG. 1, FPC is a flexible wiring board.
Note that FIG. 1 illustrates the case where the drive circuit (DRV) is configured by one semiconductor chip. However, the drive circuit (DRV) includes, for example, a thin film transistor that uses low-temperature polysilicon for a semiconductor layer. And may be formed directly on a glass substrate (GLASS).
Similarly, a part of the circuit of the drive circuit (DRV) may be divided and the drive circuit (DRV) may be configured by a plurality of semiconductor chips. A thin film transistor using low-temperature polysilicon as a layer may be used to form directly on a glass substrate (GLASS).
Further, the drive circuit (DRV) or a part of the drive circuit (DRV) may be formed on the flexible wiring board instead of being mounted on the glass substrate (GLASS).

Display data and a display control signal are input to the controller circuit 100 from a microcomputer on the main body side (hereinafter referred to as MCU) or from a graphic controller or the like.
In FIG. 1, SI is a system interface and is a system in which various control signals and image data are input from an MCU or the like.
DI is a display data interface (RGB interface), and is a system (external data) in which image data formed by an external graphic controller and a data capturing clock are continuously input.
In this display data interface (DI), the image data is sequentially captured in accordance with the capture clock in the same manner as a drain driver used in a conventional personal computer.
The controller circuit 100 controls the display by sending the image data received from the system interface (SI) and the display data interface (DI) to the source driver 130 and the RAM 150.

FIG. 2 is a circuit diagram showing one memory cell of the SRAM inside the RAM 150 of this embodiment.
In the SRAM of this embodiment, in order to separate data writing and data reading, the word line is separated into a writing word line (W2) and a reading word line (W1).
Thus, the data line (DT) becomes a write-only data line, and the data line (DB) becomes a read-only data line.
The NMOS transistor (M1), the P-type MOS transistor (hereinafter simply referred to as PMOS) (M3), and the NMOS (M2) and PMOS (M4) constitute a transfer switching element.
Here, an inverter (I3) is provided between the gate of the PMOS (M3) and the word line (W2). Similarly, between the gate of the PMOS (M4) and the word line (W1), An inverter (I4) is provided.
In the SRAM of this embodiment, precharging of the data line is not necessary.
Hereinafter, the data write / read operation of the SRAM of this embodiment will be described.
(1) Write Operation The word line (W2) is set to H level, the NMOS (M1) and the PMOS (M3) are turned on, and the data line (DT) is changed. For example, when “0” is written, the data line (DT) is set to L level. Then, the internal node (node1) is always at the L level, and “0” is written in the memory cell.
Conversely, when “1” is written, the data line (DT) is set to the H level. Then, the internal node (node1) is always at the H level, and “1” is written in the memory cell.
(2) Read-out operation The word line (W1) is set to the H level, and the NMOS (M2) and the PMOS (M4) are turned on. Then, when the data in the memory cell is “0”, the data line (DB) changes to the H level because the internal node (node2) is at the H level.
Conversely, when the data in the memory cell is “1”, the data (DB) changes to the L level because the internal node (node2) is at the L level. As a result, the data read operation of the SRAM can be performed.

In FIG. 2, an inverter (I3, I4) is added to drive the PMOS (M2, M4). However, as shown in FIGS. 4, 5, and 28, the word line (W1) is used instead of the inverter. Alternatively, a word line (W1B) or a word line (W2B) to which an inverted signal of a signal applied to the word line (W2) is applied is added and applied to the gates of the PMOS (M2, M4). May be.
4 shows a driving circuit to which video data is supplied from the outside, a video line to which a video signal output from the driving circuit is supplied, and a pixel to which the video signal is supplied via the video line. A display device having
The drive circuit has a memory for storing video data in a memory cell. The memory cell of this memory has an input terminal connected to the first node (node1) and an output terminal connected to the second node (node2). A first inverter (I1) connected to the second inverter (I2) having an output terminal connected to the first node (node1) and an input terminal connected to the second node (node2); A first transistor (M1) of a first conductivity type connected between the first data line DT and the first node (node1) and having a control terminal connected to the first word line (W2); A third inverter (I3) whose input terminal is connected to the first word line (W2);
A second transistor of the second conductivity type connected between the first data line (DT) and the first node (node1) and having a control terminal connected to the output terminal of the third inverter (I3). (M3),
A third transistor (M2) of the first conductivity type connected between the second data line (DB) and the second node (node2) and having a control terminal connected to the second word line (W1). When,
A fourth transistor (M4) of the second conductivity type connected between the second data line (W1) and the second node (node2) and having a control terminal connected to the third word line (W1B). The structure is shown.
FIG. 5 illustrates a driving circuit to which video data is supplied from the outside, a video line to which a video signal output from the driving circuit is supplied, and a pixel to which the video signal is supplied via the video line. A display device having
The drive circuit has a memory for storing video data in a memory cell,
The memory cell of the memory includes a first inverter (I1) having an input terminal connected to the first node (node1) and an output terminal connected to the second node (node2);
A second inverter (I2) having an output terminal connected to the first node (node1) and an input terminal connected to the second node (node2);
A first transistor of the first conductivity type (M1) connected between the first data line (DT) and the first node (node1) and having a control terminal connected to the first word line (W2). When,
A second transistor of the second conductivity type (M3) connected between the first data line (DT) and the first node (node1) and having a control terminal connected to the third word line (W2B). When,
A third transistor (M2) of the first conductivity type connected between the second data line (DB) and the second node (node2) and having a control terminal connected to the second word line (W1). When,
A second transistor of the second conductivity type (M4) connected between the second data line (DB) and the second node (node2) and having a control terminal connected to the fourth word line (W1B). It is said to have.
FIG. 28 shows a driving circuit to which video data is supplied from the outside, a video line to which a video signal output from the driving circuit is supplied, and a pixel to which the video signal is supplied via the video line. A display device having
The drive circuit has a memory for storing the video data in a memory cell,
The memory cell of the memory includes a first inverter (I1) having an input terminal connected to the first node (node1) and an output terminal connected to the second node (node2);
A second inverter (I2) having an output terminal connected to the first node (node1) and an input terminal connected to the second node (node2);
A first transistor of the first conductivity type (M1) connected between the first data line (DT) and the first node (node1) and having a control terminal connected to the first word line (W2). When,
A second transistor of the second conductivity type (M3) connected between the first data line (DT) and the first node (node1) and having a control terminal connected to the third word line (W2B). When,
A third transistor (M2) of the first conductivity type connected between the second data line (DB) and the second node (node2) and having a control terminal connected to the second word line (W1). When,
A third inverter (I3) whose input terminal is connected to the second word line (W1);
A fourth transistor (second conductivity type) connected between the second data line (DB) and the second node (node2) and having a control terminal connected to the output terminal of the third inverter (I3) ( M4).
3 to 5 and 28, the inverter (I2) may be changed to a clocked inverter, and the inverter (I2) may be stopped when data is written.
In the case of the circuit configurations shown in FIGS. 3 to 5 and FIG. 28, the load when data is written to the memory cell can be reduced.
For example, when data “1” is written in a memory cell in which data “0” has been stored, it is necessary to change the internal node (node1) from L level to H level.
In this case, in the circuit configuration shown in FIG. 2, it is necessary to invert both the inverter (I1) and the inverter (I2), whereas in the circuit configurations shown in FIGS. 3 to 5 and FIG. 28, the inverter (I1) Since it is sufficient to invert only the data, the load when data is written to the memory cell can be reduced.
More specific circuit configurations of one memory cell shown in FIG. 3 are shown in FIGS.
5A and 5B, the NMOS (M13) and the PMOS (M14) constitute the inverter (I1) shown in FIG. 3, and the NMOS (M11, M15) and the PMOS (M12, M16). Constitutes the clocked inverter (I2) shown in FIG.
5A and 5B, when the word line (W2) is at the H level, the NMOS (M15) and the PMOS (M16) are off, and when the word line (W2) is at the L level, the NMOS ( Since M15) and PMOS (M16) are turned on, the clocked inverter (I2) can be stopped when writing data.

When memory cells that do not require precharge of this embodiment are used, all the memory cells connected to the same word line are in a write / read state. However, in the write state, the data line (DT) must be connected. Since data is written, it is necessary to input data to all the memory cells connected to the same word line, unlike the case of using the conventional memory cell shown in FIG.
For this reason, when data is written, in order to hold data of a memory cell that is not connected to the same word line (W1, W2), the data is once read from the memory cell and then again. An operation to write back the read data is required.
FIG. 6 shows an example of the configuration.
6, 151 is a memory cell shown in FIG. 2, 152 is an X direction control circuit, 153 is a Y direction control circuit, 154 is a multiplexer, 155 is a write circuit, and 156 and 157 are read circuits.
When data is written, the read circuit 156 once reads data from the memory cells connected to the same word line (W2).
Thereafter, the multiplexer 154 is controlled by the X direction control circuit 152 to select whether to write back or rewrite data, and the write circuit 155 writes data to the selected memory cell.
With the above-described operation, it is possible to hold data of memory cells that are connected to the same word line (W2) and are not written with data when data is written.
By using the drive circuit incorporating the SRAM of this embodiment, the power consumption of the liquid crystal display module can be reduced.

FIG. 7 is a block diagram showing a schematic configuration of an example of the controller circuit 100, the source driver 130, and the RAM 150 shown in FIG.
In the configuration shown in FIG. 7, the controller circuit 100 includes an SRAM control circuit 1, an arithmetic circuit 6 for external data and SRAM data, an oscillator 10, and a display timing generation circuit 11.
The source driver 130 includes an SRAM data parallel-serial conversion shift register (1) 4, an SRAM data selector circuit 5, a display data serial-parallel conversion shift register (2) 7, and a display data latch. A circuit (1) 8, a selector circuit 9 for operation data and SRAM data, a display data latch circuit (2) 12, a display data latch circuit (3) 13, a level shift circuit 14 and a DA converter circuit (gray scale) A voltage decoding circuit) 15, an output circuit (current amplification amplifier circuit) 16, and a gradation voltage generation circuit 17.
Further, the RAM 150 includes an SRAM 2 and an SRAM data latch circuit 3.
The configuration shown in FIG. 7 is characterized by having two shift registers (4, 7), an SRAM 2 for holding image data, and an arithmetic circuit 6 for external data and SRAM data.

In the configuration shown in FIG. 7, image data from SI (system interface) is input to the SRAM control circuit 1 and sent to the SRAM 2. The data stored in the SRAM 2 is latched by the SRAM data latch circuit 3 and then used to display an image on the liquid crystal panel (PNL).
Image data from DI (RGB interface) is input to the SRAM control circuit 1 or the arithmetic circuit 6 for external data and SRAM data and sent to the SRAM 2 or the display data latch circuit (1) 8.
The data sent to the SRAM 2 can be stored up to the RAM capacity and used as a frame memory for still images and moving images.
The RAM capacity changes depending on the number of pixels of the liquid crystal panel (PNL) and the number of display colors. In some cases, the total number of pixels and all the gradations are provided, and in addition, in order to superimpose a clock display of a mobile phone on a display image, there are cases where the number exceeds the number of pixels of the liquid crystal panel (PNL).
On the other hand, the RAM capacity may have only information on the standby screen of the mobile phone (only clock display etc.).
For example, QVGA does not have a RAM capacity for all 320 lines and has only 96 lines, or the display color is limited to only 8 colors (1 bit for each of RGB). Here, the reason for having only the image information of the standby screen is to reduce the power consumption.
By using the SRAM 2, a still image can be displayed on the liquid crystal panel (PNL) without driving an external bus. A state in which the display line is limited and the display color is limited during standby is called partial display.

The external data sent to the display data latch circuit (1) 8 is serial-parallel converted by the display data serial-parallel conversion shift register (2) 7, and the display data latch circuit (1) 8 receives the liquid crystal panel. (PNL) is sequentially stored as display data for one scanning line and becomes video data for one scanning line.
In the configuration shown in FIG. 7, since the data stored in the SRAM 2 and the external data are independent, it is possible to perform arithmetic processing.
Here, the calculation mainly includes superposition of data stored in the SRAM 2 and external data. In general, there is one that can arbitrarily set the transmittance of each data.
Regarding the calculation, there are the following two methods (a) and (b).
(A) Since the external data is serial data that is continuously input, the stored SRAM data is subjected to parallel-serial conversion to perform continuous calculation.
(B) Serial-parallel conversion of external data is performed and one scan line is collectively calculated with SRAM data.
The configuration shown in FIG. 7 corresponds to the case of (a). In this method, since only one arithmetic circuit for SRAM data and external data is required, an arithmetic circuit for SRAM data and external data is required for the number of video line outputs. Can be small.

In order to realize the method (a) described above, a shift register (1) 4 for parallel-serial conversion of SRAM data, a selector circuit 5 for SRAM data, and an arithmetic circuit 6 for external data and SRAM data are required. Become. These have a smaller area than arranging an arithmetic circuit for each video line.
The shift register (1) 4 is a shift register for parallel-serial conversion of the SRAM data. The selected SRAM data is sent to the arithmetic circuit 6 by the selector circuit 5, and the arithmetic is executed.
The serial data after the calculation is sent to the display data latch circuit (1) 8, serial-parallel converted by the serial-parallel conversion shift register (2) 7 of the display data, and then sent to the display data latch circuit (1) 8. Are sequentially stored as display data for one scanning line of the liquid crystal panel (PNL), and become video data for one scanning line.
One of the display data latched by the display data latch circuit (1) 8 (external data, or data after calculation of external data and SRAM data, or RAM data) is selected by the selector circuit 9, and the display data latch circuit (2) 12 and the display data latch circuit (3) 13 holds the data as one scan line.
Note that the display data latch circuit (3) 13 may not be particularly necessary depending on the timing of a signal input from DI (RGB interface).

The selector circuit 9 for operation data and SRAM data, the display data latch circuit (2) 12, and the display data latch circuit (3) 13 operate based on the display timing clock (CL1) generated by the display timing generation circuit 11.
When there is no synchronization signal (dot clock) input from DI (RGB interface), it is necessary to generate a timing clock for synchronization by the internal oscillator 10.
This applies to systems using only SI (system interface), or partial display of low power consumption display.
The video data latched in the display data latch circuit (3) 13 is converted into an analog gradation voltage by a DA conversion circuit (gradation voltage decoding circuit) 15 after the voltage level is converted by the level shift circuit 14. .
The gradation voltage is current-amplified by an output circuit (current amplification amplifier circuit) 16 and is output to each video line (S1 to S720).
Here, the gradation voltage of 64 gradations (V0 to V63) generated by the gradation voltage generation circuit 17 is input to the DA conversion circuit (gradation voltage decoding circuit) 15.

In the configuration shown in FIG. 7, the flow of image data is as follows.
(1) Image data from DI (RGB interface) Mode A; not via RAM External data and SRAM data arithmetic circuit 6 → display data latch circuit (1) 8 → arithmetic data and RAM data selector circuit 9 (normally display)
Mode B; via RAM Same as mode C below (normal display)
(2) Image data from SI (system interface) Mode C: No calculation SRAM control circuit 1 → SRAM 2 → SRAM data latch circuit 3 → Selection circuit 9 for calculation data and SRAM data (normal display or partial display)
Mode D: With calculation SRAM control circuit 1 → SRAM 2 → SRAM data latch circuit 3 → SRAM data selector circuit 5 → External data and SRAM data operation circuit 6 → Display data latch circuit (1) 8 → Operation data and SRAM Data selector circuit 9 (normal display (overlapping))
The display timing clock (CL1) is generated by the synchronization clock (DOTCLK) included in DI (RGB interface) when DI (RGB interface) is used, and is generated by the oscillator 10 when DI (RGB interface) is not used. Clock is used.

Hereinafter, each mode will be described.
(1) Mode A
FIG. 8A shows the flow of image data in mode A, and shows the flow up to the display data latch circuit (2) 12 in FIG.
FIG. 8B is a diagram schematically showing an image displayed on the liquid crystal panel (PNL) in mode A. Note that FIG. 8B is a drawing that displays 260,000 colors assuming 6 bits for each of RGB, but the number of colors and the number of pixels are not limited to this.
The flow of image data in mode A is in the order of DI (RGB interface) → arithmetic circuit 6 → display data latch circuit (1) 8 → selector circuit 9 → display data latch circuit (2) 12.
As described above, in the mode A, the SRAM 2, the SRAM data latch circuit 3, the shift register (1) 4, and the selector circuit 5 are not used, so that the operation of these circuits can be stopped.
Furthermore, since the SRAM 2 is not used for the arithmetic circuit 6 and the selector circuit 9, data can be passed through.
In the case of DI (RGB interface), the synchronization clock is also input at the same time, so the oscillator 10 need not be used.
However, since it takes several ms until the operation of the oscillator 10 is stabilized, the oscillator 10 may be kept operating in order to cope with a quick state change to the mode C using the oscillator 10. Is possible.
Note that when generating a boost clock used in the liquid crystal drive power generation circuit 120 based on the clock generated by the oscillator 10, the oscillator 10 needs to be kept operating. This is the same in each mode described below.

(2) Mode B
FIG. 9A shows the flow of image data in mode B, and shows the flow up to the display data latch circuit (2) 12 in FIG.
FIG. 9B is a diagram schematically illustrating an image displayed on the liquid crystal panel (PNL) in mode B. In FIG. 9B, 260,000 colors are displayed assuming 6 bits of RGB, but the number of colors and the number of pixels are not limited to this.
The flow of image data in mode B is in the order of DI (RGB interface) → SRAM control circuit 1 → SRAM 2 → SRAM data latch circuit 3 → selector circuit 9 → display data latch circuit (2) 12.
Thus, in mode B, the shift register (1) 4, the selector circuit 5, the arithmetic circuit 6, the shift register (2) 7, and the display data latch circuit (1) 8 are not used. It is possible to stop.
Furthermore, since the SRAM 2 is not used for the selector circuit 9, data can be passed through.
In the case of DI (RGB interface), the synchronization clock is also input at the same time, so the oscillator 10 need not be used.
However, since it takes several ms until the operation of the oscillator 10 is stabilized, the oscillator 10 may be kept operating in order to cope with a quick state change to the mode C using the oscillator 10. Is possible.

(3) Mode C
FIG. 10A shows the flow of image data in mode C, and shows the flow up to the display data latch circuit (2) 12 in FIG.
The mode C is the same as the mode B shown in FIG. 9A except that the image data input to the SRAM control circuit 1 is input from SI (system interface).
However, in mode C, since the synchronous clock is not input from SI (system interface), the clock generated by the oscillator 10 is used as the display timing clock (CL1).
FIG. 10B is a diagram schematically illustrating an image displayed on the liquid crystal panel (PNL) in the normal display state in mode C. In FIG. 10B, 260,000 colors are displayed assuming 6 bits for each of RGB, but the number of colors and the number of pixels are not limited to this.
FIG. 10C is a diagram schematically showing an image displayed on the liquid crystal panel (PNL) in the partial display state in mode C. In addition, the areas a and b in FIG. 10C indicate eight-color display locations, and the other areas indicate white or black non-display areas. FIG. 10C shows the case where the SRAM data has 8 colors. However, the number of colors and the number of partial display lines (a and b in FIG. 10C) are not limited thereto. Absent.

(4) Mode D
FIG. 11A shows the flow of image data in mode D, and shows the flow up to the display data latch circuit (2) 12 in FIG.
FIG. 11B is a diagram schematically showing an image displayed on the liquid crystal panel (PNL) in mode D. Note that a and b in FIG. 11B indicate an overlay display area of 8 colors + 260,000 colors, and the other areas indicate display areas of 260,000 colors. In FIG. 11 (b), 260,000 colors are shown assuming 6 bits for each of RGB, but the number of colors and the number of pixels are not limited to this. Similarly, although the case where the SRAM data is eight colors is illustrated, the number of colors and the superimposed display lines (a and b in FIG. 11B) are not limited to this.
There are two systems of image data flow in mode D. One system is SI (system interface) → SRAM control circuit 1 → SRAM 2 → SRAM data latch circuit 3 → SRAM data selector circuit 5 → arithmetic circuit 6 → display data. Latch circuit (1) 8 → selector circuit 9 → display data latch circuit (2) 12 in this order, and the other system is DI (RGB interface) → arithmetic circuit 6 → display data latch circuit (1) 8 → selector circuit. 9 → display data latch circuit (2) 12 in this order.
In mode D, since the synchronous clock is also input simultaneously from DI (RGB interface), the oscillator 10 does not need to be used in particular.
However, since it takes several ms until the operation of the oscillator 10 is stabilized, the oscillator 10 may be kept operating in order to cope with a quick state change to the mode C using the oscillator 10. Is possible.
Further, by performing calculation in the arithmetic circuit 6, all of the superimposed display line portions (a and b in FIG. 11B) are changed to 8 colors, a part of 260,000 colors are displayed, and the others are displayed in 8 colors or SRAM. Data and external data input from DI (RGB interface) can be displayed in a 50% watermark.

FIG. 12 is a block diagram showing a schematic configuration of another example of the controller circuit, the source driver, and the SRAM shown in FIG.
The configuration shown in FIG. 12 is characterized by having an arithmetic circuit 6 for external data and SRAM data for each bit of video data. The external data is serial-parallel converted, and is combined for one scanning line. The operation with the SRAM data is performed.
The difference from the block diagram shown in FIG. 7 is that the SRAM data parallel-serial conversion shift register (1) 4 and the SRAM data selector circuit 5 are omitted, and the arithmetic data and SRAM data selector circuit 9 is omitted. In addition, an arithmetic circuit 6 for external data and SRAM data is provided for each video data bit.
As shown in FIG. 12, providing the arithmetic circuit 6 for each video bit increases the circuit scale and increases the chip size, but it is not necessary to match the external data transfer cycle. A margin is born. The operation may be about a cycle for each scan line output.
Furthermore, in the configuration shown in FIG. 12, when the process shrinks and the area of the digital circuit can be reduced, the influence of the increase in the circuit scale of this configuration is reduced as a whole. Can afford.

In the configuration shown in FIG. 12, the flow of image data is as follows.
(1) Image data from DI (RGB interface) Mode A; not via RAM Display data latch circuit (1) 8 → External data and SRAM data arithmetic circuit 6 → Calculation data and RAM data selector circuit 9
Mode B; via RAM Same as mode C below (2) Image data from SI (system interface) Mode C; no computation SRAM control circuit 1 → SRAM 2 → SRAM data latch circuit 3 → calculation data and SRAM Data selector circuit 9
Mode D: With calculation SRAM control circuit 1 → SRAM 2 → SRAM data latch circuit 3 → External data and SRAM data operation circuit 6 → Operation data and SRAM data selector circuit 9

Hereinafter, each mode will be described.
(1) Mode A
FIG. 13A shows the flow of image data in mode A, and shows the flow up to the display data latch circuit (2) 12 in FIG.
FIG. 13B is a diagram schematically showing an image displayed on the liquid crystal panel (PNL) in mode A. In FIG. 13B, 260,000 colors are displayed assuming 6 bits for each of RGB, but the number of colors and the number of pixels are not limited to this.
The flow of image data in mode A is in the order of DI (RGB interface) → display data latch circuit (1) 8 → (arithmetic circuit 6 + selector circuit 9) → display data latch circuit (2) 12.
Thus, in mode A, since the SRAM 2 and the SRAM data latch circuit 3 are not used, the operation of these circuits can be stopped.
Further, regarding the arithmetic circuit 6 and the selector circuit 9, since the SRAM 2 is not used, it is possible to let data pass through.
In the case of DI (RGB interface), the synchronization clock is also input at the same time, so the oscillator 10 need not be used.
However, since it takes several ms until the operation of the oscillator 10 is stabilized, the oscillator 10 may be kept operating in order to cope with a quick state change to the mode C using the oscillator 10. Is possible.

(2) Mode B
FIG. 14A shows the flow of image data in mode B, and shows the flow up to the display data latch circuit (2) 12 in FIG.
FIG. 14B is a diagram schematically showing an image displayed on the liquid crystal panel (PNL) in mode A. In FIG. 14B, 260,000 colors are displayed assuming 6 bits for each RGB, but the number of colors and the number of pixels are not limited to this.
The flow of image data in mode B is in the order of DI (RGB interface) → SRAM control circuit 1 → SRAM 2 → SRAM data latch circuit 3 → (arithmetic circuit 6 + selector circuit 9) → display data latch circuit (2) 12.
As described above, in the mode B, the shift register (2) 7 and the display data latch circuit (1) 8 are not used, so that the operation of these circuits can be stopped.
Further, regarding the arithmetic circuit 6 and the selector circuit 9, since the SRAM 2 is not used, it is possible to let data pass through.
In the case of DI (RGB interface), the synchronization clock is also input at the same time, so the oscillator 10 need not be used.
However, since it takes several ms until the operation of the oscillator 10 is stabilized, the oscillator 10 may be kept operating in order to cope with a quick state change to the mode C using the oscillator 10. Is possible.

(3) Mode C
FIG. 15A shows the flow of image data in mode B, and shows the flow up to the display data latch circuit (2) 12 in FIG.
The mode C is the same as the mode B shown in FIG. 14A except that the image data input to the SRAM control circuit 1 is input from SI (system interface).
However, in mode C, since the synchronous clock is not input from SI (system interface), the clock generated by the oscillator 10 is used as the display timing clock (CL1).
FIG. 15B is a diagram schematically showing an image displayed on the liquid crystal panel (PNL) in the normal display state in mode C. Note that the areas a and b in FIG. 15C indicate 8-color display locations, and the other areas indicate white or black non-display areas. Further, in FIG. 15B, 260,000 colors are illustrated assuming 6 bits for each of RGB, but the number of colors and the number of pixels are not limited to this.
FIG. 15C is a diagram schematically illustrating an image displayed on the liquid crystal panel (PNL) in the partial display state in mode C. In FIG. 15C, the case where the SRAM data is 8 colors is illustrated, but the number of colors and the number of partial display lines (a and b in FIG. 15C) are not limited thereto. Absent.

(4) Mode D
FIG. 16A shows the flow of image data in mode D, and shows the flow up to the display data latch circuit (2) 12 in FIG.
FIG. 16B is a diagram schematically showing an image displayed on the liquid crystal panel (PNL) in mode D. Note that a and b in FIG. 11B indicate an overlay display area of 8 colors + 260,000 colors, and the other areas indicate display areas of 260,000 colors. In addition, in FIG. 16B, 260,000 colors are illustrated assuming 6 bits for each of RGB, but the number of colors and the number of pixels are not limited to this. Similarly, although the case where the SRAM data is eight colors is illustrated, the number of colors and the superimposed display lines (a and b in FIG. 16B) are not limited to this.
The flow of image data in mode D has two systems, and one system is SI (system interface) → SRAM control circuit 1 → SRAM 2 → SRAM data latch circuit 3 → (arithmetic circuit 6 + selector circuit 9) → display data latch circuit. (2) The order is 12, and the other system is the order of DI (RGB interface) → display data latch circuit (1) 8 → (arithmetic circuit 6 + selector circuit 9) → display data latch circuit (2) 12. .
In mode D, since the synchronous clock is also input simultaneously from DI (RGB interface), the oscillator 10 does not need to be used in particular.
However, since it takes several ms until the operation of the oscillator 10 is stabilized, the oscillator 10 may be kept operating in order to cope with a quick state change to the mode C using the oscillator 10. Is possible.
Further, by performing calculation in the arithmetic circuit 6, all of the superimposed display line portions (a and b in FIG. 11B) are changed to 8 colors, a part of 260,000 colors are displayed, and the others are displayed in 8 colors or SRAM. Data and external data input from DI (RGB interface) can be displayed in a 50% watermark.

FIG. 17 is a circuit diagram showing an example of the output circuit (current amplification amplifier circuit) 16 shown in FIG. 7 or FIG.
As described above, the partial display is a total of eight colors (= 2 × 2 × 2) for each of R, G, and B, and displays only a clock or the like, and further reduces the number of scanning lines to be used. It is a display method.
The circuit shown in FIG. 17 further reduces the power consumption during the partial display. Therefore, a clocked inverter (INV) is connected in parallel to the operational amplifier (AMP) of the output circuit 16 to display the partial display. Sometimes, the operational amplifier of the output circuit 16 is stopped to reduce power consumption.
The inverter (INV) is supplied with the maximum gradation voltage (V0) and the minimum gradation voltage (V63) as the power supply voltage, and receives level-shifted data (for example, D5T in FIG. 17).
The operation of the circuit shown in FIG. 17 will be described below.
(1) During normal display, the operational amplifier (AMP) of the output circuit 16 is set in an operating state.
Further, the clock (T) is set to H level and the clock (B) is set to L level to stop the operation of the inverter (INV) (the output is in a high impedance state).
Here, the H level of the power supply voltage is higher than the maximum gradation voltage (V0), and the L level (GND) of the power supply voltage is lower than the minimum gradation voltage (V63). The voltage level of B) may be a power supply level.

(2) During partial display, the operational amplifier (AMP) of the output circuit 16 is stopped (the output is in a high impedance state and a direct current (DC) path cut state).
Further, the clock (T) is set to L level, the clock (B) is set to H level, and the inverter (INV) is set in an operating state.
Level-shifted data (for example, D5T) is input to the inverter (INV). Here, D5T is data in which a gradation voltage of V63 (low) is selected when “1”, and data in which a gradation voltage of V0 (high) is selected when “0”. The data may be one of D0 to D5.
As a result, a gradation voltage of V63 (low) or a gradation voltage of V0 (high) is output from the output of the inverter (INV).
As a result, the operational amplifier (AMP) of the output circuit 16 can be stopped at the time of partial display, and the gradation voltage of V0 or the gradation voltage of V63 can be output, so that the low power consumption is greatly reduced at the time of partial display. It becomes possible to do.
When D5B is used as video data to be input to the inverter (INV), a logically correct gradation voltage can be output by connecting the inverters (INV) in two stages in series.
That is, the inverter (INV) may have n (n ≧ 2) stages. However, in order to reduce the through current between the voltages (V0, V63) applied as the power supply voltage of the inverter (INV), the minimum one stage is preferable.
Note that although FIG. 17 illustrates the case where the video data is 6 bits, the video data may be 8 bits, and input data may be one of D0 to D7.

In FIG. 17, D5T is the only data required for partial display. Therefore, at the time of partial, level shift operation other than the D5 bit is not necessary in the level shift circuit 14 shown in FIG.
In general, a level shift circuit has a large through current, so that if it can be stopped, an effect of low power consumption can be expected.
FIG. 18 is a diagram illustrating an example of a circuit configuration when the level shift operation of bits other than D5 is stopped during partial display.
In the circuit shown in FIG. 18, the voltage of the control line A is set to L level (GND) at the time of partial setting.
As a result, the output of the NAND circuit (NAND) is fixed to the H level, the operation of the D0 to D4 bits is stopped, and the power consumption can be further reduced during partial display.

FIG. 19 is a circuit diagram showing another example of the output circuit (current amplification amplifier circuit) 16 shown in FIG. 7 or FIG.
In FIG. 19, the difference from FIG. 17 is that the decoder output (analog voltage) of the DA conversion circuit (grayscale voltage decoding circuit) 15 is used for the input of the inverter (INV).
This configuration is effective when video data cannot be routed to the output circuit 16 due to chip layout.
At the time of partial display, the decoder output of the DA conversion circuit 15 needs to output the gradation voltage of V0, the gradation voltage of V63, or the gradation voltage selected as it is.
Therefore, in the circuit shown in FIG. 18, the inverters (INV) need to be cascaded in an even number of stages so that the output is not logically inverted.

In the circuit shown in FIG. 17 or FIG. 19, the input voltage of the inverter (INV) is changed when the L level clock (T) and the H level clock (B) are input to the inverter (INV). In some cases, a through current flows.
Even in that case, there is no problem in the display of the liquid crystal panel (PNL), but there is a concern about an increase in power consumption. In order to reduce this through current, it is necessary to stop the operation of the inverter (INV) when the input voltage of the inverter (INV) changes.
An example of the operation timing in that case is shown in FIG.
In FIG. 20, GATE CL is a clock for ON / OFF of the gate line (G) of the liquid crystal panel (PNL), and is turned on at H level and turned off at L level.
LINE CL is a latch clock of the display data latch circuit (3) 13 in FIGS. 7 and 12. In FIG. 20, the data of the next scanning line is latched at the falling (P) point (data change). Timing).
If the inverter (INV) is stopped (clock (T) is at H level and clock (B) is at L level) at the timing when data changes, the through current does not flow.
Therefore, the trailing edge (P) may be positioned in the YZ period shown in FIG.
Note that the inverter (INV) output is in a high-impedance state during the Y-Z period, and during this period, the liquid crystal is not driven, but if the liquid crystal can be driven sufficiently in the time after the high-impedance state, No problem.
In addition, if the point Y comes earlier than X in FIG. 20, the output of the inverter (INV) is in a high impedance state at the end of the previous stage of writing. In addition, there is no problem if the level charged in the liquid crystal is not long enough to escape due to a minute leak.
As described above, by stopping the inverter (INV) during the change time of the data input to the inverter (INV), it is possible to eliminate the through current and further reduce power consumption. It becomes.

FIG. 21 is a diagram illustrating an example of the gradation voltage generation circuit 17 illustrated in FIGS. 7 and 12.
In general, the gradation voltage generation circuit 17 shown in FIGS. 7 and 12 divides a voltage (Vref in FIG. 21) generated in the liquid crystal drive power generation circuit 120 by a resistance voltage dividing circuit (Ra), and outputs a plurality of voltages. Grayscale reference voltages (five grayscale reference voltages in FIG. 21) are generated, and the grayscale reference voltages are divided by a resistance voltage dividing circuit (Rb) to generate a plurality of grayscale voltages (FIG. 21). In this case, a gradation voltage of 64 gradations) is generated.
In this case, the plurality of gradation reference voltages are amplified by an amplifier circuit (or buffer circuit).
In the partial display shown in FIG. 10C, it is necessary to display black or white on lines other than the partial display line.
Here, when displaying only black or white, the gradation voltage output from the source driver 130 to the video line (S) needs only the upper and lower binary values.
Therefore, as shown in FIG. 21, when the gray scale reference voltage is supplied via the amplifier circuit, the V0 gray scale voltage and the V63 gray scale amplifier circuit (FIG. The operation of the amplifier circuits (AMPA to AMPe) other than AMP0 and AMP63 of 21 can be stopped, and the power consumption can be reduced.
In this way, at the time of partial display, by stopping the amplifier circuit that amplifies the gradation reference voltage output from the gradation voltage generation circuit 47, it is possible to further reduce power consumption.

FIG. 22 is a circuit diagram showing a conventional oscillator.
In the oscillator 10 shown in FIG. 22, five inverters (I11 to I15) are connected in series via a resistance element (R), and a capacitive element (between the inverter (I11) and the inverter (I12)). C2) is connected, and the power supply voltage (Vcc) is supplied to the inverter (I11) via the capacitor (C1).
In the oscillator 10 shown in FIG. 22, the oscillation frequency can be adjusted by changing the resistance element R and the capacitance elements (C1, C2).
However, in the conventional oscillator 10, a normal resistance element (so-called external resistance element) is used as the resistance element (R) in order to stabilize the oscillation frequency.
That is, since an accurate resistance device cannot be formed with a normal CMOS semiconductor or the like, the resistance element (R) is not built in the semiconductor chip constituting the drive circuit (DRV). This is the same even when formed on a glass substrate using a polysilicon TFT or the like.
For normal full gradation display, a clock input from DI (RGB interface) is used. Therefore, in this embodiment, when the SRAM data is used only for partial display, the oscillator 10 shown in FIGS. 7 and 12 is used only for partial display.
Since the partial display has only a small number of colors and a simple display such as a clock, even if there is a certain change in the AC cycle of the liquid crystal, it is difficult to display as a disturbance in image quality.
Therefore, since there is a margin in the accuracy of the resistance element used in the oscillator 10, it is possible to reduce the number of liquid crystal display module components by incorporating the resistance element in the semiconductor chip.
Further, by incorporating the resistance element in the semiconductor chip, it becomes possible to make some resistance values variable by controlling the MCU (that is, in software). That is, the adjustment can be made according to the image quality and current consumption of the liquid crystal display module.

FIG. 23 is a block diagram illustrating a schematic configuration of the oscillator 10 according to the present embodiment.
The oscillator 10 shown in FIG. 23 uses a resistance array (R Decoder) built in a semiconductor chip as a resistance element. Furthermore, terminals (PIN1, PIN2) are provided so that an external resistance element (R) can be used.
24 is a circuit diagram showing a configuration of the resistance array (R Decoder) shown in FIG.
When the external resistance element (R) is used, the transfer gate circuit (MZ1) is turned on and the transfer gate circuit (MZ2) is turned off. The current loop of the oscillator 10 at this time is indicated by OSCR = 0 in FIG.
Further, when the resistor array (R Decoder) is used, the transfer gate circuit (MZ1) is turned off and the transfer gate circuit (MZ2) is turned on.
In the resistor array (R Decoder), a plurality of internal resistors are connected in series, and the resistance value can be varied by selecting the internal resistor in one of the transfer gate circuit (MZT) groups.
24, the current loop of the oscillator 10 when 450 kΩ is selected as the resistor array (R Decoder) is OSCR = 2 in FIG. 24, and the oscillator 10 when 175 kΩ is selected as the resistor array (R Decoder). 24 is shown as OSCR = 10, and as a resistor array (R Decoder), the current loop of the oscillator 10 when 50 kΩ is selected is shown as OSCR = 15 in FIG.

FIG. 25 is a diagram for explaining the display timing clock (CL1) generated by the display timing generation circuit 11 and the boosting clock generated by the oscillator 10 in this embodiment.
As shown in FIG. 25A, the display timing generation circuit 11 generates a display timing clock (CL1) based on a horizontal synchronization signal (HSYNC) input from DI (RGB interface) and a dot clock (DOTCLK). Generate.
The display timing clock (CL1) is a signal having a constant cycle (T1 shown in FIG. 25B).
The boost clock generation circuit 20 divides the clock (OSC1) generated by the oscillator 10 to generate a boost clock (DCCLK).
The period of the boost clock (DCCLK) (T2 shown in FIG. 25B) can be changed in units of one period of the clock (OSC1) generated by the oscillator 10.
In the circuit shown in FIG. 25, the display timing clock (CL1) and the boost clock (DCCLK) are generated inside the same semiconductor chip. Asynchronous.
For this reason, there is a case where image quality deterioration is caused in an image displayed on the liquid crystal panel (PNL) due to interference between the display timing clock (CL1) and the boost clock (DCCLK).

FIG. 26 is a diagram for explaining the display timing clock (CL1) generated by the display timing generation circuit 11 and the boosting clock generated by the oscillator in a modification of the present embodiment.
26 prevents the image displayed on the liquid crystal panel (PNL) from deteriorating due to the interference between the display timing clock (CL1) and the boost clock (DCCLK). .
In the circuit shown in FIG. 26, when the display timing clock (CL1) generated by the display timing generation circuit 11 is used as the display control signal, the boost clock generation circuit 20 is input via the switch (SW). The boost clock (DCCLK) is generated based on the dot clock (DOTCLK).
As a result, the display timing clock (CL1) and the boost clock (DCCLK) are synchronized, so that it is possible to prevent the image displayed on the liquid crystal panel (PNL) from deteriorating in image quality.
In this case, the boost clock generation circuit 20 generates the following two modes of the boost clock (DCCLK).

(1) Mode 1
Boosting clock (DCCLK) whose cycle is the same as that of the display timing clock (CL1) and whose duty ratio as the charging / discharging ratio of the liquid crystal drive power generation circuit 120 can be varied (see T3 shown in FIG. 26B) )
(2) Mode 2
A step-up clock (DCCLK) in which the cycle is variable in synchronization with the dot clock (DOTCLK) and the duty ratio as the charge / discharge ratio of the liquid crystal drive power generation circuit 120 is fixed to 50% (see FIG. 26B). T4 shown).
However, in this mode 2, the boosting clock (DCCLK) is asynchronous with the display timing clock (CL1).
In the above description, the embodiment in which the present invention is applied to the TFT type liquid crystal display module has been described. However, the present invention is not limited to this, and the present invention is not limited to the STN type liquid crystal display module. The present invention is also applicable to an EL display device having an organic EL element.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

It is a block diagram which shows schematic structure of the liquid crystal display module of the Example of this invention. It is a circuit diagram which shows one memory cell of RAM of the Example of this invention. It is a circuit diagram which shows 1 memory cell of the modification of RAM of the Example of this invention. It is a circuit diagram which shows 1 memory cell of the modification of RAM of the Example of this invention. It is a circuit diagram which shows 1 memory cell of the modification of RAM of the Example of this invention. FIG. 4 is a circuit diagram showing an example of a more specific circuit configuration of one memory cell shown in FIG. 3. FIG. 4 is a circuit diagram showing another example of a more specific circuit configuration of one memory cell shown in FIG. 3. It is a block diagram which shows the internal structure of RAM of the Example of this invention. FIG. 2 is a block diagram illustrating a schematic configuration of an example of a controller circuit, a source driver, and an SRAM illustrated in FIG. 1. FIG. 8 is a diagram showing a flow of image data in mode A and a display image on a liquid crystal panel in the configuration shown in FIG. 7. FIG. 8 is a diagram illustrating a flow of image data in mode B and a display image on the liquid crystal panel in the configuration illustrated in FIG. 7. FIG. 8 is a diagram illustrating a flow of image data in mode C and a display image on the liquid crystal panel in the configuration illustrated in FIG. 7. FIG. 8 is a diagram showing a flow of image data in mode D and a display image on the liquid crystal panel in the configuration shown in FIG. 7. FIG. 3 is a block diagram illustrating a schematic configuration of another example of the controller circuit, the source driver, and the SRAM illustrated in FIG. 1. FIG. 13 is a diagram showing a flow of image data in mode A and a display image on a liquid crystal panel in the configuration shown in FIG. 12. FIG. 13 is a diagram showing a flow of image data in mode B and a display image on a liquid crystal panel in the configuration shown in FIG. 12. FIG. 13 is a diagram showing a flow of image data in mode C and a display image on a liquid crystal panel in the configuration shown in FIG. 12. FIG. 13 is a diagram showing a flow of image data in mode D and a display image on a liquid crystal panel in the configuration shown in FIG. 12. FIG. 13 is a circuit diagram showing an example of the output circuit (current amplification amplifier circuit) 16 shown in FIG. 7 or FIG. 12. It is a figure which shows an example of a circuit structure in the case of stopping the level shift operation | movement of bits other than D5 at the time of a partial display. FIG. 13 is a circuit diagram showing another example of the output circuit (current amplification amplifier circuit) 16 shown in FIG. 7 or FIG. 12. FIG. 20 is a timing chart for stopping the operation of the inverter (INV) when the input voltage of the inverter (INV) changes in the circuits shown in FIGS. 17 and 19. It is a figure which shows an example of the gradation voltage generation circuit shown in FIG. 7, FIG. It is a circuit diagram which shows the conventional oscillator. It is a block diagram which shows schematic structure of the oscillator of the Example of this invention. FIG. 24 is a circuit diagram showing a configuration of a resistance array (R Decoder) shown in FIG. 23. FIG. 6 is a diagram for explaining a display timing clock (CL1) generated by a display timing generation circuit and a boost clock generated by an oscillator in the embodiment of the present invention. It is a figure for demonstrating the display timing clock (CL1) produced | generated by the display timing generation circuit in the modification of the Example of this invention, and the pressure | voltage rise clock produced | generated by an oscillator. It is a circuit diagram which shows one memory cell of the conventional SRAM. It is a circuit diagram which shows 1 memory cell of the modification of RAM of the Example of this invention.

Explanation of symbols

1 SRAM control circuit 2 Semiconductor Random Access Memory (SRAM)
3 SRAM data latch circuit 4 Parallel-serial conversion shift register (1)
5,9 Selector circuit 6 Arithmetic circuit 7 Serial-parallel conversion shift register (2)
8 Display data latch circuit (1)
10 Oscillator 11 Display Timing Generation Circuit 12 Display Data Latch Circuit (2)
13 Display data latch circuit (3)
14 level shift circuit 15 DA conversion circuit (grayscale voltage decoding circuit)
16 Output circuit (current amplifier circuit)
17 gradation voltage generation circuit 20 boost clock generation circuit 100 controller circuit 120 liquid crystal drive power generation circuit 130 source driver 140 gate driver 150 memory circuit 151 memory cell 152 X direction control circuit 153 Y direction control circuit 154 multiplexer 155 write circuit 156, 157 Readout circuit PNL Liquid crystal panel S Video line (or drain line)
G Scan line (or gate line)
TFT Thin film transistor ITO1 Pixel electrode ITO2 Common electrode (counter electrode or common electrode)
LC liquid crystal capacitance GLASS glass substrate DRV drive circuit W, W1, W1B, W2, W2B Word line DT, DB Data line M1, M2, M11, M13, M15 N-type MOS transistors M3, M4, M12, M14, M16 P-type MOS Transistors I1 to I4, I11 to I15, INV Inverter node1 and node2 Internal node AMP Operational amplifier NAND NAND circuit Ra and Rb Resistance voltage dividing circuit AMP0, AMP63, AMPa to AMpe Amplifier circuit R Resistance element C1, C2 Capacitance element PIN1, PIN2 Terminal MZ1 , MZ2, MZT Transfer gate circuit R Decoder Resistor array

Claims (18)

A display device comprising: a drive circuit to which video data is supplied from the outside; a video line to which a video signal output from the drive circuit is supplied; and a pixel to which the video signal is supplied through the video line. ,
The drive circuit has a memory for storing the video data in a memory cell;
The memory cell of the memory includes a first inverter having an input terminal connected to the first node and an output terminal connected to the second node;
A second inverter having an output terminal connected to the first node and an input terminal connected to the second node;
A first conductivity type first transistor connected between a first data line and the first node and having a control terminal connected to the first word line;
A second transistor of a second conductivity type connected between the first data line and the first node and having a control terminal connected to a third word line;
A third transistor of a first conductivity type connected between a second data line and the second node and having a control terminal connected to the second word line;
A display device having a fourth transistor of a second conductivity type connected between the second data line and the second node and having a control terminal connected to the fourth word line. The display device according to claim 1.
The memory has a control unit,
The control unit turns on the first and second transistors when writing the video data,
A display device for supplying video data to be stored in the memory cell to the first data line. The display device according to claim 1.
The controller turns on the third and fourth transistors when reading the video data,
A display device for supplying video data read from the memory cell to the second data line. The display device according to claim 3.
The memory has storage means for storing video data read from the memory cell supplied to the second data line;
The control unit is a display device that selects video data input from the outside or data stored in the storage unit and supplies the video data to the first data line when the video data is written. The display device according to claim 1.
The second inverter is a clocked inverter;
The clocked inverter is a display device that is turned off when the first and second transistors are turned on. The display device according to claim 1.
The display device in which the video data stored in the memory is video data for partial display. A display device comprising: a drive circuit to which video data is supplied from the outside; a video line to which a video signal output from the drive circuit is supplied; and a pixel to which the video signal is supplied through the video line. ,
The drive circuit includes a memory for storing the video data in a memory cell;
A DA conversion circuit provided between the memory and the video line;
The memory cell of the memory includes a first inverter having an input terminal connected to the first node and an output terminal connected to the second node;
A second inverter having an output terminal connected to the first node and an input terminal connected to the second node;
A first conductivity type first transistor and a second conductivity type second transistor connected between a first data line and the first node;
A first conductivity type third transistor and a second conductivity type fourth transistor connected between a second data line and the second node;
The first and second transistors are turned on when the video data is written, and turned off when the video data is read.
The display device in which the third transistor and the fourth transistor are turned off when the video data is written and turned on when the video data is read. The display device according to claim 7.
The drive circuit has a first path for supplying the video data to the DA converter circuit without going through the memory;
And a second path for supplying the DA conversion circuit via the memory. The display device according to claim 8.
The drive circuit has a gradation voltage generation unit for outputting a plurality of gradation voltages to the DA conversion circuit,
A display device that stops the operation of a part of the circuits of the gradation voltage generation unit when the video data is supplied to the DA conversion circuit via the second path. The display device according to claim 7.
The display device having a first operation state in which the drive circuit supplies the video data to the DA conversion circuit without going through the memory, and a second state in which the video data is stored in the memory. The display device according to claim 10.
The drive circuit has a gradation voltage generation unit for outputting a plurality of gradation voltages to the DA conversion circuit,
A display device that stops the operation of a part of the circuits of the gradation voltage generation unit in the second operation state. The display device according to claim 11.
The gradation voltage generation unit includes a plurality of amplifier circuits that output a gradation reference voltage,
The display device that stops the operation of an amplifier circuit other than the amplifier circuit that outputs the maximum gradation voltage and the minimum gradation voltage among the plurality of amplifier circuits in the second operation state. The display device according to claim 10.
An output circuit between the DA conversion circuit and the video line;
A display device that stops the operation of the output circuit in the second operation state. The display device according to claim 13,
In the second operating state, when the operation of the output circuit is stopped, an analog signal output from the DA converter circuit is supplied as the video signal to the video line without passing through the output circuit. A display device having signal bypassing means. The display device according to claim 13,
In the second operation state, when the operation of the output circuit is stopped, an arbitrary two gradation voltage is supplied to the video line based on arbitrary data input to the DA conversion circuit. A display device having a video signal bypass means. The display device according to claim 14, wherein
A display device that stops the operation of the video signal bypassing means within a period in which data input to the DA converter circuit changes. The display device according to claim 14, wherein
A level shift circuit provided for each video data is provided in the preceding stage of the DA conversion circuit,
A display device that stops operation of a level shift circuit for data other than data input to the DA converter circuit when operation of the output circuit is stopped in the second operation state. The display device according to claim 13,
The display device wherein the number of gradations of the pixel in the second operation state is smaller than the number of gradations of the pixel in the first operation state.

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